src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54
  55 typedef struct midgard_branch {
  56         /* If conditional, the condition is specified in r31.w */
  57         bool conditional;
  58
  59         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  60         bool invert_conditional;
  61
  62         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  63         unsigned target_type;
  64
  65         /* The actual target */
  66         union {
  67                 int target_block;
  68                 int target_break;
  69                 int target_continue;
  70         };
  71 } midgard_branch;
  72
  73 #define PAN_WRITEOUT_C 1
  74 #define PAN_WRITEOUT_Z 2
  75 #define PAN_WRITEOUT_S 4
  76
  77 /* Generic in-memory data type repesenting a single logical instruction, rather
  78  * than a single instruction group. This is the preferred form for code gen.
  79  * Multiple midgard_insturctions will later be combined during scheduling,
  80  * though this is not represented in this structure.  Its format bridges
  81  * the low-level binary representation with the higher level semantic meaning.
  82  *
  83  * Notably, it allows registers to be specified as block local SSA, for code
  84  * emitted before the register allocation pass.
  85  */
  86
  87 #define MIR_SRC_COUNT 4
  88 #define MIR_VEC_COMPONENTS 16
  89
  90 typedef struct midgard_instruction {
  91         /* Must be first for casting */
  92         struct list_head link;
  93
  94         unsigned type; /* ALU, load/store, texture */
  95
  96         /* Instruction arguments represented as block-local SSA
  97          * indices, rather than registers. ~0 means unused. */
  98         unsigned src[MIR_SRC_COUNT];
  99         unsigned dest;
 100
 101         /* vec16 swizzle, unpacked, per source */
 102         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
 103
 104         /* Types! */
 105         nir_alu_type src_types[MIR_SRC_COUNT];
 106         nir_alu_type dest_type;
 107
 108         /* Packing ops have non-32-bit dest types even though they functionally
 109          * work at the 32-bit level, use this as a signal to disable copyprop.
 110          * We maybe need synthetic pack ops instead. */
 111         bool is_pack;
 112
 113         /* Modifiers, depending on type */
 114         union {
 115                 struct {
 116                         bool src_abs[MIR_SRC_COUNT];
 117                         bool src_neg[MIR_SRC_COUNT];
 118                 };
 119
 120                 struct {
 121                         bool src_shift[MIR_SRC_COUNT];
 122                 };
 123         };
 124
 125         /* Out of the union for csel (could maybe be fixed..) */
 126         bool src_invert[MIR_SRC_COUNT];
 127
 128         /* If the op supports it */
 129         enum midgard_roundmode roundmode;
 130
 131         /* Special fields for an ALU instruction */
 132         midgard_reg_info registers;
 133
 134         /* For textures: should helpers execute this instruction (instead of
 135          * just helping with derivatives)? Should helpers terminate after? */
 136         bool helper_terminate;
 137         bool helper_execute;
 138
 139         /* I.e. (1 << alu_bit) */
 140         int unit;
 141
 142         bool has_constants;
 143         midgard_constants constants;
 144         uint16_t inline_constant;
 145         bool has_blend_constant;
 146         bool has_inline_constant;
 147
 148         bool compact_branch;
 149         uint8_t writeout;
 150         bool last_writeout;
 151
 152         /* Masks in a saneish format. One bit per channel, not packed fancy.
 153          * Use this instead of the op specific ones, and switch over at emit
 154          * time */
 155
 156         uint16_t mask;
 157
 158         /* Hint for the register allocator not to spill the destination written
 159          * from this instruction (because it is a spill/unspill node itself).
 160          * Bitmask of spilled classes */
 161
 162         unsigned no_spill;
 163
 164         /* Generic hint for intra-pass use */
 165         bool hint;
 166
 167         /* During scheduling, the backwards dependency graph
 168          * (DAG). nr_dependencies is the number of unscheduled
 169          * instructions that must still be scheduled after
 170          * (before) this instruction. dependents are which
 171          * instructions need to be scheduled before (after) this
 172          * instruction. */
 173
 174         unsigned nr_dependencies;
 175         BITSET_WORD *dependents;
 176
 177         union {
 178                 midgard_load_store_word load_store;
 179                 midgard_vector_alu alu;
 180                 midgard_texture_word texture;
 181                 midgard_branch_extended branch_extended;
 182                 uint16_t br_compact;
 183
 184                 /* General branch, rather than packed br_compact. Higher level
 185                  * than the other components */
 186                 midgard_branch branch;
 187         };
 188 } midgard_instruction;
 189
 190 typedef struct midgard_block {
 191         pan_block base;
 192
 193         bool scheduled;
 194
 195         /* List of midgard_bundles emitted (after the scheduler has run) */
 196         struct util_dynarray bundles;
 197
 198         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 199         unsigned quadword_count;
 200
 201         /* Indicates this is a fixed-function fragment epilogue block */
 202         bool epilogue;
 203
 204         /* Are helper invocations required by this block? */
 205         bool helpers_in;
 206 } midgard_block;
 207
 208 typedef struct midgard_bundle {
 209         /* Tag for the overall bundle */
 210         int tag;
 211
 212         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 213          * sadd, vadd, smul, vlut, branch) */
 214         int instruction_count;
 215         midgard_instruction *instructions[6];
 216
 217         /* Bundle-wide ALU configuration */
 218         int padding;
 219         int control;
 220         bool has_embedded_constants;
 221         midgard_constants constants;
 222         bool has_blend_constant;
 223         bool last_writeout;
 224 } midgard_bundle;
 225
 226 enum midgard_rt_id {
 227         MIDGARD_COLOR_RT0,
 228         MIDGARD_COLOR_RT1,
 229         MIDGARD_COLOR_RT2,
 230         MIDGARD_COLOR_RT3,
 231         MIDGARD_ZS_RT,
 232         MIDGARD_NUM_RTS,
 233 };
 234
 235 typedef struct compiler_context {
 236         nir_shader *nir;
 237         gl_shader_stage stage;
 238
 239         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 240         bool is_blend;
 241
 242         /* Render target number for a keyed blend shader. Depends on is_blend */
 243         unsigned blend_rt;
 244
 245         /* Tracking for blend constant patching */
 246         int blend_constant_offset;
 247
 248         /* Number of bytes used for Thread Local Storage */
 249         unsigned tls_size;
 250
 251         /* Count of spills and fills for shaderdb */
 252         unsigned spills;
 253         unsigned fills;
 254
 255         /* Current NIR function */
 256         nir_function *func;
 257
 258         /* Allocated compiler temporary counter */
 259         unsigned temp_alloc;
 260
 261         /* Unordered list of midgard_blocks */
 262         int block_count;
 263         struct list_head blocks;
 264
 265         /* TODO merge with block_count? */
 266         unsigned block_source_count;
 267
 268         /* List of midgard_instructions emitted for the current block */
 269         midgard_block *current_block;
 270
 271         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 272         midgard_block *after_block;
 273
 274         /* The current "depth" of the loop, for disambiguating breaks/continues
 275          * when using nested loops */
 276         int current_loop_depth;
 277
 278         /* Total number of loops for shader-db */
 279         unsigned loop_count;
 280
 281         /* Constants which have been loaded, for later inlining */
 282         struct hash_table_u64 *ssa_constants;
 283
 284         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 285         struct hash_table_u64 *hash_to_temp;
 286         int temp_count;
 287         int max_hash;
 288
 289         /* Set of NIR indices that were already emitted as outmods */
 290         BITSET_WORD *already_emitted;
 291
 292         /* Just the count of the max register used. Higher count => higher
 293          * register pressure */
 294         int work_registers;
 295
 296         /* The number of uniforms allowable for the fast path */
 297         int uniform_cutoff;
 298
 299         /* Count of instructions emitted from NIR overall, across all blocks */
 300         int instruction_count;
 301
 302         /* Alpha ref value passed in */
 303         float alpha_ref;
 304
 305         unsigned quadword_count;
 306
 307         /* Bitmask of valid metadata */
 308         unsigned metadata;
 309
 310         /* Model-specific quirk set */
 311         uint32_t quirks;
 312
 313         /* Writeout instructions for each render target */
 314         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 315
 316         struct panfrost_sysvals sysvals;
 317 } compiler_context;
 318
 319 /* Per-block live_in/live_out */
 320 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 321
 322 /* Helpers for manipulating the above structures (forming the driver IR) */
 323
 324 /* Append instruction to end of current block */
 325
 326 static inline midgard_instruction *
 327 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 328 {
 329         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 330         memcpy(heap, &ins, sizeof(ins));
 331         return heap;
 332 }
 333
 334 static inline midgard_instruction *
 335 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 336 {
 337         midgard_instruction *u = mir_upload_ins(ctx, ins);
 338         list_addtail(&u->link, &ctx->current_block->base.instructions);
 339         return u;
 340 }
 341
 342 static inline struct midgard_instruction *
 343 mir_insert_instruction_before(struct compiler_context *ctx,
 344                               struct midgard_instruction *tag,
 345                               struct midgard_instruction ins)
 346 {
 347         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 348         list_addtail(&u->link, &tag->link);
 349         return u;
 350 }
 351
 352 static inline void
 353 mir_remove_instruction(struct midgard_instruction *ins)
 354 {
 355         list_del(&ins->link);
 356 }
 357
 358 static inline midgard_instruction*
 359 mir_prev_op(struct midgard_instruction *ins)
 360 {
 361         return list_last_entry(&(ins->link), midgard_instruction, link);
 362 }
 363
 364 static inline midgard_instruction*
 365 mir_next_op(struct midgard_instruction *ins)
 366 {
 367         return list_first_entry(&(ins->link), midgard_instruction, link);
 368 }
 369
 370 #define mir_foreach_block(ctx, v) \
 371         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 372
 373 #define mir_foreach_block_from(ctx, from, v) \
 374         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 375
 376 #define mir_foreach_instr_in_block(block, v) \
 377         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 378 #define mir_foreach_instr_in_block_rev(block, v) \
 379         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 380
 381 #define mir_foreach_instr_in_block_safe(block, v) \
 382         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 383
 384 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 385         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 386
 387 #define mir_foreach_instr_in_block_from(block, v, from) \
 388         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 389
 390 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 391         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 392
 393 #define mir_foreach_bundle_in_block(block, v) \
 394         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 395
 396 #define mir_foreach_bundle_in_block_rev(block, v) \
 397         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 398
 399 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 400         midgard_instruction* v; \
 401         signed i = 0; \
 402         mir_foreach_bundle_in_block_rev(block, _bundle) \
 403                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 404                                 i >= 0; \
 405                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 406
 407 #define mir_foreach_instr_global(ctx, v) \
 408         mir_foreach_block(ctx, v_block) \
 409                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 410
 411 #define mir_foreach_instr_global_safe(ctx, v) \
 412         mir_foreach_block(ctx, v_block) \
 413                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 414
 415 /* Based on set_foreach, expanded with automatic type casts */
 416
 417 #define mir_foreach_predecessor(blk, v) \
 418         struct set_entry *_entry_##v; \
 419         struct midgard_block *v; \
 420         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 421                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 422                 _entry_##v != NULL; \
 423                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 424                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 425
 426 #define mir_foreach_src(ins, v) \
 427         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 428
 429 static inline midgard_instruction *
 430 mir_last_in_block(struct midgard_block *block)
 431 {
 432         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 433 }
 434
 435 static inline midgard_block *
 436 mir_get_block(compiler_context *ctx, int idx)
 437 {
 438         struct list_head *lst = &ctx->blocks;
 439
 440         while ((idx--) + 1)
 441                 lst = lst->next;
 442
 443         return (struct midgard_block *) lst;
 444 }
 445
 446 static inline bool
 447 mir_is_alu_bundle(midgard_bundle *bundle)
 448 {
 449         return IS_ALU(bundle->tag);
 450 }
 451
 452 static inline unsigned
 453 make_compiler_temp(compiler_context *ctx)
 454 {
 455         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 456 }
 457
 458 static inline unsigned
 459 make_compiler_temp_reg(compiler_context *ctx)
 460 {
 461         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 462 }
 463
 464 static inline unsigned
 465 nir_ssa_index(nir_ssa_def *ssa)
 466 {
 467         return (ssa->index << 1) | 0;
 468 }
 469
 470 static inline unsigned
 471 nir_src_index(compiler_context *ctx, nir_src *src)
 472 {
 473         if (src->is_ssa)
 474                 return nir_ssa_index(src->ssa);
 475         else {
 476                 assert(!src->reg.indirect);
 477                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 478         }
 479 }
 480
 481 static inline unsigned
 482 nir_dest_index(nir_dest *dst)
 483 {
 484         if (dst->is_ssa)
 485                 return (dst->ssa.index << 1) | 0;
 486         else {
 487                 assert(!dst->reg.indirect);
 488                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 489         }
 490 }
 491
 492
 493
 494 /* MIR manipulation */
 495
 496 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 497 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 498 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 499 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 500 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 501 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 502 bool mir_single_use(compiler_context *ctx, unsigned value);
 503 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 504 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 505 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 506 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 507 uint16_t mir_bytemask(midgard_instruction *ins);
 508 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 509 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 510 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
 511 unsigned mir_components_for_type(nir_alu_type T);
 512
 513 /* MIR printing */
 514
 515 void mir_print_instruction(midgard_instruction *ins);
 516 void mir_print_bundle(midgard_bundle *ctx);
 517 void mir_print_block(midgard_block *block);
 518 void mir_print_shader(compiler_context *ctx);
 519 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 520 bool mir_nontrivial_outmod(midgard_instruction *ins);
 521
 522 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 523 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 524 void mir_flip(midgard_instruction *ins);
 525 void mir_compute_temp_count(compiler_context *ctx);
 526
 527 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 528
 529 /* 'Intrinsic' move for aliasing */
 530
 531 static inline midgard_instruction
 532 v_mov(unsigned src, unsigned dest)
 533 {
 534         midgard_instruction ins = {
 535                 .type = TAG_ALU_4,
 536                 .mask = 0xF,
 537                 .src = { ~0, src, ~0, ~0 },
 538                 .src_types = { 0, nir_type_uint32 },
 539                 .swizzle = SWIZZLE_IDENTITY,
 540                 .dest = dest,
 541                 .dest_type = nir_type_uint32,
 542                 .alu = {
 543                         .op = midgard_alu_op_imov,
 544                         .reg_mode = midgard_reg_mode_32,
 545                         .outmod = midgard_outmod_int_wrap
 546                 },
 547         };
 548
 549         return ins;
 550 }
 551
 552 /* Broad types of register classes so we can handle special
 553  * registers */
 554
 555 #define REG_CLASS_WORK          0
 556 #define REG_CLASS_LDST          1
 557 #define REG_CLASS_TEXR          3
 558 #define REG_CLASS_TEXW          4
 559
 560 /* Like a move, but to thread local storage! */
 561
 562 static inline midgard_instruction
 563 v_load_store_scratch(
 564                 unsigned srcdest,
 565                 unsigned index,
 566                 bool is_store,
 567                 unsigned mask)
 568 {
 569         /* We index by 32-bit vec4s */
 570         unsigned byte = (index * 4 * 4);
 571
 572         midgard_instruction ins = {
 573                 .type = TAG_LOAD_STORE_4,
 574                 .mask = mask,
 575                 .dest_type = nir_type_uint32,
 576                 .dest = ~0,
 577                 .src = { ~0, ~0, ~0, ~0 },
 578                 .swizzle = SWIZZLE_IDENTITY_4,
 579                 .load_store = {
 580                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 581
 582                         /* For register spilling - to thread local storage */
 583                         .arg_1 = 0xEA,
 584                         .arg_2 = 0x1E,
 585                 },
 586
 587                 /* If we spill an unspill, RA goes into an infinite loop */
 588                 .no_spill = (1 << REG_CLASS_WORK)
 589         };
 590
 591         ins.constants.u32[0] = byte;
 592
 593         if (is_store) {
 594                 ins.src[0] = srcdest;
 595                 ins.src_types[0] = nir_type_uint32;
 596
 597                 /* Ensure we are tightly swizzled so liveness analysis is
 598                  * correct */
 599
 600                 for (unsigned i = 0; i < 4; ++i) {
 601                         if (!(mask & (1 << i)))
 602                                 ins.swizzle[0][i] = COMPONENT_X;
 603                 }
 604         } else
 605                 ins.dest = srcdest;
 606
 607         return ins;
 608 }
 609
 610 static inline bool
 611 mir_has_arg(midgard_instruction *ins, unsigned arg)
 612 {
 613         if (!ins)
 614                 return false;
 615
 616         mir_foreach_src(ins, i) {
 617                 if (ins->src[i] == arg)
 618                         return true;
 619         }
 620
 621         return false;
 622 }
 623
 624 /* Scheduling */
 625
 626 void midgard_schedule_program(compiler_context *ctx);
 627
 628 void mir_ra(compiler_context *ctx);
 629 void mir_squeeze_index(compiler_context *ctx);
 630 void mir_lower_special_reads(compiler_context *ctx);
 631 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 632 void mir_compute_liveness(compiler_context *ctx);
 633 void mir_invalidate_liveness(compiler_context *ctx);
 634 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 635
 636 void mir_create_pipeline_registers(compiler_context *ctx);
 637 void midgard_promote_uniforms(compiler_context *ctx);
 638
 639 void
 640 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 641
 642 void
 643 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 644
 645 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 646
 647 void mir_analyze_helper_terminate(compiler_context *ctx);
 648 void mir_analyze_helper_requirements(compiler_context *ctx);
 649
 650 /* Final emission */
 651
 652 void emit_binary_bundle(
 653         compiler_context *ctx,
 654         midgard_block *block,
 655         midgard_bundle *bundle,
 656         struct util_dynarray *emission,
 657         int next_tag);
 658
 659 bool
 660 nir_undef_to_zero(nir_shader *shader);
 661 bool nir_fuse_io_16(nir_shader *shader);
 662
 663 void midgard_nir_lod_errata(nir_shader *shader);
 664
 665 /* Optimizations */
 666
 667 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 668 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 669 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 670 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 671 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 672
 673 #endif