src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54
  55 typedef struct midgard_branch {
  56         /* If conditional, the condition is specified in r31.w */
  57         bool conditional;
  58
  59         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  60         bool invert_conditional;
  61
  62         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  63         unsigned target_type;
  64
  65         /* The actual target */
  66         union {
  67                 int target_block;
  68                 int target_break;
  69                 int target_continue;
  70         };
  71 } midgard_branch;
  72
  73 /* Generic in-memory data type repesenting a single logical instruction, rather
  74  * than a single instruction group. This is the preferred form for code gen.
  75  * Multiple midgard_insturctions will later be combined during scheduling,
  76  * though this is not represented in this structure.  Its format bridges
  77  * the low-level binary representation with the higher level semantic meaning.
  78  *
  79  * Notably, it allows registers to be specified as block local SSA, for code
  80  * emitted before the register allocation pass.
  81  */
  82
  83 #define MIR_SRC_COUNT 4
  84 #define MIR_VEC_COMPONENTS 16
  85
  86 typedef struct midgard_instruction {
  87         /* Must be first for casting */
  88         struct list_head link;
  89
  90         unsigned type; /* ALU, load/store, texture */
  91
  92         /* Instruction arguments represented as block-local SSA
  93          * indices, rather than registers. ~0 means unused. */
  94         unsigned src[MIR_SRC_COUNT];
  95         unsigned dest;
  96
  97         /* vec16 swizzle, unpacked, per source */
  98         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  99
 100         /* Types! */
 101         nir_alu_type src_types[MIR_SRC_COUNT];
 102         nir_alu_type dest_type;
 103
 104         /* Special fields for an ALU instruction */
 105         midgard_reg_info registers;
 106
 107         /* For textures: should helpers execute this instruction (instead of
 108          * just helping with derivatives)? Should helpers terminate after? */
 109         bool helper_terminate;
 110         bool helper_execute;
 111
 112         /* I.e. (1 << alu_bit) */
 113         int unit;
 114
 115         bool has_constants;
 116         midgard_constants constants;
 117         uint16_t inline_constant;
 118         bool has_blend_constant;
 119         bool has_inline_constant;
 120
 121         bool compact_branch;
 122         bool writeout;
 123         bool writeout_depth;
 124         bool writeout_stencil;
 125         bool last_writeout;
 126
 127         /* Masks in a saneish format. One bit per channel, not packed fancy.
 128          * Use this instead of the op specific ones, and switch over at emit
 129          * time */
 130
 131         uint16_t mask;
 132
 133         /* For accepting ALU ops - invert the nth source */
 134         bool src_invert[MIR_SRC_COUNT];
 135
 136         /* Hint for the register allocator not to spill the destination written
 137          * from this instruction (because it is a spill/unspill node itself).
 138          * Bitmask of spilled classes */
 139
 140         unsigned no_spill;
 141
 142         /* Generic hint for intra-pass use */
 143         bool hint;
 144
 145         /* During scheduling, the backwards dependency graph
 146          * (DAG). nr_dependencies is the number of unscheduled
 147          * instructions that must still be scheduled after
 148          * (before) this instruction. dependents are which
 149          * instructions need to be scheduled before (after) this
 150          * instruction. */
 151
 152         unsigned nr_dependencies;
 153         BITSET_WORD *dependents;
 154
 155         /* For load/store ops.. force 64-bit destination */
 156         bool load_64;
 157
 158         union {
 159                 midgard_load_store_word load_store;
 160                 midgard_vector_alu alu;
 161                 midgard_texture_word texture;
 162                 midgard_branch_extended branch_extended;
 163                 uint16_t br_compact;
 164
 165                 /* General branch, rather than packed br_compact. Higher level
 166                  * than the other components */
 167                 midgard_branch branch;
 168         };
 169 } midgard_instruction;
 170
 171 typedef struct midgard_block {
 172         pan_block base;
 173
 174         bool scheduled;
 175
 176         /* List of midgard_bundles emitted (after the scheduler has run) */
 177         struct util_dynarray bundles;
 178
 179         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 180         unsigned quadword_count;
 181
 182         /* Indicates this is a fixed-function fragment epilogue block */
 183         bool epilogue;
 184
 185         /* Are helper invocations required by this block? */
 186         bool helpers_in;
 187 } midgard_block;
 188
 189 typedef struct midgard_bundle {
 190         /* Tag for the overall bundle */
 191         int tag;
 192
 193         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 194          * sadd, vadd, smul, vlut, branch) */
 195         int instruction_count;
 196         midgard_instruction *instructions[6];
 197
 198         /* Bundle-wide ALU configuration */
 199         int padding;
 200         int control;
 201         bool has_embedded_constants;
 202         midgard_constants constants;
 203         bool has_blend_constant;
 204         bool last_writeout;
 205 } midgard_bundle;
 206
 207 enum midgard_rt_id {
 208         MIDGARD_COLOR_RT0,
 209         MIDGARD_COLOR_RT1,
 210         MIDGARD_COLOR_RT2,
 211         MIDGARD_COLOR_RT3,
 212         MIDGARD_ZS_RT,
 213         MIDGARD_NUM_RTS,
 214 };
 215
 216 typedef struct compiler_context {
 217         nir_shader *nir;
 218         gl_shader_stage stage;
 219
 220         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 221         bool is_blend;
 222
 223         /* Render target number for a keyed blend shader. Depends on is_blend */
 224         unsigned blend_rt;
 225
 226         /* Tracking for blend constant patching */
 227         int blend_constant_offset;
 228
 229         /* Number of bytes used for Thread Local Storage */
 230         unsigned tls_size;
 231
 232         /* Count of spills and fills for shaderdb */
 233         unsigned spills;
 234         unsigned fills;
 235
 236         /* Current NIR function */
 237         nir_function *func;
 238
 239         /* Allocated compiler temporary counter */
 240         unsigned temp_alloc;
 241
 242         /* Unordered list of midgard_blocks */
 243         int block_count;
 244         struct list_head blocks;
 245
 246         /* TODO merge with block_count? */
 247         unsigned block_source_count;
 248
 249         /* List of midgard_instructions emitted for the current block */
 250         midgard_block *current_block;
 251
 252         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 253         midgard_block *after_block;
 254
 255         /* The current "depth" of the loop, for disambiguating breaks/continues
 256          * when using nested loops */
 257         int current_loop_depth;
 258
 259         /* Total number of loops for shader-db */
 260         unsigned loop_count;
 261
 262         /* Constants which have been loaded, for later inlining */
 263         struct hash_table_u64 *ssa_constants;
 264
 265         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 266         struct hash_table_u64 *hash_to_temp;
 267         int temp_count;
 268         int max_hash;
 269
 270         /* Set of NIR indices that were already emitted as outmods */
 271         BITSET_WORD *already_emitted;
 272
 273         /* Just the count of the max register used. Higher count => higher
 274          * register pressure */
 275         int work_registers;
 276
 277         /* The number of uniforms allowable for the fast path */
 278         int uniform_cutoff;
 279
 280         /* Count of instructions emitted from NIR overall, across all blocks */
 281         int instruction_count;
 282
 283         /* Alpha ref value passed in */
 284         float alpha_ref;
 285
 286         unsigned quadword_count;
 287
 288         /* Bitmask of valid metadata */
 289         unsigned metadata;
 290
 291         /* Model-specific quirk set */
 292         uint32_t quirks;
 293
 294         /* Writeout instructions for each render target */
 295         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 296
 297         struct panfrost_sysvals sysvals;
 298 } compiler_context;
 299
 300 /* Per-block live_in/live_out */
 301 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 302
 303 /* Helpers for manipulating the above structures (forming the driver IR) */
 304
 305 /* Append instruction to end of current block */
 306
 307 static inline midgard_instruction *
 308 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 309 {
 310         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 311         memcpy(heap, &ins, sizeof(ins));
 312         return heap;
 313 }
 314
 315 static inline midgard_instruction *
 316 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 317 {
 318         midgard_instruction *u = mir_upload_ins(ctx, ins);
 319         list_addtail(&u->link, &ctx->current_block->base.instructions);
 320         return u;
 321 }
 322
 323 static inline struct midgard_instruction *
 324 mir_insert_instruction_before(struct compiler_context *ctx,
 325                               struct midgard_instruction *tag,
 326                               struct midgard_instruction ins)
 327 {
 328         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 329         list_addtail(&u->link, &tag->link);
 330         return u;
 331 }
 332
 333 static inline void
 334 mir_remove_instruction(struct midgard_instruction *ins)
 335 {
 336         list_del(&ins->link);
 337 }
 338
 339 static inline midgard_instruction*
 340 mir_prev_op(struct midgard_instruction *ins)
 341 {
 342         return list_last_entry(&(ins->link), midgard_instruction, link);
 343 }
 344
 345 static inline midgard_instruction*
 346 mir_next_op(struct midgard_instruction *ins)
 347 {
 348         return list_first_entry(&(ins->link), midgard_instruction, link);
 349 }
 350
 351 #define mir_foreach_block(ctx, v) \
 352         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 353
 354 #define mir_foreach_block_from(ctx, from, v) \
 355         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 356
 357 #define mir_foreach_instr_in_block(block, v) \
 358         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 359 #define mir_foreach_instr_in_block_rev(block, v) \
 360         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 361
 362 #define mir_foreach_instr_in_block_safe(block, v) \
 363         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 364
 365 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 366         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 367
 368 #define mir_foreach_instr_in_block_from(block, v, from) \
 369         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 370
 371 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 372         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 373
 374 #define mir_foreach_bundle_in_block(block, v) \
 375         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 376
 377 #define mir_foreach_bundle_in_block_rev(block, v) \
 378         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 379
 380 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 381         midgard_instruction* v; \
 382         signed i = 0; \
 383         mir_foreach_bundle_in_block_rev(block, _bundle) \
 384                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 385                                 i >= 0; \
 386                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 387
 388 #define mir_foreach_instr_global(ctx, v) \
 389         mir_foreach_block(ctx, v_block) \
 390                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 391
 392 #define mir_foreach_instr_global_safe(ctx, v) \
 393         mir_foreach_block(ctx, v_block) \
 394                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 395
 396 /* Based on set_foreach, expanded with automatic type casts */
 397
 398 #define mir_foreach_predecessor(blk, v) \
 399         struct set_entry *_entry_##v; \
 400         struct midgard_block *v; \
 401         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 402                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 403                 _entry_##v != NULL; \
 404                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 405                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 406
 407 #define mir_foreach_src(ins, v) \
 408         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 409
 410 static inline midgard_instruction *
 411 mir_last_in_block(struct midgard_block *block)
 412 {
 413         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 414 }
 415
 416 static inline midgard_block *
 417 mir_get_block(compiler_context *ctx, int idx)
 418 {
 419         struct list_head *lst = &ctx->blocks;
 420
 421         while ((idx--) + 1)
 422                 lst = lst->next;
 423
 424         return (struct midgard_block *) lst;
 425 }
 426
 427 static inline bool
 428 mir_is_alu_bundle(midgard_bundle *bundle)
 429 {
 430         return IS_ALU(bundle->tag);
 431 }
 432
 433 static inline unsigned
 434 make_compiler_temp(compiler_context *ctx)
 435 {
 436         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 437 }
 438
 439 static inline unsigned
 440 make_compiler_temp_reg(compiler_context *ctx)
 441 {
 442         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 443 }
 444
 445 static inline unsigned
 446 nir_ssa_index(nir_ssa_def *ssa)
 447 {
 448         return (ssa->index << 1) | 0;
 449 }
 450
 451 static inline unsigned
 452 nir_src_index(compiler_context *ctx, nir_src *src)
 453 {
 454         if (src->is_ssa)
 455                 return nir_ssa_index(src->ssa);
 456         else {
 457                 assert(!src->reg.indirect);
 458                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 459         }
 460 }
 461
 462 static inline unsigned
 463 nir_dest_index(nir_dest *dst)
 464 {
 465         if (dst->is_ssa)
 466                 return (dst->ssa.index << 1) | 0;
 467         else {
 468                 assert(!dst->reg.indirect);
 469                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 470         }
 471 }
 472
 473
 474
 475 /* MIR manipulation */
 476
 477 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 478 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 479 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 480 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 481 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 482 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 483 bool mir_single_use(compiler_context *ctx, unsigned value);
 484 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 485 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 486 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 487 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 488 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 489 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 490 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 491 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 492 uint16_t mir_bytemask(midgard_instruction *ins);
 493 uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
 494 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 495 unsigned mir_upper_override(midgard_instruction *ins);
 496
 497 /* MIR printing */
 498
 499 void mir_print_instruction(midgard_instruction *ins);
 500 void mir_print_bundle(midgard_bundle *ctx);
 501 void mir_print_block(midgard_block *block);
 502 void mir_print_shader(compiler_context *ctx);
 503 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 504 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 505 bool mir_nontrivial_outmod(midgard_instruction *ins);
 506
 507 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 508 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 509 void mir_flip(midgard_instruction *ins);
 510 void mir_compute_temp_count(compiler_context *ctx);
 511
 512 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 513
 514 /* 'Intrinsic' move for aliasing */
 515
 516 static inline midgard_instruction
 517 v_mov(unsigned src, unsigned dest)
 518 {
 519         midgard_instruction ins = {
 520                 .type = TAG_ALU_4,
 521                 .mask = 0xF,
 522                 .src = { ~0, src, ~0, ~0 },
 523                 .src_types = { 0, nir_type_uint32 },
 524                 .swizzle = SWIZZLE_IDENTITY,
 525                 .dest = dest,
 526                 .dest_type = nir_type_uint32,
 527                 .alu = {
 528                         .op = midgard_alu_op_imov,
 529                         .reg_mode = midgard_reg_mode_32,
 530                         .dest_override = midgard_dest_override_none,
 531                         .outmod = midgard_outmod_int_wrap
 532                 },
 533         };
 534
 535         return ins;
 536 }
 537
 538 /* Broad types of register classes so we can handle special
 539  * registers */
 540
 541 #define REG_CLASS_WORK          0
 542 #define REG_CLASS_LDST          1
 543 #define REG_CLASS_TEXR          3
 544 #define REG_CLASS_TEXW          4
 545
 546 /* Like a move, but to thread local storage! */
 547
 548 static inline midgard_instruction
 549 v_load_store_scratch(
 550                 unsigned srcdest,
 551                 unsigned index,
 552                 bool is_store,
 553                 unsigned mask)
 554 {
 555         /* We index by 32-bit vec4s */
 556         unsigned byte = (index * 4 * 4);
 557
 558         midgard_instruction ins = {
 559                 .type = TAG_LOAD_STORE_4,
 560                 .mask = mask,
 561                 .dest = ~0,
 562                 .src = { ~0, ~0, ~0, ~0 },
 563                 .swizzle = SWIZZLE_IDENTITY_4,
 564                 .load_store = {
 565                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 566
 567                         /* For register spilling - to thread local storage */
 568                         .arg_1 = 0xEA,
 569                         .arg_2 = 0x1E,
 570                 },
 571
 572                 /* If we spill an unspill, RA goes into an infinite loop */
 573                 .no_spill = (1 << REG_CLASS_WORK)
 574         };
 575
 576         ins.constants.u32[0] = byte;
 577
 578         if (is_store) {
 579                 ins.src[0] = srcdest;
 580
 581                 /* Ensure we are tightly swizzled so liveness analysis is
 582                  * correct */
 583
 584                 for (unsigned i = 0; i < 4; ++i) {
 585                         if (!(mask & (1 << i)))
 586                                 ins.swizzle[0][i] = COMPONENT_X;
 587                 }
 588         } else
 589                 ins.dest = srcdest;
 590
 591         return ins;
 592 }
 593
 594 static inline bool
 595 mir_has_arg(midgard_instruction *ins, unsigned arg)
 596 {
 597         if (!ins)
 598                 return false;
 599
 600         mir_foreach_src(ins, i) {
 601                 if (ins->src[i] == arg)
 602                         return true;
 603         }
 604
 605         return false;
 606 }
 607
 608 /* Scheduling */
 609
 610 void midgard_schedule_program(compiler_context *ctx);
 611
 612 void mir_ra(compiler_context *ctx);
 613 void mir_squeeze_index(compiler_context *ctx);
 614 void mir_lower_special_reads(compiler_context *ctx);
 615 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 616 void mir_compute_liveness(compiler_context *ctx);
 617 void mir_invalidate_liveness(compiler_context *ctx);
 618 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 619
 620 void mir_create_pipeline_registers(compiler_context *ctx);
 621 void midgard_promote_uniforms(compiler_context *ctx);
 622
 623 void
 624 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 625
 626 void
 627 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 628
 629 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 630
 631 void mir_analyze_helper_terminate(compiler_context *ctx);
 632 void mir_analyze_helper_requirements(compiler_context *ctx);
 633
 634 /* Final emission */
 635
 636 void emit_binary_bundle(
 637         compiler_context *ctx,
 638         midgard_bundle *bundle,
 639         struct util_dynarray *emission,
 640         int next_tag);
 641
 642 bool
 643 nir_undef_to_zero(nir_shader *shader);
 644
 645 void midgard_nir_lod_errata(nir_shader *shader);
 646
 647 /* Optimizations */
 648
 649 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 650 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 651 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 652 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 653 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 654 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 655
 656 #endif