2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
32 #include "util/hash_table.h"
33 #include "util/u_dynarray.h"
35 #include "util/list.h"
37 #include "main/mtypes.h"
38 #include "compiler/nir_types.h"
39 #include "compiler/nir/nir.h"
44 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
45 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
46 * instruction is actually a discard op. */
49 #define TARGET_BREAK 1
50 #define TARGET_CONTINUE 2
51 #define TARGET_DISCARD 3
53 typedef struct midgard_branch
{
54 /* If conditional, the condition is specified in r31.w */
57 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
58 bool invert_conditional
;
60 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
63 /* The actual target */
71 /* Generic in-memory data type repesenting a single logical instruction, rather
72 * than a single instruction group. This is the preferred form for code gen.
73 * Multiple midgard_insturctions will later be combined during scheduling,
74 * though this is not represented in this structure. Its format bridges
75 * the low-level binary representation with the higher level semantic meaning.
77 * Notably, it allows registers to be specified as block local SSA, for code
78 * emitted before the register allocation pass.
81 #define MIR_SRC_COUNT 3
82 #define MIR_VEC_COMPONENTS 16
84 typedef struct midgard_instruction
{
85 /* Must be first for casting */
86 struct list_head link
;
88 unsigned type
; /* ALU, load/store, texture */
90 /* Instruction arguments represented as block-local SSA
91 * indices, rather than registers. ~0 means unused. */
95 /* vec16 swizzle, unpacked, per source */
96 unsigned swizzle
[MIR_SRC_COUNT
][MIR_VEC_COMPONENTS
];
98 /* Special fields for an ALU instruction */
99 midgard_reg_info registers
;
101 /* I.e. (1 << alu_bit) */
105 uint32_t constants
[4];
106 uint16_t inline_constant
;
107 bool has_blend_constant
;
108 bool has_inline_constant
;
112 bool prepacked_branch
;
114 /* Kind of a hack, but hint against aggressive DCE */
117 /* Masks in a saneish format. One bit per channel, not packed fancy.
118 * Use this instead of the op specific ones, and switch over at emit
123 /* For ALU ops only: set to true to invert (bitwise NOT) the
124 * destination of an integer-out op. Not imeplemented in hardware but
125 * allows more optimizations */
129 /* Hint for the register allocator not to spill the destination written
130 * from this instruction (because it is a spill/unspill node itself) */
134 /* Generic hint for intra-pass use */
137 /* During scheduling, the backwards dependency graph
138 * (DAG). nr_dependencies is the number of unscheduled
139 * instructions that must still be scheduled after
140 * (before) this instruction. dependents are which
141 * instructions need to be scheduled before (after) this
144 unsigned nr_dependencies
;
145 BITSET_WORD
*dependents
;
148 midgard_load_store_word load_store
;
149 midgard_vector_alu alu
;
150 midgard_texture_word texture
;
151 midgard_branch_extended branch_extended
;
154 /* General branch, rather than packed br_compact. Higher level
155 * than the other components */
156 midgard_branch branch
;
158 } midgard_instruction
;
160 typedef struct midgard_block
{
161 /* Link to next block. Must be first for mir_get_block */
162 struct list_head link
;
164 /* List of midgard_instructions emitted for the current block */
165 struct list_head instructions
;
167 /* Index of the block in source order */
172 /* List of midgard_bundles emitted (after the scheduler has run) */
173 struct util_dynarray bundles
;
175 /* Number of quadwords _actually_ emitted, as determined after scheduling */
176 unsigned quadword_count
;
178 /* Succeeding blocks. The compiler should not necessarily rely on
179 * source-order traversal */
180 struct midgard_block
*successors
[2];
181 unsigned nr_successors
;
183 struct set
*predecessors
;
185 /* The successors pointer form a graph, and in the case of
186 * complex control flow, this graph has a cycles. To aid
187 * traversal during liveness analysis, we have a visited?
188 * boolean for passes to use as they see fit, provided they
192 /* In liveness analysis, these are live masks (per-component) for
193 * indices for the block. Scalar compilers have the luxury of using
194 * simple bit fields, but for us, liveness is a vector idea. */
199 typedef struct midgard_bundle
{
200 /* Tag for the overall bundle */
203 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
204 * sadd, vadd, smul, vlut, branch) */
205 int instruction_count
;
206 midgard_instruction
*instructions
[6];
208 /* Bundle-wide ALU configuration */
211 bool has_embedded_constants
;
213 bool has_blend_constant
;
216 typedef struct compiler_context
{
218 gl_shader_stage stage
;
220 /* The screen we correspond to */
221 struct midgard_screen
*screen
;
223 /* Is internally a blend shader? Depends on stage == FRAGMENT */
226 /* Tracking for blend constant patching */
227 int blend_constant_offset
;
229 /* Number of bytes used for Thread Local Storage */
232 /* Count of spills and fills for shaderdb */
236 /* Current NIR function */
239 /* Allocated compiler temporary counter */
242 /* Unordered list of midgard_blocks */
244 struct list_head blocks
;
246 /* TODO merge with block_count? */
247 unsigned block_source_count
;
249 /* List of midgard_instructions emitted for the current block */
250 midgard_block
*current_block
;
252 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
253 midgard_block
*after_block
;
255 /* The current "depth" of the loop, for disambiguating breaks/continues
256 * when using nested loops */
257 int current_loop_depth
;
259 /* Total number of loops for shader-db */
262 /* Constants which have been loaded, for later inlining */
263 struct hash_table_u64
*ssa_constants
;
265 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
266 struct hash_table_u64
*hash_to_temp
;
270 /* Just the count of the max register used. Higher count => higher
271 * register pressure */
274 /* Used for cont/last hinting. Increase when a tex op is added.
275 * Decrease when a tex op is removed. */
276 int texture_op_count
;
278 /* The number of uniforms allowable for the fast path */
281 /* Count of instructions emitted from NIR overall, across all blocks */
282 int instruction_count
;
284 /* Alpha ref value passed in */
287 unsigned quadword_count
;
289 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
290 unsigned sysvals
[MAX_SYSVAL_COUNT
];
291 unsigned sysval_count
;
292 struct hash_table_u64
*sysval_to_id
;
294 /* Bitmask of valid metadata */
300 /* Per-block live_in/live_out */
301 #define MIDGARD_METADATA_LIVENESS (1 << 0)
303 /* Helpers for manipulating the above structures (forming the driver IR) */
305 /* Append instruction to end of current block */
307 static inline midgard_instruction
*
308 mir_upload_ins(struct compiler_context
*ctx
, struct midgard_instruction ins
)
310 midgard_instruction
*heap
= ralloc(ctx
, struct midgard_instruction
);
311 memcpy(heap
, &ins
, sizeof(ins
));
315 static inline midgard_instruction
*
316 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
318 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
319 list_addtail(&u
->link
, &ctx
->current_block
->instructions
);
323 static inline struct midgard_instruction
*
324 mir_insert_instruction_before(struct compiler_context
*ctx
,
325 struct midgard_instruction
*tag
,
326 struct midgard_instruction ins
)
328 struct midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
329 list_addtail(&u
->link
, &tag
->link
);
334 mir_remove_instruction(struct midgard_instruction
*ins
)
336 list_del(&ins
->link
);
339 static inline midgard_instruction
*
340 mir_prev_op(struct midgard_instruction
*ins
)
342 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
345 static inline midgard_instruction
*
346 mir_next_op(struct midgard_instruction
*ins
)
348 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
351 #define mir_foreach_block(ctx, v) \
352 list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
354 #define mir_foreach_block_from(ctx, from, v) \
355 list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
357 #define mir_foreach_instr(ctx, v) \
358 list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
360 #define mir_foreach_instr_safe(ctx, v) \
361 list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
363 #define mir_foreach_instr_in_block(block, v) \
364 list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
365 #define mir_foreach_instr_in_block_rev(block, v) \
366 list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
368 #define mir_foreach_instr_in_block_safe(block, v) \
369 list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
371 #define mir_foreach_instr_in_block_safe_rev(block, v) \
372 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
374 #define mir_foreach_instr_in_block_from(block, v, from) \
375 list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
377 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
378 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
380 #define mir_foreach_bundle_in_block(block, v) \
381 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
383 #define mir_foreach_bundle_in_block_rev(block, v) \
384 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
386 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
387 midgard_instruction* v; \
389 mir_foreach_bundle_in_block_rev(block, _bundle) \
390 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
392 --i, v = _bundle->instructions[i]) \
394 #define mir_foreach_instr_global(ctx, v) \
395 mir_foreach_block(ctx, v_block) \
396 mir_foreach_instr_in_block(v_block, v)
398 #define mir_foreach_instr_global_safe(ctx, v) \
399 mir_foreach_block(ctx, v_block) \
400 mir_foreach_instr_in_block_safe(v_block, v)
402 #define mir_foreach_successor(blk, v) \
403 struct midgard_block *v; \
404 struct midgard_block **_v; \
405 for (_v = &blk->successors[0], \
407 v != NULL && _v < &blk->successors[2]; \
410 /* Based on set_foreach, expanded with automatic type casts */
412 #define mir_foreach_predecessor(blk, v) \
413 struct set_entry *_entry_##v; \
414 struct midgard_block *v; \
415 for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
416 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
417 _entry_##v != NULL; \
418 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
419 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
421 #define mir_foreach_src(ins, v) \
422 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
424 static inline midgard_instruction
*
425 mir_last_in_block(struct midgard_block
*block
)
427 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
430 static inline midgard_block
*
431 mir_get_block(compiler_context
*ctx
, int idx
)
433 struct list_head
*lst
= &ctx
->blocks
;
438 return (struct midgard_block
*) lst
;
441 static inline midgard_block
*
442 mir_exit_block(struct compiler_context
*ctx
)
444 midgard_block
*last
= list_last_entry(&ctx
->blocks
,
445 struct midgard_block
, link
);
447 /* The last block must be empty logically but contains branch writeout
448 * for fragment shaders */
450 assert(last
->nr_successors
== 0);
456 mir_is_alu_bundle(midgard_bundle
*bundle
)
458 return IS_ALU(bundle
->tag
);
461 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
465 static inline unsigned
466 make_compiler_temp(compiler_context
*ctx
)
468 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
471 static inline unsigned
472 make_compiler_temp_reg(compiler_context
*ctx
)
474 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | IS_REG
;
477 static inline unsigned
478 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
481 return (src
->ssa
->index
<< 1) | 0;
483 assert(!src
->reg
.indirect
);
484 return (src
->reg
.reg
->index
<< 1) | IS_REG
;
488 static inline unsigned
489 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
491 return nir_src_index(ctx
, &src
->src
);
494 static inline unsigned
495 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
498 return (dst
->ssa
.index
<< 1) | 0;
500 assert(!dst
->reg
.indirect
);
501 return (dst
->reg
.reg
->index
<< 1) | IS_REG
;
507 /* MIR manipulation */
509 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
510 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
511 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
512 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
513 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
514 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned *swizzle
);
515 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
516 bool mir_special_index(compiler_context
*ctx
, unsigned idx
);
517 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
518 bool mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
);
519 uint16_t mir_bytemask_of_read_components(midgard_instruction
*ins
, unsigned node
);
520 unsigned mir_ubo_shift(midgard_load_store_op op
);
521 midgard_reg_mode
mir_typesize(midgard_instruction
*ins
);
522 midgard_reg_mode
mir_srcsize(midgard_instruction
*ins
, unsigned i
);
523 unsigned mir_bytes_for_mode(midgard_reg_mode mode
);
524 uint16_t mir_from_bytemask(uint16_t bytemask
, midgard_reg_mode mode
);
525 uint16_t mir_bytemask(midgard_instruction
*ins
);
526 uint16_t mir_round_bytemask_down(uint16_t mask
, midgard_reg_mode mode
);
527 void mir_set_bytemask(midgard_instruction
*ins
, uint16_t bytemask
);
531 void mir_print_instruction(midgard_instruction
*ins
);
532 void mir_print_bundle(midgard_bundle
*ctx
);
533 void mir_print_block(midgard_block
*block
);
534 void mir_print_shader(compiler_context
*ctx
);
535 bool mir_nontrivial_source2_mod(midgard_instruction
*ins
);
536 bool mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
);
537 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
539 void mir_insert_instruction_before_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
540 void mir_insert_instruction_after_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
541 void mir_flip(midgard_instruction
*ins
);
542 void mir_compute_temp_count(compiler_context
*ctx
);
544 /* 'Intrinsic' move for aliasing */
546 static inline midgard_instruction
547 v_mov(unsigned src
, unsigned dest
)
549 midgard_instruction ins
= {
552 .src
= { SSA_UNUSED
, src
, SSA_UNUSED
},
553 .swizzle
= SWIZZLE_IDENTITY
,
556 .op
= midgard_alu_op_imov
,
557 .reg_mode
= midgard_reg_mode_32
,
558 .dest_override
= midgard_dest_override_none
,
559 .outmod
= midgard_outmod_int_wrap
567 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
572 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
573 if (ins
->src
[i
] == arg
)
582 void schedule_program(compiler_context
*ctx
);
584 /* Broad types of register classes so we can handle special
587 #define NR_REG_CLASSES 6
589 #define REG_CLASS_WORK 0
590 #define REG_CLASS_LDST 1
591 #define REG_CLASS_LDST27 2
592 #define REG_CLASS_TEXR 3
593 #define REG_CLASS_TEXW 4
594 #define REG_CLASS_FRAGC 5
596 void mir_lower_special_reads(compiler_context
*ctx
);
597 struct lcra_state
* allocate_registers(compiler_context
*ctx
, bool *spilled
);
598 void install_registers(compiler_context
*ctx
, struct lcra_state
*g
);
599 void mir_liveness_ins_update(uint16_t *live
, midgard_instruction
*ins
, unsigned max
);
600 void mir_compute_liveness(compiler_context
*ctx
);
601 void mir_invalidate_liveness(compiler_context
*ctx
);
602 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
604 void mir_create_pipeline_registers(compiler_context
*ctx
);
607 midgard_promote_uniforms(compiler_context
*ctx
, unsigned promoted_count
);
609 midgard_instruction
*
611 compiler_context
*ctx
,
615 nir_src
*indirect_offset
,
619 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
, unsigned nr_components
);
622 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
625 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
627 bool mir_op_computes_derivatives(unsigned op
);
631 void emit_binary_bundle(
632 compiler_context
*ctx
,
633 midgard_bundle
*bundle
,
634 struct util_dynarray
*emission
,
638 nir_undef_to_zero(nir_shader
*shader
);
642 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
643 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
644 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
645 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
);
646 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);
648 void midgard_lower_invert(compiler_context
*ctx
, midgard_block
*block
);
649 bool midgard_opt_not_propagate(compiler_context
*ctx
, midgard_block
*block
);
650 bool midgard_opt_fuse_src_invert(compiler_context
*ctx
, midgard_block
*block
);
651 bool midgard_opt_fuse_dest_invert(compiler_context
*ctx
, midgard_block
*block
);
652 bool midgard_opt_csel_invert(compiler_context
*ctx
, midgard_block
*block
);
653 bool midgard_opt_promote_fmov(compiler_context
*ctx
, midgard_block
*block
);