src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Generic in-memory data type repesenting a single logical instruction, rather
  71  * than a single instruction group. This is the preferred form for code gen.
  72  * Multiple midgard_insturctions will later be combined during scheduling,
  73  * though this is not represented in this structure.  Its format bridges
  74  * the low-level binary representation with the higher level semantic meaning.
  75  *
  76  * Notably, it allows registers to be specified as block local SSA, for code
  77  * emitted before the register allocation pass.
  78  */
  79
  80 typedef struct midgard_instruction {
  81         /* Must be first for casting */
  82         struct list_head link;
  83
  84         unsigned type; /* ALU, load/store, texture */
  85
  86         /* Instruction arguments represented as block-local SSA
  87          * indices, rather than registers. ~0 means unused. */
  88         unsigned src[3];
  89         unsigned dest;
  90
  91         /* Swizzle for the conditional for a csel/branch */
  92         unsigned cond_swizzle;
  93
  94         /* Special fields for an ALU instruction */
  95         midgard_reg_info registers;
  96
  97         /* I.e. (1 << alu_bit) */
  98         int unit;
  99
 100         bool has_constants;
 101         uint32_t constants[4];
 102         uint16_t inline_constant;
 103         bool has_blend_constant;
 104         bool has_inline_constant;
 105
 106         bool compact_branch;
 107         bool writeout;
 108         bool prepacked_branch;
 109
 110         /* Kind of a hack, but hint against aggressive DCE */
 111         bool dont_eliminate;
 112
 113         /* Masks in a saneish format. One bit per channel, not packed fancy.
 114          * Use this instead of the op specific ones, and switch over at emit
 115          * time */
 116
 117         uint16_t mask;
 118
 119         /* For ALU ops only: set to true to invert (bitwise NOT) the
 120          * destination of an integer-out op. Not imeplemented in hardware but
 121          * allows more optimizations */
 122
 123         bool invert;
 124
 125         /* Hint for the register allocator not to spill the destination written
 126          * from this instruction (because it is a spill/unspill node itself) */
 127
 128         bool no_spill;
 129
 130         /* Generic hint for intra-pass use */
 131         bool hint;
 132
 133         /* During scheduling, the backwards dependency graph
 134          * (DAG). nr_dependencies is the number of unscheduled
 135          * instructions that must still be scheduled after
 136          * (before) this instruction. dependents are which
 137          * instructions need to be scheduled before (after) this
 138          * instruction. */
 139
 140         unsigned nr_dependencies;
 141         BITSET_WORD *dependents;
 142
 143         union {
 144                 midgard_load_store_word load_store;
 145                 midgard_vector_alu alu;
 146                 midgard_texture_word texture;
 147                 midgard_branch_extended branch_extended;
 148                 uint16_t br_compact;
 149
 150                 /* General branch, rather than packed br_compact. Higher level
 151                  * than the other components */
 152                 midgard_branch branch;
 153         };
 154 } midgard_instruction;
 155
 156 typedef struct midgard_block {
 157         /* Link to next block. Must be first for mir_get_block */
 158         struct list_head link;
 159
 160         /* List of midgard_instructions emitted for the current block */
 161         struct list_head instructions;
 162
 163         /* Index of the block in source order */
 164         unsigned source_id;
 165
 166         bool is_scheduled;
 167
 168         /* List of midgard_bundles emitted (after the scheduler has run) */
 169         struct util_dynarray bundles;
 170
 171         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 172         unsigned quadword_count;
 173
 174         /* Succeeding blocks. The compiler should not necessarily rely on
 175          * source-order traversal */
 176         struct midgard_block *successors[2];
 177         unsigned nr_successors;
 178
 179         struct set *predecessors;
 180
 181         /* The successors pointer form a graph, and in the case of
 182          * complex control flow, this graph has a cycles. To aid
 183          * traversal during liveness analysis, we have a visited?
 184          * boolean for passes to use as they see fit, provided they
 185          * clean up later */
 186         bool visited;
 187
 188         /* In liveness analysis, these are live masks (per-component) for
 189          * indices for the block. Scalar compilers have the luxury of using
 190          * simple bit fields, but for us, liveness is a vector idea. */
 191         uint16_t *live_in;
 192         uint16_t *live_out;
 193 } midgard_block;
 194
 195 typedef struct midgard_bundle {
 196         /* Tag for the overall bundle */
 197         int tag;
 198
 199         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 200          * sadd, vadd, smul, vlut, branch) */
 201         int instruction_count;
 202         midgard_instruction *instructions[6];
 203
 204         /* Bundle-wide ALU configuration */
 205         int padding;
 206         int control;
 207         bool has_embedded_constants;
 208         float constants[4];
 209         bool has_blend_constant;
 210 } midgard_bundle;
 211
 212 typedef struct compiler_context {
 213         nir_shader *nir;
 214         gl_shader_stage stage;
 215
 216         /* The screen we correspond to */
 217         struct midgard_screen *screen;
 218
 219         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 220         bool is_blend;
 221
 222         /* Tracking for blend constant patching */
 223         int blend_constant_offset;
 224
 225         /* Number of bytes used for Thread Local Storage */
 226         unsigned tls_size;
 227
 228         /* Count of spills and fills for shaderdb */
 229         unsigned spills;
 230         unsigned fills;
 231
 232         /* Current NIR function */
 233         nir_function *func;
 234
 235         /* Allocated compiler temporary counter */
 236         unsigned temp_alloc;
 237
 238         /* Unordered list of midgard_blocks */
 239         int block_count;
 240         struct list_head blocks;
 241
 242         /* TODO merge with block_count? */
 243         unsigned block_source_count;
 244
 245         /* List of midgard_instructions emitted for the current block */
 246         midgard_block *current_block;
 247
 248         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 249         midgard_block *after_block;
 250
 251         /* The current "depth" of the loop, for disambiguating breaks/continues
 252          * when using nested loops */
 253         int current_loop_depth;
 254
 255         /* Total number of loops for shader-db */
 256         unsigned loop_count;
 257
 258         /* Constants which have been loaded, for later inlining */
 259         struct hash_table_u64 *ssa_constants;
 260
 261         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 262         struct hash_table_u64 *hash_to_temp;
 263         int temp_count;
 264         int max_hash;
 265
 266         /* Just the count of the max register used. Higher count => higher
 267          * register pressure */
 268         int work_registers;
 269
 270         /* Used for cont/last hinting. Increase when a tex op is added.
 271          * Decrease when a tex op is removed. */
 272         int texture_op_count;
 273
 274         /* The number of uniforms allowable for the fast path */
 275         int uniform_cutoff;
 276
 277         /* Count of instructions emitted from NIR overall, across all blocks */
 278         int instruction_count;
 279
 280         /* Alpha ref value passed in */
 281         float alpha_ref;
 282
 283         unsigned quadword_count;
 284
 285         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 286         unsigned sysvals[MAX_SYSVAL_COUNT];
 287         unsigned sysval_count;
 288         struct hash_table_u64 *sysval_to_id;
 289
 290         /* Bitmask of valid metadata */
 291         unsigned metadata;
 292 } compiler_context;
 293
 294 /* Per-block live_in/live_out */
 295 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 296
 297 /* Helpers for manipulating the above structures (forming the driver IR) */
 298
 299 /* Append instruction to end of current block */
 300
 301 static inline midgard_instruction *
 302 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 303 {
 304         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 305         memcpy(heap, &ins, sizeof(ins));
 306         return heap;
 307 }
 308
 309 static inline midgard_instruction *
 310 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 311 {
 312         midgard_instruction *u = mir_upload_ins(ctx, ins);
 313         list_addtail(&u->link, &ctx->current_block->instructions);
 314         return u;
 315 }
 316
 317 static inline struct midgard_instruction *
 318 mir_insert_instruction_before(struct compiler_context *ctx,
 319                               struct midgard_instruction *tag,
 320                               struct midgard_instruction ins)
 321 {
 322         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 323         list_addtail(&u->link, &tag->link);
 324         return u;
 325 }
 326
 327 static inline void
 328 mir_remove_instruction(struct midgard_instruction *ins)
 329 {
 330         list_del(&ins->link);
 331 }
 332
 333 static inline midgard_instruction*
 334 mir_prev_op(struct midgard_instruction *ins)
 335 {
 336         return list_last_entry(&(ins->link), midgard_instruction, link);
 337 }
 338
 339 static inline midgard_instruction*
 340 mir_next_op(struct midgard_instruction *ins)
 341 {
 342         return list_first_entry(&(ins->link), midgard_instruction, link);
 343 }
 344
 345 #define mir_foreach_block(ctx, v) \
 346         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 347
 348 #define mir_foreach_block_from(ctx, from, v) \
 349         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 350
 351 #define mir_foreach_instr(ctx, v) \
 352         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 353
 354 #define mir_foreach_instr_safe(ctx, v) \
 355         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 356
 357 #define mir_foreach_instr_in_block(block, v) \
 358         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 359 #define mir_foreach_instr_in_block_rev(block, v) \
 360         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 361
 362 #define mir_foreach_instr_in_block_safe(block, v) \
 363         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 364
 365 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 366         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 367
 368 #define mir_foreach_instr_in_block_from(block, v, from) \
 369         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 370
 371 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 372         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 373
 374 #define mir_foreach_bundle_in_block(block, v) \
 375         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 376
 377 #define mir_foreach_bundle_in_block_rev(block, v) \
 378         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 379
 380 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 381         midgard_instruction* v; \
 382         signed i = 0; \
 383         mir_foreach_bundle_in_block_rev(block, _bundle) \
 384                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 385                                 i >= 0; \
 386                                 --i, v = _bundle->instructions[i]) \
 387
 388 #define mir_foreach_instr_global(ctx, v) \
 389         mir_foreach_block(ctx, v_block) \
 390                 mir_foreach_instr_in_block(v_block, v)
 391
 392 #define mir_foreach_instr_global_safe(ctx, v) \
 393         mir_foreach_block(ctx, v_block) \
 394                 mir_foreach_instr_in_block_safe(v_block, v)
 395
 396 #define mir_foreach_successor(blk, v) \
 397         struct midgard_block *v; \
 398         struct midgard_block **_v; \
 399         for (_v = &blk->successors[0], \
 400                 v = *_v; \
 401                 v != NULL && _v < &blk->successors[2]; \
 402                 _v++, v = *_v) \
 403
 404 /* Based on set_foreach, expanded with automatic type casts */
 405
 406 #define mir_foreach_predecessor(blk, v) \
 407         struct set_entry *_entry_##v; \
 408         struct midgard_block *v; \
 409         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 410                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 411                 _entry_##v != NULL; \
 412                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 413                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 414
 415 #define mir_foreach_src(ins, v) \
 416         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 417
 418 static inline midgard_instruction *
 419 mir_last_in_block(struct midgard_block *block)
 420 {
 421         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 422 }
 423
 424 static inline midgard_block *
 425 mir_get_block(compiler_context *ctx, int idx)
 426 {
 427         struct list_head *lst = &ctx->blocks;
 428
 429         while ((idx--) + 1)
 430                 lst = lst->next;
 431
 432         return (struct midgard_block *) lst;
 433 }
 434
 435 static inline midgard_block *
 436 mir_exit_block(struct compiler_context *ctx)
 437 {
 438         midgard_block *last = list_last_entry(&ctx->blocks,
 439                         struct midgard_block, link);
 440
 441         /* The last block must be empty logically but contains branch writeout
 442          * for fragment shaders */
 443
 444         assert(last->nr_successors == 0);
 445
 446         return last;
 447 }
 448
 449 static inline bool
 450 mir_is_alu_bundle(midgard_bundle *bundle)
 451 {
 452         return IS_ALU(bundle->tag);
 453 }
 454
 455 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 456
 457 #define IS_REG (1)
 458
 459 static inline unsigned
 460 make_compiler_temp(compiler_context *ctx)
 461 {
 462         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 463 }
 464
 465 static inline unsigned
 466 make_compiler_temp_reg(compiler_context *ctx)
 467 {
 468         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 469 }
 470
 471 static inline unsigned
 472 nir_src_index(compiler_context *ctx, nir_src *src)
 473 {
 474         if (src->is_ssa)
 475                 return (src->ssa->index << 1) | 0;
 476         else {
 477                 assert(!src->reg.indirect);
 478                 return (src->reg.reg->index << 1) | IS_REG;
 479         }
 480 }
 481
 482 static inline unsigned
 483 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 484 {
 485         return nir_src_index(ctx, &src->src);
 486 }
 487
 488 static inline unsigned
 489 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 490 {
 491         if (dst->is_ssa)
 492                 return (dst->ssa.index << 1) | 0;
 493         else {
 494                 assert(!dst->reg.indirect);
 495                 return (dst->reg.reg->index << 1) | IS_REG;
 496         }
 497 }
 498
 499
 500
 501 /* MIR manipulation */
 502
 503 unsigned mir_get_swizzle(midgard_instruction *ins, unsigned idx);
 504 void mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new);
 505 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 506 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 507 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 508 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 509 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 510 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 511 bool mir_single_use(compiler_context *ctx, unsigned value);
 512 bool mir_special_index(compiler_context *ctx, unsigned idx);
 513 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 514 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 515 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 516 unsigned mir_ubo_shift(midgard_load_store_op op);
 517 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 518 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 519 uint16_t mir_bytemask(midgard_instruction *ins);
 520 uint16_t mir_round_bytemask_down(uint16_t mask, midgard_reg_mode mode);
 521
 522 /* MIR printing */
 523
 524 void mir_print_instruction(midgard_instruction *ins);
 525 void mir_print_bundle(midgard_bundle *ctx);
 526 void mir_print_block(midgard_block *block);
 527 void mir_print_shader(compiler_context *ctx);
 528 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 529 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 530 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 531 bool mir_nontrivial_outmod(midgard_instruction *ins);
 532
 533 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 534 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 535 void mir_flip(midgard_instruction *ins);
 536 void mir_compute_temp_count(compiler_context *ctx);
 537
 538 /* MIR goodies */
 539
 540 static const midgard_vector_alu_src blank_alu_src = {
 541         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 542 };
 543
 544 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 545         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 546 };
 547
 548 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 549         .full = true
 550 };
 551
 552 /* Used for encoding the unused source of 1-op instructions */
 553 static const midgard_vector_alu_src zero_alu_src = { 0 };
 554
 555 /* 'Intrinsic' move for aliasing */
 556
 557 static inline midgard_instruction
 558 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 559 {
 560         midgard_instruction ins = {
 561                 .type = TAG_ALU_4,
 562                 .mask = 0xF,
 563                 .src = { SSA_UNUSED, src, SSA_UNUSED },
 564                 .dest = dest,
 565                 .alu = {
 566                         .op = midgard_alu_op_imov,
 567                         .reg_mode = midgard_reg_mode_32,
 568                         .dest_override = midgard_dest_override_none,
 569                         .outmod = midgard_outmod_int_wrap,
 570                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 571                         .src2 = vector_alu_srco_unsigned(mod)
 572                 },
 573         };
 574
 575         return ins;
 576 }
 577
 578 static inline bool
 579 mir_has_arg(midgard_instruction *ins, unsigned arg)
 580 {
 581         if (!ins)
 582                 return false;
 583
 584         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 585                 if (ins->src[i] == arg)
 586                         return true;
 587         }
 588
 589         return false;
 590 }
 591
 592 /* Scheduling */
 593
 594 void schedule_program(compiler_context *ctx);
 595
 596 /* Register allocation */
 597
 598 struct ra_graph;
 599
 600 /* Broad types of register classes so we can handle special
 601  * registers */
 602
 603 #define NR_REG_CLASSES 6
 604
 605 #define REG_CLASS_WORK          0
 606 #define REG_CLASS_LDST          1
 607 #define REG_CLASS_LDST27        2
 608 #define REG_CLASS_TEXR          3
 609 #define REG_CLASS_TEXW          4
 610 #define REG_CLASS_FRAGC         5
 611
 612 void mir_lower_special_reads(compiler_context *ctx);
 613 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 614 void install_registers(compiler_context *ctx, struct ra_graph *g);
 615 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 616 void mir_compute_liveness(compiler_context *ctx);
 617 void mir_invalidate_liveness(compiler_context *ctx);
 618 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 619
 620 void mir_create_pipeline_registers(compiler_context *ctx);
 621
 622 void
 623 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 624
 625 midgard_instruction *
 626 emit_ubo_read(
 627         compiler_context *ctx,
 628         nir_instr *instr,
 629         unsigned dest,
 630         unsigned offset,
 631         nir_src *indirect_offset,
 632         unsigned index);
 633
 634 void
 635 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 636
 637 void
 638 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 639
 640 void
 641 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 642
 643 bool mir_op_computes_derivatives(unsigned op);
 644
 645 /* Final emission */
 646
 647 void emit_binary_bundle(
 648         compiler_context *ctx,
 649         midgard_bundle *bundle,
 650         struct util_dynarray *emission,
 651         int next_tag);
 652
 653 bool
 654 nir_undef_to_zero(nir_shader *shader);
 655
 656 /* Optimizations */
 657
 658 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 659 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 660 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 661 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 662 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 663
 664 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 665 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 666 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 667 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 668 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 669 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 670
 671 #endif