src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54
  55 typedef struct midgard_branch {
  56         /* If conditional, the condition is specified in r31.w */
  57         bool conditional;
  58
  59         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  60         bool invert_conditional;
  61
  62         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  63         unsigned target_type;
  64
  65         /* The actual target */
  66         union {
  67                 int target_block;
  68                 int target_break;
  69                 int target_continue;
  70         };
  71 } midgard_branch;
  72
  73 /* Generic in-memory data type repesenting a single logical instruction, rather
  74  * than a single instruction group. This is the preferred form for code gen.
  75  * Multiple midgard_insturctions will later be combined during scheduling,
  76  * though this is not represented in this structure.  Its format bridges
  77  * the low-level binary representation with the higher level semantic meaning.
  78  *
  79  * Notably, it allows registers to be specified as block local SSA, for code
  80  * emitted before the register allocation pass.
  81  */
  82
  83 #define MIR_SRC_COUNT 4
  84 #define MIR_VEC_COMPONENTS 16
  85
  86 typedef struct midgard_instruction {
  87         /* Must be first for casting */
  88         struct list_head link;
  89
  90         unsigned type; /* ALU, load/store, texture */
  91
  92         /* Instruction arguments represented as block-local SSA
  93          * indices, rather than registers. ~0 means unused. */
  94         unsigned src[MIR_SRC_COUNT];
  95         unsigned dest;
  96
  97         /* vec16 swizzle, unpacked, per source */
  98         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  99
 100         /* Types! */
 101         nir_alu_type src_types[MIR_SRC_COUNT];
 102         nir_alu_type dest_type;
 103
 104         /* Modifiers, depending on type */
 105         union {
 106                 struct {
 107                         bool src_abs[MIR_SRC_COUNT];
 108                         bool src_neg[MIR_SRC_COUNT];
 109                 };
 110
 111                 struct {
 112                         bool src_shift[MIR_SRC_COUNT];
 113                 };
 114         };
 115
 116         /* Out of the union for csel (could maybe be fixed..) */
 117         bool src_invert[MIR_SRC_COUNT];
 118
 119         /* Special fields for an ALU instruction */
 120         midgard_reg_info registers;
 121
 122         /* For textures: should helpers execute this instruction (instead of
 123          * just helping with derivatives)? Should helpers terminate after? */
 124         bool helper_terminate;
 125         bool helper_execute;
 126
 127         /* I.e. (1 << alu_bit) */
 128         int unit;
 129
 130         bool has_constants;
 131         midgard_constants constants;
 132         uint16_t inline_constant;
 133         bool has_blend_constant;
 134         bool has_inline_constant;
 135
 136         bool compact_branch;
 137         bool writeout;
 138         bool writeout_depth;
 139         bool writeout_stencil;
 140         bool last_writeout;
 141
 142         /* Masks in a saneish format. One bit per channel, not packed fancy.
 143          * Use this instead of the op specific ones, and switch over at emit
 144          * time */
 145
 146         uint16_t mask;
 147
 148         /* Hint for the register allocator not to spill the destination written
 149          * from this instruction (because it is a spill/unspill node itself).
 150          * Bitmask of spilled classes */
 151
 152         unsigned no_spill;
 153
 154         /* Generic hint for intra-pass use */
 155         bool hint;
 156
 157         /* During scheduling, the backwards dependency graph
 158          * (DAG). nr_dependencies is the number of unscheduled
 159          * instructions that must still be scheduled after
 160          * (before) this instruction. dependents are which
 161          * instructions need to be scheduled before (after) this
 162          * instruction. */
 163
 164         unsigned nr_dependencies;
 165         BITSET_WORD *dependents;
 166
 167         /* For load/store ops.. force 64-bit destination */
 168         bool load_64;
 169
 170         union {
 171                 midgard_load_store_word load_store;
 172                 midgard_vector_alu alu;
 173                 midgard_texture_word texture;
 174                 midgard_branch_extended branch_extended;
 175                 uint16_t br_compact;
 176
 177                 /* General branch, rather than packed br_compact. Higher level
 178                  * than the other components */
 179                 midgard_branch branch;
 180         };
 181 } midgard_instruction;
 182
 183 typedef struct midgard_block {
 184         pan_block base;
 185
 186         bool scheduled;
 187
 188         /* List of midgard_bundles emitted (after the scheduler has run) */
 189         struct util_dynarray bundles;
 190
 191         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 192         unsigned quadword_count;
 193
 194         /* Indicates this is a fixed-function fragment epilogue block */
 195         bool epilogue;
 196
 197         /* Are helper invocations required by this block? */
 198         bool helpers_in;
 199 } midgard_block;
 200
 201 typedef struct midgard_bundle {
 202         /* Tag for the overall bundle */
 203         int tag;
 204
 205         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 206          * sadd, vadd, smul, vlut, branch) */
 207         int instruction_count;
 208         midgard_instruction *instructions[6];
 209
 210         /* Bundle-wide ALU configuration */
 211         int padding;
 212         int control;
 213         bool has_embedded_constants;
 214         midgard_constants constants;
 215         bool has_blend_constant;
 216         bool last_writeout;
 217 } midgard_bundle;
 218
 219 enum midgard_rt_id {
 220         MIDGARD_COLOR_RT0,
 221         MIDGARD_COLOR_RT1,
 222         MIDGARD_COLOR_RT2,
 223         MIDGARD_COLOR_RT3,
 224         MIDGARD_ZS_RT,
 225         MIDGARD_NUM_RTS,
 226 };
 227
 228 typedef struct compiler_context {
 229         nir_shader *nir;
 230         gl_shader_stage stage;
 231
 232         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 233         bool is_blend;
 234
 235         /* Render target number for a keyed blend shader. Depends on is_blend */
 236         unsigned blend_rt;
 237
 238         /* Tracking for blend constant patching */
 239         int blend_constant_offset;
 240
 241         /* Number of bytes used for Thread Local Storage */
 242         unsigned tls_size;
 243
 244         /* Count of spills and fills for shaderdb */
 245         unsigned spills;
 246         unsigned fills;
 247
 248         /* Current NIR function */
 249         nir_function *func;
 250
 251         /* Allocated compiler temporary counter */
 252         unsigned temp_alloc;
 253
 254         /* Unordered list of midgard_blocks */
 255         int block_count;
 256         struct list_head blocks;
 257
 258         /* TODO merge with block_count? */
 259         unsigned block_source_count;
 260
 261         /* List of midgard_instructions emitted for the current block */
 262         midgard_block *current_block;
 263
 264         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 265         midgard_block *after_block;
 266
 267         /* The current "depth" of the loop, for disambiguating breaks/continues
 268          * when using nested loops */
 269         int current_loop_depth;
 270
 271         /* Total number of loops for shader-db */
 272         unsigned loop_count;
 273
 274         /* Constants which have been loaded, for later inlining */
 275         struct hash_table_u64 *ssa_constants;
 276
 277         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 278         struct hash_table_u64 *hash_to_temp;
 279         int temp_count;
 280         int max_hash;
 281
 282         /* Set of NIR indices that were already emitted as outmods */
 283         BITSET_WORD *already_emitted;
 284
 285         /* Just the count of the max register used. Higher count => higher
 286          * register pressure */
 287         int work_registers;
 288
 289         /* The number of uniforms allowable for the fast path */
 290         int uniform_cutoff;
 291
 292         /* Count of instructions emitted from NIR overall, across all blocks */
 293         int instruction_count;
 294
 295         /* Alpha ref value passed in */
 296         float alpha_ref;
 297
 298         unsigned quadword_count;
 299
 300         /* Bitmask of valid metadata */
 301         unsigned metadata;
 302
 303         /* Model-specific quirk set */
 304         uint32_t quirks;
 305
 306         /* Writeout instructions for each render target */
 307         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 308
 309         struct panfrost_sysvals sysvals;
 310 } compiler_context;
 311
 312 /* Per-block live_in/live_out */
 313 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 314
 315 /* Helpers for manipulating the above structures (forming the driver IR) */
 316
 317 /* Append instruction to end of current block */
 318
 319 static inline midgard_instruction *
 320 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 321 {
 322         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 323         memcpy(heap, &ins, sizeof(ins));
 324         return heap;
 325 }
 326
 327 static inline midgard_instruction *
 328 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 329 {
 330         midgard_instruction *u = mir_upload_ins(ctx, ins);
 331         list_addtail(&u->link, &ctx->current_block->base.instructions);
 332         return u;
 333 }
 334
 335 static inline struct midgard_instruction *
 336 mir_insert_instruction_before(struct compiler_context *ctx,
 337                               struct midgard_instruction *tag,
 338                               struct midgard_instruction ins)
 339 {
 340         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 341         list_addtail(&u->link, &tag->link);
 342         return u;
 343 }
 344
 345 static inline void
 346 mir_remove_instruction(struct midgard_instruction *ins)
 347 {
 348         list_del(&ins->link);
 349 }
 350
 351 static inline midgard_instruction*
 352 mir_prev_op(struct midgard_instruction *ins)
 353 {
 354         return list_last_entry(&(ins->link), midgard_instruction, link);
 355 }
 356
 357 static inline midgard_instruction*
 358 mir_next_op(struct midgard_instruction *ins)
 359 {
 360         return list_first_entry(&(ins->link), midgard_instruction, link);
 361 }
 362
 363 #define mir_foreach_block(ctx, v) \
 364         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 365
 366 #define mir_foreach_block_from(ctx, from, v) \
 367         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 368
 369 #define mir_foreach_instr_in_block(block, v) \
 370         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 371 #define mir_foreach_instr_in_block_rev(block, v) \
 372         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 373
 374 #define mir_foreach_instr_in_block_safe(block, v) \
 375         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 376
 377 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 378         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 379
 380 #define mir_foreach_instr_in_block_from(block, v, from) \
 381         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 382
 383 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 384         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 385
 386 #define mir_foreach_bundle_in_block(block, v) \
 387         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 388
 389 #define mir_foreach_bundle_in_block_rev(block, v) \
 390         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 391
 392 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 393         midgard_instruction* v; \
 394         signed i = 0; \
 395         mir_foreach_bundle_in_block_rev(block, _bundle) \
 396                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 397                                 i >= 0; \
 398                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 399
 400 #define mir_foreach_instr_global(ctx, v) \
 401         mir_foreach_block(ctx, v_block) \
 402                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 403
 404 #define mir_foreach_instr_global_safe(ctx, v) \
 405         mir_foreach_block(ctx, v_block) \
 406                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 407
 408 /* Based on set_foreach, expanded with automatic type casts */
 409
 410 #define mir_foreach_predecessor(blk, v) \
 411         struct set_entry *_entry_##v; \
 412         struct midgard_block *v; \
 413         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 414                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 415                 _entry_##v != NULL; \
 416                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 417                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 418
 419 #define mir_foreach_src(ins, v) \
 420         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 421
 422 static inline midgard_instruction *
 423 mir_last_in_block(struct midgard_block *block)
 424 {
 425         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 426 }
 427
 428 static inline midgard_block *
 429 mir_get_block(compiler_context *ctx, int idx)
 430 {
 431         struct list_head *lst = &ctx->blocks;
 432
 433         while ((idx--) + 1)
 434                 lst = lst->next;
 435
 436         return (struct midgard_block *) lst;
 437 }
 438
 439 static inline bool
 440 mir_is_alu_bundle(midgard_bundle *bundle)
 441 {
 442         return IS_ALU(bundle->tag);
 443 }
 444
 445 static inline unsigned
 446 make_compiler_temp(compiler_context *ctx)
 447 {
 448         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 449 }
 450
 451 static inline unsigned
 452 make_compiler_temp_reg(compiler_context *ctx)
 453 {
 454         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 455 }
 456
 457 static inline unsigned
 458 nir_ssa_index(nir_ssa_def *ssa)
 459 {
 460         return (ssa->index << 1) | 0;
 461 }
 462
 463 static inline unsigned
 464 nir_src_index(compiler_context *ctx, nir_src *src)
 465 {
 466         if (src->is_ssa)
 467                 return nir_ssa_index(src->ssa);
 468         else {
 469                 assert(!src->reg.indirect);
 470                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 471         }
 472 }
 473
 474 static inline unsigned
 475 nir_dest_index(nir_dest *dst)
 476 {
 477         if (dst->is_ssa)
 478                 return (dst->ssa.index << 1) | 0;
 479         else {
 480                 assert(!dst->reg.indirect);
 481                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 482         }
 483 }
 484
 485
 486
 487 /* MIR manipulation */
 488
 489 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 490 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 491 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 492 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 493 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 494 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 495 bool mir_single_use(compiler_context *ctx, unsigned value);
 496 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 497 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 498 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 499 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 500 uint16_t mir_bytemask(midgard_instruction *ins);
 501 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 502 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 503 unsigned mir_upper_override(midgard_instruction *ins);
 504
 505 /* MIR printing */
 506
 507 void mir_print_instruction(midgard_instruction *ins);
 508 void mir_print_bundle(midgard_bundle *ctx);
 509 void mir_print_block(midgard_block *block);
 510 void mir_print_shader(compiler_context *ctx);
 511 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 512 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 513 bool mir_nontrivial_outmod(midgard_instruction *ins);
 514
 515 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 516 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 517 void mir_flip(midgard_instruction *ins);
 518 void mir_compute_temp_count(compiler_context *ctx);
 519
 520 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 521
 522 /* 'Intrinsic' move for aliasing */
 523
 524 static inline midgard_instruction
 525 v_mov(unsigned src, unsigned dest)
 526 {
 527         midgard_instruction ins = {
 528                 .type = TAG_ALU_4,
 529                 .mask = 0xF,
 530                 .src = { ~0, src, ~0, ~0 },
 531                 .src_types = { 0, nir_type_uint32 },
 532                 .swizzle = SWIZZLE_IDENTITY,
 533                 .dest = dest,
 534                 .dest_type = nir_type_uint32,
 535                 .alu = {
 536                         .op = midgard_alu_op_imov,
 537                         .reg_mode = midgard_reg_mode_32,
 538                         .dest_override = midgard_dest_override_none,
 539                         .outmod = midgard_outmod_int_wrap
 540                 },
 541         };
 542
 543         return ins;
 544 }
 545
 546 /* Broad types of register classes so we can handle special
 547  * registers */
 548
 549 #define REG_CLASS_WORK          0
 550 #define REG_CLASS_LDST          1
 551 #define REG_CLASS_TEXR          3
 552 #define REG_CLASS_TEXW          4
 553
 554 /* Like a move, but to thread local storage! */
 555
 556 static inline midgard_instruction
 557 v_load_store_scratch(
 558                 unsigned srcdest,
 559                 unsigned index,
 560                 bool is_store,
 561                 unsigned mask)
 562 {
 563         /* We index by 32-bit vec4s */
 564         unsigned byte = (index * 4 * 4);
 565
 566         midgard_instruction ins = {
 567                 .type = TAG_LOAD_STORE_4,
 568                 .mask = mask,
 569                 .dest_type = nir_type_uint32,
 570                 .dest = ~0,
 571                 .src = { ~0, ~0, ~0, ~0 },
 572                 .swizzle = SWIZZLE_IDENTITY_4,
 573                 .load_store = {
 574                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 575
 576                         /* For register spilling - to thread local storage */
 577                         .arg_1 = 0xEA,
 578                         .arg_2 = 0x1E,
 579                 },
 580
 581                 /* If we spill an unspill, RA goes into an infinite loop */
 582                 .no_spill = (1 << REG_CLASS_WORK)
 583         };
 584
 585         ins.constants.u32[0] = byte;
 586
 587         if (is_store) {
 588                 ins.src[0] = srcdest;
 589                 ins.src_types[0] = nir_type_uint32;
 590
 591                 /* Ensure we are tightly swizzled so liveness analysis is
 592                  * correct */
 593
 594                 for (unsigned i = 0; i < 4; ++i) {
 595                         if (!(mask & (1 << i)))
 596                                 ins.swizzle[0][i] = COMPONENT_X;
 597                 }
 598         } else
 599                 ins.dest = srcdest;
 600
 601         return ins;
 602 }
 603
 604 static inline bool
 605 mir_has_arg(midgard_instruction *ins, unsigned arg)
 606 {
 607         if (!ins)
 608                 return false;
 609
 610         mir_foreach_src(ins, i) {
 611                 if (ins->src[i] == arg)
 612                         return true;
 613         }
 614
 615         return false;
 616 }
 617
 618 /* Scheduling */
 619
 620 void midgard_schedule_program(compiler_context *ctx);
 621
 622 void mir_ra(compiler_context *ctx);
 623 void mir_squeeze_index(compiler_context *ctx);
 624 void mir_lower_special_reads(compiler_context *ctx);
 625 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 626 void mir_compute_liveness(compiler_context *ctx);
 627 void mir_invalidate_liveness(compiler_context *ctx);
 628 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 629
 630 void mir_create_pipeline_registers(compiler_context *ctx);
 631 void midgard_promote_uniforms(compiler_context *ctx);
 632
 633 void
 634 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 635
 636 void
 637 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 638
 639 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 640
 641 void mir_analyze_helper_terminate(compiler_context *ctx);
 642 void mir_analyze_helper_requirements(compiler_context *ctx);
 643
 644 /* Final emission */
 645
 646 void emit_binary_bundle(
 647         compiler_context *ctx,
 648         midgard_bundle *bundle,
 649         struct util_dynarray *emission,
 650         int next_tag);
 651
 652 bool
 653 nir_undef_to_zero(nir_shader *shader);
 654
 655 void midgard_nir_lod_errata(nir_shader *shader);
 656
 657 /* Optimizations */
 658
 659 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 660 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 661 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 662 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 663 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 664
 665 #endif