5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
45 static unsigned *midg_tags
;
46 static bool is_instruction_int
= false;
50 static struct midgard_disasm_stats midg_stats
;
52 /* Prints a short form of the tag for branching, the minimum needed to be
53 * legible and unambiguous */
56 print_tag_short(FILE *fp
, unsigned tag
)
58 switch (midgard_word_types
[tag
]) {
59 case midgard_word_type_texture
:
60 fprintf(fp
, "tex/%X", tag
);
63 case midgard_word_type_load_store
:
67 case midgard_word_type_alu
:
68 fprintf(fp
, "alu%u/%X", midgard_word_size
[tag
], tag
);
72 fprintf(fp
, "%s%X", (tag
> 0) ? "" : "unk", tag
);
78 print_alu_opcode(FILE *fp
, midgard_alu_op op
)
82 if (alu_opcode_props
[op
].name
) {
83 fprintf(fp
, "%s", alu_opcode_props
[op
].name
);
85 int_op
= midgard_is_integer_op(op
);
87 fprintf(fp
, "alu_op_%02X", op
);
89 /* For constant analysis */
90 is_instruction_int
= int_op
;
94 print_ld_st_opcode(FILE *fp
, midgard_load_store_op op
)
96 if (load_store_opcode_props
[op
].name
)
97 fprintf(fp
, "%s", load_store_opcode_props
[op
].name
);
99 fprintf(fp
, "ldst_op_%02X", op
);
102 static bool is_embedded_constant_half
= false;
103 static bool is_embedded_constant_int
= false;
106 prefix_for_bits(unsigned bits
)
120 /* For static analysis to ensure all registers are written at least once before
121 * use along the source code path (TODO: does this break done for complex CF?)
124 uint16_t midg_ever_written
= 0;
127 print_reg(FILE *fp
, unsigned reg
, unsigned bits
)
129 /* Perform basic static analysis for expanding constants correctly */
132 is_embedded_constant_int
= is_instruction_int
;
133 is_embedded_constant_half
= (bits
< 32);
136 unsigned uniform_reg
= 23 - reg
;
137 bool is_uniform
= false;
139 /* For r8-r15, it could be a work or uniform. We distinguish based on
140 * the fact work registers are ALWAYS written before use, but uniform
141 * registers are NEVER written before use. */
143 if ((reg
>= 8 && reg
< 16) && !(midg_ever_written
& (1 << reg
)))
146 /* r16-r23 are always uniform */
148 if (reg
>= 16 && reg
<= 23)
151 /* Update the uniform count appropriately */
154 midg_stats
.uniform_count
=
155 MAX2(uniform_reg
+ 1, midg_stats
.uniform_count
);
157 char prefix
= prefix_for_bits(bits
);
162 fprintf(fp
, "r%u", reg
);
165 static char *outmod_names_float
[4] = {
172 static char *outmod_names_int
[4] = {
179 static char *srcmod_names_int
[4] = {
187 print_outmod(FILE *fp
, unsigned outmod
, bool is_int
)
189 fprintf(fp
, "%s", is_int
? outmod_names_int
[outmod
] :
190 outmod_names_float
[outmod
]);
194 print_quad_word(FILE *fp
, uint32_t *words
, unsigned tabs
)
198 for (i
= 0; i
< 4; i
++)
199 fprintf(fp
, "0x%08X%s ", words
[i
], i
== 3 ? "" : ",");
204 static const char components
[16] = "xyzwefghijklmnop";
206 /* Helper to print 4 chars of a swizzle */
208 print_swizzle_helper(FILE *fp
, unsigned swizzle
, bool upper
)
210 for (unsigned i
= 0; i
< 4; ++i
) {
211 unsigned c
= (swizzle
>> (i
* 2)) & 3;
213 fprintf(fp
, "%c", components
[c
]);
217 /* Helper to print 8 chars of a swizzle, duplicating over */
219 print_swizzle_helper_8(FILE *fp
, unsigned swizzle
, bool upper
)
221 for (unsigned i
= 0; i
< 4; ++i
) {
222 unsigned c
= (swizzle
>> (i
* 2)) & 3;
225 fprintf(fp
, "%c%c", components
[c
], components
[c
+1]);
230 print_swizzle_vec16(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
,
231 midgard_dest_override override
)
235 if (override
== midgard_dest_override_upper
) {
237 fprintf(fp
, " /* rep_high */ ");
239 fprintf(fp
, " /* rep_low */ ");
241 if (!rep_high
&& rep_low
)
242 print_swizzle_helper_8(fp
, swizzle
, true);
244 print_swizzle_helper_8(fp
, swizzle
, false);
246 print_swizzle_helper_8(fp
, swizzle
, rep_high
& 1);
247 print_swizzle_helper_8(fp
, swizzle
, !(rep_low
& 1));
252 print_swizzle_vec8(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
)
256 print_swizzle_helper(fp
, swizzle
, rep_high
& 1);
257 print_swizzle_helper(fp
, swizzle
, !(rep_low
& 1));
261 print_swizzle_vec4(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
)
264 fprintf(fp
, " /* rep_high */ ");
266 fprintf(fp
, " /* rep_low */ ");
268 if (swizzle
== 0xE4) return; /* xyzw */
271 print_swizzle_helper(fp
, swizzle
, 0);
274 print_swizzle_vec2(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
)
277 fprintf(fp
, " /* rep_high */ ");
279 fprintf(fp
, " /* rep_low */ ");
281 if (swizzle
== 0xE4) return; /* XY */
285 for (unsigned i
= 0; i
< 4; i
+= 2) {
286 unsigned a
= (swizzle
>> (i
* 2)) & 3;
287 unsigned b
= (swizzle
>> ((i
+1) * 2)) & 3;
289 /* Normally we're adjacent, but if there's an issue, don't make
293 fprintf(fp
, "[%c%c]", components
[a
], components
[b
]);
295 fprintf(fp
, "%c", components
[a
>> 1]);
296 else if (b
== (a
+ 1))
297 fprintf(fp
, "%c", "XY"[a
>> 1]);
299 fprintf(fp
, "[%c%c]", components
[a
], components
[b
]);
304 bits_for_mode(midgard_reg_mode mode
)
307 case midgard_reg_mode_8
:
309 case midgard_reg_mode_16
:
311 case midgard_reg_mode_32
:
313 case midgard_reg_mode_64
:
316 unreachable("Invalid reg mode");
322 bits_for_mode_halved(midgard_reg_mode mode
, bool half
)
324 unsigned bits
= bits_for_mode(mode
);
333 print_scalar_constant(FILE *fp
, unsigned src_binary
,
334 const midgard_constants
*consts
,
335 midgard_scalar_alu
*alu
)
337 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
340 if (!midgard_is_integer_op(alu
->op
)) {
342 mod
|= MIDGARD_FLOAT_MOD_ABS
;
344 mod
|= MIDGARD_FLOAT_MOD_NEG
;
346 mod
= midgard_int_normal
;
350 mir_print_constant_component(fp
, consts
, src
->component
,
352 midgard_reg_mode_32
: midgard_reg_mode_16
,
353 false, mod
, alu
->op
);
357 print_vector_constants(FILE *fp
, unsigned src_binary
,
358 const midgard_constants
*consts
,
359 midgard_vector_alu
*alu
)
361 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
362 unsigned bits
= bits_for_mode_halved(alu
->reg_mode
, src
->half
);
363 unsigned max_comp
= MIN2((sizeof(*consts
) * 8) / bits
, 8);
364 unsigned comp_mask
, num_comp
= 0;
368 comp_mask
= effective_writemask(alu
, condense_writemask(alu
->mask
, bits
));
369 num_comp
= util_bitcount(comp_mask
);
373 fprintf(fp
, "vec%d(", num_comp
);
377 for (unsigned i
= 0; i
< max_comp
; ++i
) {
378 if (!(comp_mask
& (1 << i
))) continue;
380 unsigned c
= (src
->swizzle
>> (i
* 2)) & 3;
387 mir_print_constant_component(fp
, consts
, c
, alu
->reg_mode
,
388 src
->half
, src
->mod
, alu
->op
);
396 print_vector_src(FILE *fp
, unsigned src_binary
,
397 midgard_reg_mode mode
, unsigned reg
,
398 midgard_dest_override override
, bool is_int
)
400 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
402 /* Modifiers change meaning depending on the op's context */
404 midgard_int_mod int_mod
= src
->mod
;
407 fprintf(fp
, "%s", srcmod_names_int
[int_mod
]);
409 if (src
->mod
& MIDGARD_FLOAT_MOD_NEG
)
412 if (src
->mod
& MIDGARD_FLOAT_MOD_ABS
)
417 unsigned bits
= bits_for_mode_halved(mode
, src
->half
);
418 print_reg(fp
, reg
, bits
);
422 /* When the mode of the instruction is itself 16-bit,
423 * rep_low/high work more or less as expected. But if the mode
424 * is 32-bit and we're stepping down, you only have vec4 and
425 * the meaning shifts to rep_low as higher-half and rep_high is
426 * never seen. TODO: are other modes similar? */
428 if (mode
== midgard_reg_mode_32
) {
430 print_swizzle_helper(fp
, src
->swizzle
, src
->rep_low
);
431 assert(!src
->rep_high
);
433 print_swizzle_vec8(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
);
435 } else if (bits
== 8)
436 print_swizzle_vec16(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, override
);
438 print_swizzle_vec4(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
);
440 print_swizzle_vec2(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
);
442 /* Since we wrapped with a function-looking thing */
444 if (is_int
&& int_mod
== midgard_int_shift
)
445 fprintf(fp
, ") << %u", bits
);
446 else if ((is_int
&& (int_mod
!= midgard_int_normal
))
447 || (!is_int
&& src
->mod
& MIDGARD_FLOAT_MOD_ABS
))
452 decode_vector_imm(unsigned src2_reg
, unsigned imm
)
455 ret
= src2_reg
<< 11;
456 ret
|= (imm
& 0x7) << 8;
457 ret
|= (imm
>> 3) & 0xFF;
462 print_immediate(FILE *fp
, uint16_t imm
)
464 if (is_instruction_int
)
465 fprintf(fp
, "#%u", imm
);
467 fprintf(fp
, "#%g", _mesa_half_to_float(imm
));
471 update_dest(unsigned reg
)
473 /* We should record writes as marking this as a work register. Store
474 * the max register in work_count; we'll add one at the end */
477 midg_stats
.work_count
= MAX2(reg
, midg_stats
.work_count
);
478 midg_ever_written
|= (1 << reg
);
483 print_dest(FILE *fp
, unsigned reg
, midgard_reg_mode mode
, midgard_dest_override override
)
485 /* Depending on the mode and override, we determine the type of
486 * destination addressed. Absent an override, we address just the
487 * type of the operation itself */
489 unsigned bits
= bits_for_mode(mode
);
491 if (override
!= midgard_dest_override_none
)
495 print_reg(fp
, reg
, bits
);
499 print_mask_vec16(FILE *fp
, uint8_t mask
, midgard_dest_override override
)
503 for (unsigned i
= 0; i
< 8; i
++) {
507 components
[i
*2 + 1]);
511 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
512 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
513 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
514 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
515 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
516 * the mask to make it obvious what happened */
519 print_mask(FILE *fp
, uint8_t mask
, unsigned bits
, midgard_dest_override override
)
522 print_mask_vec16(fp
, mask
, override
);
526 /* Skip 'complete' masks */
528 if (override
== midgard_dest_override_none
) {
529 if (bits
>= 32 && mask
== 0xFF) return;
534 else if (mask
== 0xF0) {
543 unsigned skip
= (bits
/ 16);
544 bool uppercase
= bits
> 32;
545 bool tripped
= false;
547 /* To apply an upper destination override, we "shift" the alphabet.
548 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
549 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
551 const char *alphabet
= components
;
553 if (override
== midgard_dest_override_upper
)
554 alphabet
+= (128 / bits
);
556 for (unsigned i
= 0; i
< 8; i
+= skip
) {
557 bool a
= (mask
& (1 << i
)) != 0;
559 for (unsigned j
= 1; j
< skip
; ++j
) {
560 bool dupe
= (mask
& (1 << (i
+ j
))) != 0;
561 tripped
|= (dupe
!= a
);
565 char c
= alphabet
[i
/ skip
];
570 fprintf(fp
, "%c", c
);
575 fprintf(fp
, " /* %X */", mask
);
578 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
579 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
580 * mode as well, but not load/store-style 16-bit mode. */
583 print_mask_4(FILE *fp
, unsigned mask
, bool upper
)
594 for (unsigned i
= 0; i
< 4; ++i
) {
595 bool a
= (mask
& (1 << i
)) != 0;
597 fprintf(fp
, "%c", components
[i
+ (upper
? 4 : 0)]);
602 print_vector_field(FILE *fp
, const char *name
, uint16_t *words
, uint16_t reg_word
,
603 const midgard_constants
*consts
, unsigned tabs
)
605 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
606 midgard_vector_alu
*alu_field
= (midgard_vector_alu
*) words
;
607 midgard_reg_mode mode
= alu_field
->reg_mode
;
608 unsigned override
= alu_field
->dest_override
;
610 /* For now, prefix instruction names with their unit, until we
611 * understand how this works on a deeper level */
612 fprintf(fp
, "%s.", name
);
614 print_alu_opcode(fp
, alu_field
->op
);
616 /* Postfix with the size to disambiguate if necessary */
617 char postfix
= prefix_for_bits(bits_for_mode(mode
));
618 bool size_ambiguous
= override
!= midgard_dest_override_none
;
621 fprintf(fp
, "%c", postfix
? postfix
: 'r');
623 /* Print the outmod, if there is one */
624 print_outmod(fp
, alu_field
->outmod
,
625 midgard_is_integer_out_op(alu_field
->op
));
629 /* Mask denoting status of 8-lanes */
630 uint8_t mask
= alu_field
->mask
;
632 /* First, print the destination */
633 print_dest(fp
, reg_info
->out_reg
, mode
, alu_field
->dest_override
);
635 if (override
!= midgard_dest_override_none
) {
636 bool modeable
= (mode
!= midgard_reg_mode_8
);
637 bool known
= override
!= 0x3; /* Unused value */
639 if (!(modeable
&& known
))
640 fprintf(fp
, "/* do%u */ ", override
);
643 print_mask(fp
, mask
, bits_for_mode(mode
), override
);
647 bool is_int
= midgard_is_integer_op(alu_field
->op
);
649 if (reg_info
->src1_reg
== 26)
650 print_vector_constants(fp
, alu_field
->src1
, consts
, alu_field
);
652 print_vector_src(fp
, alu_field
->src1
, mode
, reg_info
->src1_reg
, override
, is_int
);
656 if (reg_info
->src2_imm
) {
657 uint16_t imm
= decode_vector_imm(reg_info
->src2_reg
, alu_field
->src2
>> 2);
658 print_immediate(fp
, imm
);
659 } else if (reg_info
->src2_reg
== 26) {
660 print_vector_constants(fp
, alu_field
->src2
, consts
, alu_field
);
662 print_vector_src(fp
, alu_field
->src2
, mode
,
663 reg_info
->src2_reg
, override
, is_int
);
666 midg_stats
.instruction_count
++;
671 print_scalar_src(FILE *fp
, unsigned src_binary
, unsigned reg
)
673 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
681 print_reg(fp
, reg
, src
->full
? 32 : 16);
683 unsigned c
= src
->component
;
686 assert((c
& 1) == 0);
690 fprintf(fp
, ".%c", components
[c
]);
698 decode_scalar_imm(unsigned src2_reg
, unsigned imm
)
701 ret
= src2_reg
<< 11;
702 ret
|= (imm
& 3) << 9;
703 ret
|= (imm
& 4) << 6;
704 ret
|= (imm
& 0x38) << 2;
710 print_scalar_field(FILE *fp
, const char *name
, uint16_t *words
, uint16_t reg_word
,
711 const midgard_constants
*consts
, unsigned tabs
)
713 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
714 midgard_scalar_alu
*alu_field
= (midgard_scalar_alu
*) words
;
716 if (alu_field
->unknown
)
717 fprintf(fp
, "scalar ALU unknown bit set\n");
719 fprintf(fp
, "%s.", name
);
720 print_alu_opcode(fp
, alu_field
->op
);
721 print_outmod(fp
, alu_field
->outmod
,
722 midgard_is_integer_out_op(alu_field
->op
));
725 bool full
= alu_field
->output_full
;
726 update_dest(reg_info
->out_reg
);
727 print_reg(fp
, reg_info
->out_reg
, full
? 32 : 16);
728 unsigned c
= alu_field
->output_component
;
731 assert((c
& 1) == 0);
735 fprintf(fp
, ".%c, ", components
[c
]);
737 if (reg_info
->src1_reg
== 26)
738 print_scalar_constant(fp
, alu_field
->src1
, consts
, alu_field
);
740 print_scalar_src(fp
, alu_field
->src1
, reg_info
->src1_reg
);
744 if (reg_info
->src2_imm
) {
745 uint16_t imm
= decode_scalar_imm(reg_info
->src2_reg
,
747 print_immediate(fp
, imm
);
748 } else if (reg_info
->src2_reg
== 26) {
749 print_scalar_constant(fp
, alu_field
->src2
, consts
, alu_field
);
751 print_scalar_src(fp
, alu_field
->src2
, reg_info
->src2_reg
);
753 midg_stats
.instruction_count
++;
758 print_branch_op(FILE *fp
, unsigned op
)
761 case midgard_jmp_writeout_op_branch_uncond
:
762 fprintf(fp
, "uncond.");
765 case midgard_jmp_writeout_op_branch_cond
:
766 fprintf(fp
, "cond.");
769 case midgard_jmp_writeout_op_writeout
:
770 fprintf(fp
, "write.");
773 case midgard_jmp_writeout_op_tilebuffer_pending
:
774 fprintf(fp
, "tilebuffer.");
777 case midgard_jmp_writeout_op_discard
:
778 fprintf(fp
, "discard.");
782 fprintf(fp
, "unk%u.", op
);
788 print_branch_cond(FILE *fp
, int cond
)
791 case midgard_condition_write0
:
792 fprintf(fp
, "write0");
795 case midgard_condition_false
:
796 fprintf(fp
, "false");
799 case midgard_condition_true
:
803 case midgard_condition_always
:
804 fprintf(fp
, "always");
808 fprintf(fp
, "unk%X", cond
);
814 print_compact_branch_writeout_field(FILE *fp
, uint16_t word
)
816 midgard_jmp_writeout_op op
= word
& 0x7;
817 midg_stats
.instruction_count
++;
820 case midgard_jmp_writeout_op_branch_uncond
: {
821 midgard_branch_uncond br_uncond
;
822 memcpy((char *) &br_uncond
, (char *) &word
, sizeof(br_uncond
));
823 fprintf(fp
, "br.uncond ");
825 if (br_uncond
.unknown
!= 1)
826 fprintf(fp
, "unknown:%u, ", br_uncond
.unknown
);
828 if (br_uncond
.offset
>= 0)
831 fprintf(fp
, "%d -> ", br_uncond
.offset
);
832 print_tag_short(fp
, br_uncond
.dest_tag
);
835 return br_uncond
.offset
>= 0;
838 case midgard_jmp_writeout_op_branch_cond
:
839 case midgard_jmp_writeout_op_writeout
:
840 case midgard_jmp_writeout_op_discard
:
842 midgard_branch_cond br_cond
;
843 memcpy((char *) &br_cond
, (char *) &word
, sizeof(br_cond
));
847 print_branch_op(fp
, br_cond
.op
);
848 print_branch_cond(fp
, br_cond
.cond
);
852 if (br_cond
.offset
>= 0)
855 fprintf(fp
, "%d -> ", br_cond
.offset
);
856 print_tag_short(fp
, br_cond
.dest_tag
);
859 return br_cond
.offset
>= 0;
867 print_extended_branch_writeout_field(FILE *fp
, uint8_t *words
, unsigned next
)
869 midgard_branch_extended br
;
870 memcpy((char *) &br
, (char *) words
, sizeof(br
));
874 print_branch_op(fp
, br
.op
);
876 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
878 bool single_channel
= true;
880 for (unsigned i
= 0; i
< 16; i
+= 2) {
881 single_channel
&= (((br
.cond
>> i
) & 0x3) == (br
.cond
& 0x3));
885 print_branch_cond(fp
, br
.cond
& 0x3);
887 fprintf(fp
, "lut%X", br
.cond
);
890 fprintf(fp
, ".unknown%u", br
.unknown
);
897 fprintf(fp
, "%d -> ", br
.offset
);
898 print_tag_short(fp
, br
.dest_tag
);
901 unsigned I
= next
+ br
.offset
* 4;
903 if (midg_tags
[I
] && midg_tags
[I
] != br
.dest_tag
) {
904 fprintf(fp
, "\t/* XXX TAG ERROR: jumping to ");
905 print_tag_short(fp
, br
.dest_tag
);
906 fprintf(fp
, " but tagged ");
907 print_tag_short(fp
, midg_tags
[I
]);
908 fprintf(fp
, " */\n");
911 midg_tags
[I
] = br
.dest_tag
;
913 midg_stats
.instruction_count
++;
914 return br
.offset
>= 0;
918 num_alu_fields_enabled(uint32_t control_word
)
922 if ((control_word
>> 17) & 1)
925 if ((control_word
>> 19) & 1)
928 if ((control_word
>> 21) & 1)
931 if ((control_word
>> 23) & 1)
934 if ((control_word
>> 25) & 1)
941 print_alu_word(FILE *fp
, uint32_t *words
, unsigned num_quad_words
,
942 unsigned tabs
, unsigned next
)
944 uint32_t control_word
= words
[0];
945 uint16_t *beginning_ptr
= (uint16_t *)(words
+ 1);
946 unsigned num_fields
= num_alu_fields_enabled(control_word
);
947 uint16_t *word_ptr
= beginning_ptr
+ num_fields
;
948 unsigned num_words
= 2 + num_fields
;
949 const midgard_constants
*consts
= NULL
;
950 bool branch_forward
= false;
952 if ((control_word
>> 17) & 1)
955 if ((control_word
>> 19) & 1)
958 if ((control_word
>> 21) & 1)
961 if ((control_word
>> 23) & 1)
964 if ((control_word
>> 25) & 1)
967 if ((control_word
>> 26) & 1)
970 if ((control_word
>> 27) & 1)
973 if (num_quad_words
> (num_words
+ 7) / 8) {
974 assert(num_quad_words
== (num_words
+ 15) / 8);
975 //Assume that the extra quadword is constants
976 consts
= (midgard_constants
*)(words
+ (4 * num_quad_words
- 4));
979 if ((control_word
>> 16) & 1)
980 fprintf(fp
, "unknown bit 16 enabled\n");
982 if ((control_word
>> 17) & 1) {
983 print_vector_field(fp
, "vmul", word_ptr
, *beginning_ptr
, consts
, tabs
);
988 if ((control_word
>> 18) & 1)
989 fprintf(fp
, "unknown bit 18 enabled\n");
991 if ((control_word
>> 19) & 1) {
992 print_scalar_field(fp
, "sadd", word_ptr
, *beginning_ptr
, consts
, tabs
);
997 if ((control_word
>> 20) & 1)
998 fprintf(fp
, "unknown bit 20 enabled\n");
1000 if ((control_word
>> 21) & 1) {
1001 print_vector_field(fp
, "vadd", word_ptr
, *beginning_ptr
, consts
, tabs
);
1006 if ((control_word
>> 22) & 1)
1007 fprintf(fp
, "unknown bit 22 enabled\n");
1009 if ((control_word
>> 23) & 1) {
1010 print_scalar_field(fp
, "smul", word_ptr
, *beginning_ptr
, consts
, tabs
);
1015 if ((control_word
>> 24) & 1)
1016 fprintf(fp
, "unknown bit 24 enabled\n");
1018 if ((control_word
>> 25) & 1) {
1019 print_vector_field(fp
, "lut", word_ptr
, *beginning_ptr
, consts
, tabs
);
1023 if ((control_word
>> 26) & 1) {
1024 branch_forward
|= print_compact_branch_writeout_field(fp
, *word_ptr
);
1028 if ((control_word
>> 27) & 1) {
1029 branch_forward
|= print_extended_branch_writeout_field(fp
, (uint8_t *) word_ptr
, next
);
1034 fprintf(fp
, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1035 consts
->u32
[0], consts
->u32
[1],
1036 consts
->u32
[2], consts
->u32
[3]);
1038 return branch_forward
;
1042 print_varying_parameters(FILE *fp
, midgard_load_store_word
*word
)
1044 midgard_varying_parameter param
;
1045 unsigned v
= word
->varying_parameters
;
1046 memcpy(¶m
, &v
, sizeof(param
));
1048 if (param
.is_varying
) {
1049 /* If a varying, there are qualifiers */
1051 fprintf(fp
, ".flat");
1053 if (param
.interpolation
!= midgard_interp_default
) {
1054 if (param
.interpolation
== midgard_interp_centroid
)
1055 fprintf(fp
, ".centroid");
1057 fprintf(fp
, ".interp%d", param
.interpolation
);
1060 if (param
.modifier
!= midgard_varying_mod_none
) {
1061 if (param
.modifier
== midgard_varying_mod_perspective_w
)
1062 fprintf(fp
, ".perspectivew");
1063 else if (param
.modifier
== midgard_varying_mod_perspective_z
)
1064 fprintf(fp
, ".perspectivez");
1066 fprintf(fp
, ".mod%d", param
.modifier
);
1068 } else if (param
.flat
|| param
.interpolation
|| param
.modifier
) {
1069 fprintf(fp
, " /* is_varying not set but varying metadata attached */");
1072 if (param
.zero0
|| param
.zero1
|| param
.zero2
)
1073 fprintf(fp
, " /* zero tripped, %u %u %u */ ", param
.zero0
, param
.zero1
, param
.zero2
);
1077 is_op_varying(unsigned op
)
1080 case midgard_op_st_vary_16
:
1081 case midgard_op_st_vary_32
:
1082 case midgard_op_st_vary_32i
:
1083 case midgard_op_st_vary_32u
:
1084 case midgard_op_ld_vary_16
:
1085 case midgard_op_ld_vary_32
:
1086 case midgard_op_ld_vary_32i
:
1087 case midgard_op_ld_vary_32u
:
1095 is_op_attribute(unsigned op
)
1098 case midgard_op_ld_attr_16
:
1099 case midgard_op_ld_attr_32
:
1100 case midgard_op_ld_attr_32i
:
1101 case midgard_op_ld_attr_32u
:
1109 print_load_store_arg(FILE *fp
, uint8_t arg
, unsigned index
)
1111 /* Try to interpret as a register */
1112 midgard_ldst_register_select sel
;
1113 memcpy(&sel
, &arg
, sizeof(arg
));
1115 /* If unknown is set, we're not sure what this is or how to
1116 * interpret it. But if it's zero, we get it. */
1119 fprintf(fp
, "0x%02X", arg
);
1123 unsigned reg
= REGISTER_LDST_BASE
+ sel
.select
;
1124 char comp
= components
[sel
.component
];
1126 fprintf(fp
, "r%u.%c", reg
, comp
);
1128 /* Only print a shift if it's non-zero. Shifts only make sense for the
1129 * second index. For the first, we're not sure what it means yet */
1133 fprintf(fp
, " << %u", sel
.shift
);
1135 fprintf(fp
, " /* %X */", sel
.shift
);
1140 update_stats(signed *stat
, unsigned address
)
1143 *stat
= MAX2(*stat
, address
+ 1);
1147 print_load_store_instr(FILE *fp
, uint64_t data
,
1150 midgard_load_store_word
*word
= (midgard_load_store_word
*) &data
;
1152 print_ld_st_opcode(fp
, word
->op
);
1154 unsigned address
= word
->address
;
1156 if (is_op_varying(word
->op
)) {
1157 print_varying_parameters(fp
, word
);
1159 /* Do some analysis: check if direct cacess */
1161 if ((word
->arg_2
== 0x1E) && midg_stats
.varying_count
>= 0)
1162 update_stats(&midg_stats
.varying_count
, address
);
1164 midg_stats
.varying_count
= -16;
1165 } else if (is_op_attribute(word
->op
)) {
1166 if ((word
->arg_2
== 0x1E) && midg_stats
.attribute_count
>= 0)
1167 update_stats(&midg_stats
.attribute_count
, address
);
1169 midg_stats
.attribute_count
= -16;
1172 fprintf(fp
, " r%u", word
->reg
+ (OP_IS_STORE(word
->op
) ? 26 : 0));
1173 print_mask_4(fp
, word
->mask
, false);
1175 if (!OP_IS_STORE(word
->op
))
1176 update_dest(word
->reg
);
1178 bool is_ubo
= OP_IS_UBO_READ(word
->op
);
1181 /* UBOs use their own addressing scheme */
1183 int lo
= word
->varying_parameters
>> 7;
1184 int hi
= word
->address
;
1186 /* TODO: Combine fields logically */
1187 address
= (hi
<< 3) | lo
;
1190 fprintf(fp
, ", %u", address
);
1192 print_swizzle_vec4(fp
, word
->swizzle
, false, false);
1197 fprintf(fp
, "ubo%u", word
->arg_1
);
1198 update_stats(&midg_stats
.uniform_buffer_count
, word
->arg_1
);
1200 print_load_store_arg(fp
, word
->arg_1
, 0);
1203 print_load_store_arg(fp
, word
->arg_2
, 1);
1204 fprintf(fp
, " /* %X */\n", word
->varying_parameters
);
1206 midg_stats
.instruction_count
++;
1210 print_load_store_word(FILE *fp
, uint32_t *word
, unsigned tabs
)
1212 midgard_load_store
*load_store
= (midgard_load_store
*) word
;
1214 if (load_store
->word1
!= 3) {
1215 print_load_store_instr(fp
, load_store
->word1
, tabs
);
1218 if (load_store
->word2
!= 3) {
1219 print_load_store_instr(fp
, load_store
->word2
, tabs
);
1224 print_texture_reg_select(FILE *fp
, uint8_t u
, unsigned base
)
1226 midgard_tex_register_select sel
;
1227 memcpy(&sel
, &u
, sizeof(u
));
1232 fprintf(fp
, "r%u", base
+ sel
.select
);
1234 unsigned component
= sel
.component
;
1236 /* Use the upper half in half-reg mode */
1242 fprintf(fp
, ".%c", components
[component
]);
1244 assert(sel
.zero
== 0);
1248 print_texture_format(FILE *fp
, int format
)
1250 /* Act like a modifier */
1254 DEFINE_CASE(MALI_TEX_1D
, "1d");
1255 DEFINE_CASE(MALI_TEX_2D
, "2d");
1256 DEFINE_CASE(MALI_TEX_3D
, "3d");
1257 DEFINE_CASE(MALI_TEX_CUBE
, "cube");
1260 unreachable("Bad format");
1265 midgard_op_has_helpers(unsigned op
, bool gather
)
1271 case TEXTURE_OP_NORMAL
:
1272 case TEXTURE_OP_DFDX
:
1273 case TEXTURE_OP_DFDY
:
1281 print_texture_op(FILE *fp
, unsigned op
, bool gather
)
1283 /* Act like a bare name, like ESSL functions */
1286 fprintf(fp
, "textureGather");
1288 unsigned component
= op
>> 4;
1289 unsigned bottom
= op
& 0xF;
1292 fprintf(fp
, "_unk%u", bottom
);
1294 fprintf(fp
, ".%c", components
[component
]);
1299 DEFINE_CASE(TEXTURE_OP_NORMAL
, "texture");
1300 DEFINE_CASE(TEXTURE_OP_LOD
, "textureLod");
1301 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH
, "texelFetch");
1302 DEFINE_CASE(TEXTURE_OP_BARRIER
, "barrier");
1303 DEFINE_CASE(TEXTURE_OP_DFDX
, "dFdx");
1304 DEFINE_CASE(TEXTURE_OP_DFDY
, "dFdy");
1307 fprintf(fp
, "tex_%X", op
);
1313 texture_op_takes_bias(unsigned op
)
1315 return op
== TEXTURE_OP_NORMAL
;
1319 sampler_type_name(enum mali_sampler_type t
)
1322 case MALI_SAMPLER_FLOAT
:
1324 case MALI_SAMPLER_UNSIGNED
:
1326 case MALI_SAMPLER_SIGNED
:
1335 print_texture_barrier(FILE *fp
, uint32_t *word
)
1337 midgard_texture_barrier_word
*barrier
= (midgard_texture_barrier_word
*) word
;
1339 if (barrier
->type
!= 0x4)
1340 fprintf(fp
, "/* barrier tag %X != 0x4 */ ", barrier
->type
);
1343 fprintf(fp
, "/* cont missing? */");
1346 fprintf(fp
, "/* last missing? */");
1349 fprintf(fp
, "/* zero1 = 0x%X */ ", barrier
->zero1
);
1352 fprintf(fp
, "/* zero2 = 0x%X */ ", barrier
->zero2
);
1355 fprintf(fp
, "/* zero3 = 0x%X */ ", barrier
->zero3
);
1358 fprintf(fp
, "/* zero4 = 0x%X */ ", barrier
->zero4
);
1361 fprintf(fp
, "/* zero4 = 0x%" PRIx64
" */ ", barrier
->zero5
);
1363 fprintf(fp
, " 0x%X\n", barrier
->unknown4
);
1369 print_texture_word(FILE *fp
, uint32_t *word
, unsigned tabs
, unsigned in_reg_base
, unsigned out_reg_base
)
1371 midgard_texture_word
*texture
= (midgard_texture_word
*) word
;
1373 midg_stats
.helper_invocations
|=
1374 midgard_op_has_helpers(texture
->op
, texture
->is_gather
);
1376 /* Broad category of texture operation in question */
1377 print_texture_op(fp
, texture
->op
, texture
->is_gather
);
1379 /* Barriers use a dramatically different code path */
1380 if (texture
->op
== TEXTURE_OP_BARRIER
) {
1381 print_texture_barrier(fp
, word
);
1383 } else if (texture
->type
== 0x4)
1384 fprintf (fp
, "/* nonbarrier had tag 0x4 */ ");
1386 /* Specific format in question */
1387 print_texture_format(fp
, texture
->format
);
1389 /* Instruction "modifiers" parallel the ALU instructions. */
1391 if (texture
->shadow
)
1392 fprintf(fp
, ".shadow");
1395 fprintf(fp
, ".cont");
1398 fprintf(fp
, ".last");
1400 /* Output modifiers are always interpreted floatly */
1401 print_outmod(fp
, texture
->outmod
, false);
1403 fprintf(fp
, " %sr%u", texture
->out_full
? "" : "h",
1404 out_reg_base
+ texture
->out_reg_select
);
1405 print_mask_4(fp
, texture
->mask
, texture
->out_upper
);
1406 assert(!(texture
->out_full
&& texture
->out_upper
));
1409 /* Depending on whether we read from textures directly or indirectly,
1410 * we may be able to update our analysis */
1412 if (texture
->texture_register
) {
1413 fprintf(fp
, "texture[");
1414 print_texture_reg_select(fp
, texture
->texture_handle
, in_reg_base
);
1417 /* Indirect, tut tut */
1418 midg_stats
.texture_count
= -16;
1420 fprintf(fp
, "texture%u, ", texture
->texture_handle
);
1421 update_stats(&midg_stats
.texture_count
, texture
->texture_handle
);
1424 /* Print the type, GL style */
1425 fprintf(fp
, "%csampler", sampler_type_name(texture
->sampler_type
));
1427 if (texture
->sampler_register
) {
1429 print_texture_reg_select(fp
, texture
->sampler_handle
, in_reg_base
);
1432 midg_stats
.sampler_count
= -16;
1434 fprintf(fp
, "%u", texture
->sampler_handle
);
1435 update_stats(&midg_stats
.sampler_count
, texture
->sampler_handle
);
1438 print_swizzle_vec4(fp
, texture
->swizzle
, false, false);
1439 fprintf(fp
, ", %sr%u", texture
->in_reg_full
? "" : "h", in_reg_base
+ texture
->in_reg_select
);
1440 assert(!(texture
->in_reg_full
&& texture
->in_reg_upper
));
1442 /* TODO: integrate with swizzle */
1443 if (texture
->in_reg_upper
)
1446 print_swizzle_vec4(fp
, texture
->in_reg_swizzle
, false, false);
1448 /* There is *always* an offset attached. Of
1449 * course, that offset is just immediate #0 for a
1450 * GLES call that doesn't take an offset. If there
1451 * is a non-negative non-zero offset, this is
1452 * specified in immediate offset mode, with the
1453 * values in the offset_* fields as immediates. If
1454 * this is a negative offset, we instead switch to
1455 * a register offset mode, where the offset_*
1456 * fields become register triplets */
1458 if (texture
->offset_register
) {
1461 bool full
= texture
->offset
& 1;
1462 bool select
= texture
->offset
& 2;
1463 bool upper
= texture
->offset
& 4;
1465 fprintf(fp
, "%sr%u", full
? "" : "h", in_reg_base
+ select
);
1466 assert(!(texture
->out_full
&& texture
->out_upper
));
1468 /* TODO: integrate with swizzle */
1472 print_swizzle_vec4(fp
, texture
->offset
>> 3, false, false);
1475 } else if (texture
->offset
) {
1476 /* Only select ops allow negative immediate offsets, verify */
1478 signed offset_x
= (texture
->offset
& 0xF);
1479 signed offset_y
= ((texture
->offset
>> 4) & 0xF);
1480 signed offset_z
= ((texture
->offset
>> 8) & 0xF);
1482 bool neg_x
= offset_x
< 0;
1483 bool neg_y
= offset_y
< 0;
1484 bool neg_z
= offset_z
< 0;
1485 bool any_neg
= neg_x
|| neg_y
|| neg_z
;
1487 if (any_neg
&& texture
->op
!= TEXTURE_OP_TEXEL_FETCH
)
1488 fprintf(fp
, "/* invalid negative */ ");
1490 /* Regardless, just print the immediate offset */
1492 fprintf(fp
, " + <%d, %d, %d>, ", offset_x
, offset_y
, offset_z
);
1497 char lod_operand
= texture_op_takes_bias(texture
->op
) ? '+' : '=';
1499 if (texture
->lod_register
) {
1500 fprintf(fp
, "lod %c ", lod_operand
);
1501 print_texture_reg_select(fp
, texture
->bias
, in_reg_base
);
1504 if (texture
->bias_int
)
1505 fprintf(fp
, " /* bias_int = 0x%X */", texture
->bias_int
);
1506 } else if (texture
->op
== TEXTURE_OP_TEXEL_FETCH
) {
1507 /* For texel fetch, the int LOD is in the fractional place and
1508 * there is no fraction / possibility of bias. We *always* have
1509 * an explicit LOD, even if it's zero. */
1511 if (texture
->bias_int
)
1512 fprintf(fp
, " /* bias_int = 0x%X */ ", texture
->bias_int
);
1514 fprintf(fp
, "lod = %u, ", texture
->bias
);
1515 } else if (texture
->bias
|| texture
->bias_int
) {
1516 signed bias_int
= texture
->bias_int
;
1517 float bias_frac
= texture
->bias
/ 256.0f
;
1518 float bias
= bias_int
+ bias_frac
;
1520 bool is_bias
= texture_op_takes_bias(texture
->op
);
1521 char sign
= (bias
>= 0.0) ? '+' : '-';
1522 char operand
= is_bias
? sign
: '=';
1524 fprintf(fp
, "lod %c %f, ", operand
, fabsf(bias
));
1529 /* While not zero in general, for these simple instructions the
1530 * following unknowns are zero, so we don't include them */
1532 if (texture
->unknown4
||
1533 texture
->unknownA
||
1534 texture
->unknown8
) {
1535 fprintf(fp
, "// unknown4 = 0x%x\n", texture
->unknown4
);
1536 fprintf(fp
, "// unknownA = 0x%x\n", texture
->unknownA
);
1537 fprintf(fp
, "// unknown8 = 0x%x\n", texture
->unknown8
);
1540 midg_stats
.instruction_count
++;
1543 struct midgard_disasm_stats
1544 disassemble_midgard(FILE *fp
, uint8_t *code
, size_t size
, unsigned gpu_id
, gl_shader_stage stage
)
1546 uint32_t *words
= (uint32_t *) code
;
1547 unsigned num_words
= size
/ 4;
1550 bool branch_forward
= false;
1552 int last_next_tag
= -1;
1556 midg_tags
= calloc(sizeof(midg_tags
[0]), num_words
);
1558 /* Stats for shader-db */
1559 memset(&midg_stats
, 0, sizeof(midg_stats
));
1560 midg_ever_written
= 0;
1562 while (i
< num_words
) {
1563 unsigned tag
= words
[i
] & 0xF;
1564 unsigned next_tag
= (words
[i
] >> 4) & 0xF;
1565 fprintf(fp
, "\t%X -> %X\n", tag
, next_tag
);
1566 unsigned num_quad_words
= midgard_word_size
[tag
];
1568 if (midg_tags
[i
] && midg_tags
[i
] != tag
) {
1569 fprintf(fp
, "\t/* XXX: TAG ERROR branch, got ");
1570 print_tag_short(fp
, tag
);
1571 fprintf(fp
, " expected ");
1572 print_tag_short(fp
, midg_tags
[i
]);
1573 fprintf(fp
, " */\n");
1579 if (last_next_tag
> 1) {
1580 if (last_next_tag
!= tag
) {
1581 fprintf(fp
, "\t/* XXX: TAG ERROR sequence, got ");
1582 print_tag_short(fp
, tag
);
1583 fprintf(fp
, " expected ");
1584 print_tag_short(fp
, last_next_tag
);
1585 fprintf(fp
, " */\n");
1588 /* TODO: Check ALU case */
1591 last_next_tag
= next_tag
;
1593 switch (midgard_word_types
[tag
]) {
1594 case midgard_word_type_texture
: {
1595 bool interpipe_aliasing
=
1596 midgard_get_quirks(gpu_id
) & MIDGARD_INTERPIPE_REG_ALIASING
;
1598 print_texture_word(fp
, &words
[i
], tabs
,
1599 interpipe_aliasing
? 0 : REG_TEX_BASE
,
1600 interpipe_aliasing
? REGISTER_LDST_BASE
: REG_TEX_BASE
);
1604 case midgard_word_type_load_store
:
1605 print_load_store_word(fp
, &words
[i
], tabs
);
1608 case midgard_word_type_alu
:
1609 branch_forward
= print_alu_word(fp
, &words
[i
], num_quad_words
, tabs
, i
+ 4*num_quad_words
);
1611 /* Reset word static analysis state */
1612 is_embedded_constant_half
= false;
1613 is_embedded_constant_int
= false;
1618 fprintf(fp
, "Unknown word type %u:\n", words
[i
] & 0xF);
1620 print_quad_word(fp
, &words
[i
], tabs
);
1625 /* We are parsing per bundle anyway. Add before we start
1626 * breaking out so we don't miss the final bundle. */
1628 midg_stats
.bundle_count
++;
1629 midg_stats
.quadword_count
+= num_quad_words
;
1633 unsigned next
= (words
[i
] & 0xF0) >> 4;
1635 if (i
< num_words
&& next
== 1 && !branch_forward
)
1638 i
+= 4 * num_quad_words
;
1643 /* We computed work_count as max_work_registers, so add one to get the
1644 * count. If no work registers are written, you still have one work
1645 * reported, which is exactly what the hardware expects */
1647 midg_stats
.work_count
++;