src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_LOAD_VARY_F(op) (\
  29                 op == midgard_op_ld_vary_16 || \
  30                 op == midgard_op_ld_vary_32 \
  31         )
  32
  33 #define OP_IS_STORE_VARY(op) (\
  34                 op == midgard_op_st_vary_16 || \
  35                 op == midgard_op_st_vary_32 || \
  36                 op == midgard_op_st_vary_32u || \
  37                 op == midgard_op_st_vary_32i \
  38         )
  39
  40 #define OP_IS_STORE_R26(op) (\
  41                 OP_IS_STORE_VARY(op) || \
  42                 op == midgard_op_st_char || \
  43                 op == midgard_op_st_char2 || \
  44                 op == midgard_op_st_char4 || \
  45                 op == midgard_op_st_short4 || \
  46                 op == midgard_op_st_int4 \
  47         )
  48
  49 #define OP_IS_STORE(op) (\
  50                 OP_IS_STORE_R26(op) \
  51         )
  52
  53 #define OP_IS_PROJECTION(op) ( \
  54                 op == midgard_op_ldst_perspective_division_z || \
  55                 op == midgard_op_ldst_perspective_division_w \
  56         )
  57
  58 #define OP_IS_VEC4_ONLY(op) ( \
  59                 OP_IS_PROJECTION(op) || \
  60                 op == midgard_op_ld_cubemap_coords \
  61         )
  62
  63 #define OP_IS_MOVE(op) ( \
  64                 op == midgard_alu_op_fmov || \
  65                 op == midgard_alu_op_imov \
  66         )
  67
  68 #define OP_IS_UBO_READ(op) ( \
  69                 op == midgard_op_ld_ubo_char  || \
  70                 op == midgard_op_ld_ubo_char2  || \
  71                 op == midgard_op_ld_ubo_char4  || \
  72                 op == midgard_op_ld_ubo_short4  || \
  73                 op == midgard_op_ld_ubo_int4 \
  74         )
  75
  76 #define OP_IS_CSEL(op) ( \
  77                 op == midgard_alu_op_icsel || \
  78                 op == midgard_alu_op_icsel_v || \
  79                 op == midgard_alu_op_fcsel_v || \
  80                 op == midgard_alu_op_fcsel \
  81         )
  82
  83 #define OP_IS_DERIVATIVE(op) ( \
  84                 op == TEXTURE_OP_DFDX || \
  85                 op == TEXTURE_OP_DFDY \
  86         )
  87
  88 /* ALU control words are single bit fields with a lot of space */
  89
  90 #define ALU_ENAB_VEC_MUL  (1 << 17)
  91 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  92 #define ALU_ENAB_VEC_ADD  (1 << 21)
  93 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  94 #define ALU_ENAB_VEC_LUT  (1 << 25)
  95 #define ALU_ENAB_BR_COMPACT (1 << 26)
  96 #define ALU_ENAB_BRANCH   (1 << 27)
  97
  98 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  99
 100 /* Denotes an opcode that takes a vector input with a fixed-number of
 101  * channels, but outputs to only a single output channel, like dot products.
 102  * For these, to determine the effective mask, this quirk can be set. We have
 103  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
 104  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
 105  * make sense (since then why are we quirked?), so that corresponds to "no
 106  * count set" */
 107
 108 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
 109 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
 110
 111 /* For instructions that take a single argument, normally the first argument
 112  * slot is used for the argument and the second slot is a dummy #0 constant.
 113  * However, there are exceptions: instructions like fmov store their argument
 114  * in the _second_ slot and store a dummy r24 in the first slot, designated by
 115  * QUIRK_FLIPPED_R24 */
 116
 117 #define QUIRK_FLIPPED_R24 (1 << 2)
 118
 119 /* Is the op commutative? */
 120 #define OP_COMMUTES (1 << 3)
 121
 122 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 123 #define OP_TYPE_CONVERT (1 << 4)
 124
 125 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 126  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 127
 128 #define UNIT_MUL 0
 129 #define UNIT_ADD 1
 130 #define UNIT_LUT 2
 131
 132 /* 4-bit type tags */
 133
 134 #define TAG_TEXTURE_4_VTX 0x2
 135 #define TAG_TEXTURE_4 0x3
 136 #define TAG_LOAD_STORE_4 0x5
 137 #define TAG_ALU_4 0x8
 138 #define TAG_ALU_8 0x9
 139 #define TAG_ALU_12 0xA
 140 #define TAG_ALU_16 0xB
 141
 142 static inline int
 143 quadword_size(int tag)
 144 {
 145         switch (tag) {
 146         case TAG_ALU_4:
 147         case TAG_LOAD_STORE_4:
 148         case TAG_TEXTURE_4:
 149         case TAG_TEXTURE_4_VTX:
 150                 return 1;
 151         case TAG_ALU_8:
 152                 return 2;
 153         case TAG_ALU_12:
 154                 return 3;
 155         case TAG_ALU_16:
 156                 return 4;
 157         default:
 158                 unreachable("Unknown tag");
 159         }
 160 }
 161
 162 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 ||  \
 163                      tag == TAG_ALU_12 || tag == TAG_ALU_16)
 164
 165 /* Special register aliases */
 166
 167 #define MAX_WORK_REGISTERS 16
 168
 169 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 170 #define REGISTER_UNIFORMS 24
 171
 172 #define REGISTER_UNUSED 24
 173 #define REGISTER_CONSTANT 26
 174 #define REGISTER_LDST_BASE 26
 175 #define REGISTER_TEXTURE_BASE 28
 176 #define REGISTER_SELECT 31
 177
 178 /* SSA helper aliases to mimic the registers. */
 179
 180 #define SSA_UNUSED ~0
 181 #define SSA_FIXED_SHIFT 24
 182 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
 183 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
 184 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 185
 186 /* Swizzle support */
 187
 188 #define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
 189 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 190 #define COMPONENT_X 0x0
 191 #define COMPONENT_Y 0x1
 192 #define COMPONENT_Z 0x2
 193 #define COMPONENT_W 0x3
 194
 195 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
 196 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
 197 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
 198 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
 199 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
 200 #define SWIZZLE_XYZZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_Z)
 201 #define SWIZZLE_XXXY SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_Y)
 202 #define SWIZZLE_ZZZW SWIZZLE(COMPONENT_Z, COMPONENT_Z, COMPONENT_Z, COMPONENT_W)
 203 #define SWIZZLE_ZWWW SWIZZLE(COMPONENT_Z, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 204 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
 205
 206 static inline unsigned
 207 swizzle_of(unsigned comp)
 208 {
 209         switch (comp) {
 210         case 1:
 211                 return SWIZZLE_XXXX;
 212         case 2:
 213                 return SWIZZLE_XYXX;
 214         case 3:
 215                 return SWIZZLE_XYZX;
 216         case 4:
 217                 return SWIZZLE_XYZW;
 218         default:
 219                 unreachable("Invalid component count");
 220         }
 221 }
 222
 223 static inline unsigned
 224 mask_of(unsigned nr_comp)
 225 {
 226         return (1 << nr_comp) - 1;
 227 }
 228
 229
 230 /* See ISA notes */
 231
 232 #define LDST_NOP (3)
 233
 234 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 235  * implemented on some subset of these units (or occassionally all of them).
 236  * This table encodes a bit mask of valid units for each opcode, so the
 237  * scheduler can figure where to plonk the instruction. */
 238
 239 /* Shorthands for each unit */
 240 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 241 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 242 #define UNIT_VADD ALU_ENAB_VEC_ADD
 243 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 244 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 245
 246 /* Shorthands for usual combinations of units */
 247
 248 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 249 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 250 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 251 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 252 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 253 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 254 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 255
 256 struct mir_op_props {
 257         const char *name;
 258         unsigned props;
 259 };
 260
 261 /* This file is common, so don't define the tables themselves. #include
 262  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 263
 264 /* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
 265  * which is used for 32-bit vector units */
 266
 267 static inline unsigned
 268 expand_writemask_32(unsigned mask)
 269 {
 270         unsigned o = 0;
 271
 272         for (int i = 0; i < 4; ++i)
 273                 if (mask & (1 << i))
 274                         o |= (3 << (2 * i));
 275
 276         return o;
 277 }
 278
 279 /* Coerce structs to integer */
 280
 281 static inline unsigned
 282 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 283 {
 284         unsigned u;
 285         memcpy(&u, &src, sizeof(src));
 286         return u;
 287 }
 288
 289 static inline midgard_vector_alu_src
 290 vector_alu_from_unsigned(unsigned u)
 291 {
 292         midgard_vector_alu_src s;
 293         memcpy(&s, &u, sizeof(s));
 294         return s;
 295 }
 296
 297 /* Composes two swizzles */
 298 static inline unsigned
 299 pan_compose_swizzle(unsigned left, unsigned right)
 300 {
 301         unsigned out = 0;
 302
 303         for (unsigned c = 0; c < 4; ++c) {
 304                 unsigned s = (left >> (2*c)) & 0x3;
 305                 unsigned q = (right >> (2*s)) & 0x3;
 306
 307                 out |= (q << (2*c));
 308         }
 309
 310         return out;
 311 }
 312
 313 /* Applies a swizzle to an ALU source */
 314
 315 static inline unsigned
 316 vector_alu_apply_swizzle(unsigned src, unsigned swizzle)
 317 {
 318         midgard_vector_alu_src s =
 319                 vector_alu_from_unsigned(src);
 320
 321         s.swizzle = pan_compose_swizzle(s.swizzle, swizzle);
 322
 323         return vector_alu_srco_unsigned(s);
 324 }
 325
 326 /* Checks for an xyzw.. swizzle, given a mask */
 327
 328 static inline bool
 329 mir_is_simple_swizzle(unsigned swizzle, unsigned mask)
 330 {
 331         for (unsigned i = 0; i < 16; ++i) {
 332                 if (!(mask & (1 << i))) continue;
 333
 334                 if (((swizzle >> (2 * i)) & 0x3) != i)
 335                         return false;
 336         }
 337
 338         return true;
 339 }
 340
 341 /* Packs a load/store argument */
 342
 343 static inline uint8_t
 344 midgard_ldst_reg(unsigned reg, unsigned component)
 345 {
 346         assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1));
 347
 348         midgard_ldst_register_select sel = {
 349                 .component = component,
 350                 .select = reg - 26
 351         };
 352
 353         uint8_t packed;
 354         memcpy(&packed, &sel, sizeof(packed));
 355
 356         return packed;
 357 }
 358
 359 /* Unpacks a load/store argument */
 360
 361 static inline midgard_ldst_register_select
 362 midgard_ldst_select(uint8_t u)
 363 {
 364         midgard_ldst_register_select sel;
 365         memcpy(&sel, &u, sizeof(u));
 366         return sel;
 367 }
 368
 369 static inline uint8_t
 370 midgard_ldst_pack(midgard_ldst_register_select sel)
 371 {
 372         uint8_t packed;
 373         memcpy(&packed, &sel, sizeof(packed));
 374         return packed;
 375 }
 376
 377 /* Gets a swizzle like yyyy and returns y */
 378
 379 static inline unsigned
 380 swizzle_to_component(unsigned swizzle)
 381 {
 382         unsigned c = swizzle & 3;
 383         assert(((swizzle >> 2) & 3) == c);
 384         assert(((swizzle >> 4) & 3) == c);
 385         assert(((swizzle >> 6) & 3) == c);
 386         return  c;
 387 }
 388
 389
 390 static inline unsigned
 391 component_to_swizzle(unsigned c)
 392 {
 393         return SWIZZLE(c, c, c, c);
 394 }
 395
 396 #endif