src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <stdio.h>
  27 #include <string.h>
  28
  29 #define OP_IS_LOAD_VARY_F(op) (\
  30                 op == midgard_op_ld_vary_16 || \
  31                 op == midgard_op_ld_vary_32 \
  32         )
  33
  34 #define OP_IS_PROJECTION(op) ( \
  35                 op == midgard_op_ldst_perspective_division_z || \
  36                 op == midgard_op_ldst_perspective_division_w \
  37         )
  38
  39 #define OP_IS_VEC4_ONLY(op) ( \
  40                 OP_IS_PROJECTION(op) || \
  41                 op == midgard_op_ld_cubemap_coords \
  42         )
  43
  44 #define OP_IS_MOVE(op) ( \
  45                 op == midgard_alu_op_fmov || \
  46                 op == midgard_alu_op_imov \
  47         )
  48
  49 #define OP_IS_UBO_READ(op) ( \
  50                 op == midgard_op_ld_ubo_char  || \
  51                 op == midgard_op_ld_ubo_char2  || \
  52                 op == midgard_op_ld_ubo_char4  || \
  53                 op == midgard_op_ld_ubo_short4  || \
  54                 op == midgard_op_ld_ubo_int4 \
  55         )
  56
  57 #define OP_IS_CSEL_V(op) ( \
  58                 op == midgard_alu_op_icsel_v || \
  59                 op == midgard_alu_op_fcsel_v \
  60         )
  61
  62 #define OP_IS_CSEL(op) ( \
  63                 OP_IS_CSEL_V(op) || \
  64                 op == midgard_alu_op_icsel || \
  65                 op == midgard_alu_op_fcsel \
  66         )
  67
  68 #define OP_IS_DERIVATIVE(op) ( \
  69                 op == TEXTURE_OP_DFDX || \
  70                 op == TEXTURE_OP_DFDY \
  71         )
  72
  73 #define OP_IS_UNSIGNED_CMP(op) ( \
  74                 op == midgard_alu_op_ult || \
  75                 op == midgard_alu_op_ule \
  76         )
  77
  78 #define OP_IS_INTEGER_CMP(op) ( \
  79                 op == midgard_alu_op_ieq || \
  80                 op == midgard_alu_op_ine || \
  81                 op == midgard_alu_op_ilt || \
  82                 op == midgard_alu_op_ile || \
  83                 OP_IS_UNSIGNED_CMP(op) \
  84         )
  85
  86 /* ALU control words are single bit fields with a lot of space */
  87
  88 #define ALU_ENAB_VEC_MUL  (1 << 17)
  89 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  90 #define ALU_ENAB_VEC_ADD  (1 << 21)
  91 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  92 #define ALU_ENAB_VEC_LUT  (1 << 25)
  93 #define ALU_ENAB_BR_COMPACT (1 << 26)
  94 #define ALU_ENAB_BRANCH   (1 << 27)
  95
  96 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  97
  98 /* Denotes an opcode that takes a vector input with a fixed-number of
  99  * channels, but outputs to only a single output channel, like dot products.
 100  * For these, to determine the effective mask, this quirk can be set. We have
 101  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
 102  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
 103  * make sense (since then why are we quirked?), so that corresponds to "no
 104  * count set" */
 105
 106 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
 107 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
 108
 109 /* For instructions that take a single argument, normally the first argument
 110  * slot is used for the argument and the second slot is a dummy #0 constant.
 111  * However, there are exceptions: instructions like fmov store their argument
 112  * in the _second_ slot and store a dummy r24 in the first slot, designated by
 113  * QUIRK_FLIPPED_R24 */
 114
 115 #define QUIRK_FLIPPED_R24 (1 << 2)
 116
 117 /* Is the op commutative? */
 118 #define OP_COMMUTES (1 << 3)
 119
 120 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 121 #define OP_TYPE_CONVERT (1 << 4)
 122
 123 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 124  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 125
 126 #define UNIT_MUL 0
 127 #define UNIT_ADD 1
 128 #define UNIT_LUT 2
 129
 130 /* 4-bit type tags */
 131
 132 #define TAG_TEXTURE_4_VTX 0x2
 133 #define TAG_TEXTURE_4 0x3
 134 #define TAG_LOAD_STORE_4 0x5
 135 #define TAG_ALU_4 0x8
 136 #define TAG_ALU_8 0x9
 137 #define TAG_ALU_12 0xA
 138 #define TAG_ALU_16 0xB
 139
 140 #define IS_ALU(tag) (tag >= TAG_ALU_4)
 141
 142 /* Special register aliases */
 143
 144 #define MAX_WORK_REGISTERS 16
 145
 146 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 147 #define REGISTER_UNIFORMS 24
 148
 149 #define REGISTER_UNUSED 24
 150 #define REGISTER_CONSTANT 26
 151 #define REGISTER_LDST_BASE 26
 152 #define REGISTER_TEXTURE_BASE 28
 153 #define REGISTER_SELECT 31
 154
 155 /* SSA helper aliases to mimic the registers. */
 156
 157 #define SSA_FIXED_SHIFT 24
 158 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
 159 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
 160 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 161
 162 #define COMPONENT_X 0x0
 163 #define COMPONENT_Y 0x1
 164 #define COMPONENT_Z 0x2
 165 #define COMPONENT_W 0x3
 166
 167 #define SWIZZLE_IDENTITY { \
 168         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 169         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 170         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 171         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } \
 172 }
 173
 174 #define SWIZZLE_IDENTITY_4 { \
 175         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 176         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 177         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 178         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 179 }
 180
 181 static inline unsigned
 182 mask_of(unsigned nr_comp)
 183 {
 184         return (1 << nr_comp) - 1;
 185 }
 186
 187 /* See ISA notes */
 188
 189 #define LDST_NOP (3)
 190
 191 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 192  * implemented on some subset of these units (or occassionally all of them).
 193  * This table encodes a bit mask of valid units for each opcode, so the
 194  * scheduler can figure where to plonk the instruction. */
 195
 196 /* Shorthands for each unit */
 197 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 198 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 199 #define UNIT_VADD ALU_ENAB_VEC_ADD
 200 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 201 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 202
 203 /* Shorthands for usual combinations of units */
 204
 205 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 206 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 207 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 208 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 209 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 210 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 211 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 212
 213 struct mir_op_props {
 214         const char *name;
 215         unsigned props;
 216 };
 217
 218 /* For load/store */
 219
 220 struct mir_ldst_op_props {
 221         const char *name;
 222         unsigned props;
 223 };
 224
 225 /* Lower 2-bits are a midgard_reg_mode */
 226 #define GET_LDST_SIZE(c) (c & 3)
 227
 228 /* Store (so the primary register is a source, not a destination */
 229 #define LDST_STORE (1 << 2)
 230
 231 /* Mask has special meaning and should not be manipulated directly */
 232 #define LDST_SPECIAL_MASK (1 << 3)
 233
 234 /* Non-store operation has side effects and should not be eliminated even if
 235  * its mask is 0 */
 236 #define LDST_SIDE_FX (1 << 4)
 237
 238 /* This file is common, so don't define the tables themselves. #include
 239  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 240
 241 /* Duplicate bits to convert a per-component to duplicated 8-bit format,
 242  * which is used for vector units */
 243
 244 static inline unsigned
 245 expand_writemask(unsigned mask, unsigned channels)
 246 {
 247         unsigned o = 0;
 248         unsigned factor = 8 / channels;
 249         unsigned expanded = (1 << factor) - 1;
 250
 251         for (unsigned i = 0; i < channels; ++i)
 252                 if (mask & (1 << i))
 253                         o |= (expanded << (factor * i));
 254
 255         return o;
 256 }
 257
 258 /* Tansform an expanded writemask (duplicated 8-bit format) into its condensed
 259  * form (one bit per component) */
 260
 261 static inline unsigned
 262 condense_writemask(unsigned expanded_mask,
 263                    unsigned bits_per_component)
 264 {
 265         if (bits_per_component == 8)
 266                 unreachable("XXX TODO: sort out how 8-bit constant encoding works");
 267
 268         unsigned slots_per_component = bits_per_component / 16;
 269         unsigned max_comp = (16 * 8) / bits_per_component;
 270         unsigned condensed_mask = 0;
 271
 272         for (unsigned i = 0; i < max_comp; i++) {
 273                 if (expanded_mask & (1 << (i * slots_per_component)))
 274                         condensed_mask |= (1 << i);
 275         }
 276
 277         return condensed_mask;
 278 }
 279
 280 /* Coerce structs to integer */
 281
 282 static inline unsigned
 283 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 284 {
 285         unsigned u;
 286         memcpy(&u, &src, sizeof(src));
 287         return u;
 288 }
 289
 290 static inline midgard_vector_alu_src
 291 vector_alu_from_unsigned(unsigned u)
 292 {
 293         midgard_vector_alu_src s;
 294         memcpy(&s, &u, sizeof(s));
 295         return s;
 296 }
 297
 298 static inline void
 299 mir_compose_swizzle(unsigned *left, unsigned *right, unsigned *final_out)
 300 {
 301         unsigned out[16];
 302
 303         for (unsigned c = 0; c < 16; ++c)
 304                 out[c] = right[left[c]];
 305
 306         memcpy(final_out, out, sizeof(out));
 307 }
 308
 309 /* Checks for an xyzw.. swizzle, given a mask */
 310
 311 static inline bool
 312 mir_is_simple_swizzle(unsigned *swizzle, unsigned mask)
 313 {
 314         for (unsigned i = 0; i < 16; ++i) {
 315                 if (!(mask & (1 << i))) continue;
 316
 317                 if (swizzle[i] != i)
 318                         return false;
 319         }
 320
 321         return true;
 322 }
 323
 324 /* Packs a load/store argument */
 325
 326 static inline uint8_t
 327 midgard_ldst_reg(unsigned reg, unsigned component)
 328 {
 329         assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1));
 330
 331         midgard_ldst_register_select sel = {
 332                 .component = component,
 333                 .select = reg - 26
 334         };
 335
 336         uint8_t packed;
 337         memcpy(&packed, &sel, sizeof(packed));
 338
 339         return packed;
 340 }
 341
 342 static inline bool
 343 midgard_is_branch_unit(unsigned unit)
 344 {
 345         return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
 346 }
 347
 348 void
 349 mir_print_constant_component(FILE *fp, const midgard_constants *consts,
 350                              unsigned c, midgard_reg_mode reg_mode, bool half,
 351                              unsigned mod, midgard_alu_op op);
 352
 353 #endif