2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
81 block
->successors
[block
->nr_successors
++] = successor
;
82 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
85 /* Helpers to generate midgard_instruction's using macro magic, since every
86 * driver seems to do it that way */
88 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
90 #define M_LOAD_STORE(name, rname, uname) \
91 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
92 midgard_instruction i = { \
93 .type = TAG_LOAD_STORE_4, \
101 .op = midgard_op_##name, \
102 .swizzle = SWIZZLE_XYZW, \
110 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
111 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
113 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
114 * the corresponding Midgard source */
116 static midgard_vector_alu_src
117 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
118 bool half
, bool sext
)
120 if (!src
) return blank_alu_src
;
122 /* Figure out how many components there are so we can adjust the
123 * swizzle. Specifically we want to broadcast the last channel so
124 * things like ball2/3 work
127 if (broadcast_count
) {
128 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
130 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
131 src
->swizzle
[c
] = last_component
;
135 midgard_vector_alu_src alu_src
= {
139 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
143 alu_src
.mod
= midgard_int_normal
;
145 /* Sign/zero-extend if needed */
149 midgard_int_sign_extend
150 : midgard_int_zero_extend
;
153 /* These should have been lowered away */
154 assert(!(src
->abs
|| src
->negate
));
156 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
162 /* load/store instructions have both 32-bit and 16-bit variants, depending on
163 * whether we are using vectors composed of highp or mediump. At the moment, we
164 * don't support half-floats -- this requires changes in other parts of the
165 * compiler -- therefore the 16-bit versions are commented out. */
167 //M_LOAD(ld_attr_16);
169 //M_LOAD(ld_vary_16);
171 //M_LOAD(ld_uniform_16);
172 M_LOAD(ld_uniform_32
);
173 M_LOAD(ld_color_buffer_8
);
174 //M_STORE(st_vary_16);
176 M_LOAD(st_cubemap_coords
);
178 static midgard_instruction
179 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
181 midgard_branch_cond branch
= {
189 memcpy(&compact
, &branch
, sizeof(branch
));
191 midgard_instruction ins
= {
193 .unit
= ALU_ENAB_BR_COMPACT
,
194 .prepacked_branch
= true,
195 .compact_branch
= true,
196 .br_compact
= compact
199 if (op
== midgard_jmp_writeout_op_writeout
)
205 static midgard_instruction
206 v_branch(bool conditional
, bool invert
)
208 midgard_instruction ins
= {
210 .unit
= ALU_ENAB_BRANCH
,
211 .compact_branch
= true,
213 .conditional
= conditional
,
214 .invert_conditional
= invert
221 static midgard_branch_extended
222 midgard_create_branch_extended( midgard_condition cond
,
223 midgard_jmp_writeout_op op
,
225 signed quadword_offset
)
227 /* The condition code is actually a LUT describing a function to
228 * combine multiple condition codes. However, we only support a single
229 * condition code at the moment, so we just duplicate over a bunch of
232 uint16_t duplicated_cond
=
242 midgard_branch_extended branch
= {
244 .dest_tag
= dest_tag
,
245 .offset
= quadword_offset
,
246 .cond
= duplicated_cond
253 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
255 ins
->has_constants
= true;
256 memcpy(&ins
->constants
, constants
, 16);
260 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
262 return glsl_count_attribute_slots(type
, false);
265 /* Lower fdot2 to a vector multiplication followed by channel addition */
267 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
269 if (alu
->op
!= nir_op_fdot2
)
272 b
->cursor
= nir_before_instr(&alu
->instr
);
274 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
275 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
277 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
279 nir_ssa_def
*sum
= nir_fadd(b
,
280 nir_channel(b
, product
, 0),
281 nir_channel(b
, product
, 1));
283 /* Replace the fdot2 with this sum */
284 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
288 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
290 switch (instr
->intrinsic
) {
291 case nir_intrinsic_load_viewport_scale
:
292 return PAN_SYSVAL_VIEWPORT_SCALE
;
293 case nir_intrinsic_load_viewport_offset
:
294 return PAN_SYSVAL_VIEWPORT_OFFSET
;
300 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
303 nir_intrinsic_instr
*intr
;
304 nir_dest
*dst
= NULL
;
308 switch (instr
->type
) {
309 case nir_instr_type_intrinsic
:
310 intr
= nir_instr_as_intrinsic(instr
);
311 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
314 case nir_instr_type_tex
:
315 tex
= nir_instr_as_tex(instr
);
316 if (tex
->op
!= nir_texop_txs
)
319 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
320 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
321 nir_tex_instr_dest_size(tex
) -
322 (tex
->is_array
? 1 : 0),
331 *dest
= nir_dest_index(ctx
, dst
);
337 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
341 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
345 /* We have a sysval load; check if it's already been assigned */
347 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
350 /* It hasn't -- so assign it now! */
352 unsigned id
= ctx
->sysval_count
++;
353 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
354 ctx
->sysvals
[id
] = sysval
;
358 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
360 ctx
->sysval_count
= 0;
362 nir_foreach_function(function
, shader
) {
363 if (!function
->impl
) continue;
365 nir_foreach_block(block
, function
->impl
) {
366 nir_foreach_instr_safe(instr
, block
) {
367 midgard_nir_assign_sysval_body(ctx
, instr
);
374 midgard_nir_lower_fdot2(nir_shader
*shader
)
376 bool progress
= false;
378 nir_foreach_function(function
, shader
) {
379 if (!function
->impl
) continue;
382 nir_builder
*b
= &_b
;
383 nir_builder_init(b
, function
->impl
);
385 nir_foreach_block(block
, function
->impl
) {
386 nir_foreach_instr_safe(instr
, block
) {
387 if (instr
->type
!= nir_instr_type_alu
) continue;
389 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
390 midgard_nir_lower_fdot2_body(b
, alu
);
396 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
403 /* Flushes undefined values to zero */
406 optimise_nir(nir_shader
*nir
)
409 unsigned lower_flrp
=
410 (nir
->options
->lower_flrp16
? 16 : 0) |
411 (nir
->options
->lower_flrp32
? 32 : 0) |
412 (nir
->options
->lower_flrp64
? 64 : 0);
414 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
415 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
416 NIR_PASS(progress
, nir
, nir_lower_idiv
);
418 nir_lower_tex_options lower_tex_1st_pass_options
= {
423 nir_lower_tex_options lower_tex_2nd_pass_options
= {
424 .lower_txs_lod
= true,
427 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
428 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
433 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
434 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
436 NIR_PASS(progress
, nir
, nir_copy_prop
);
437 NIR_PASS(progress
, nir
, nir_opt_dce
);
438 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
439 NIR_PASS(progress
, nir
, nir_opt_cse
);
440 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
441 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
442 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
444 if (lower_flrp
!= 0) {
445 bool lower_flrp_progress
= false;
446 NIR_PASS(lower_flrp_progress
,
450 false /* always_precise */,
451 nir
->options
->lower_ffma
);
452 if (lower_flrp_progress
) {
453 NIR_PASS(progress
, nir
,
454 nir_opt_constant_folding
);
458 /* Nothing should rematerialize any flrps, so we only
459 * need to do this lowering once.
464 NIR_PASS(progress
, nir
, nir_opt_undef
);
465 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
467 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
470 nir_var_function_temp
);
472 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
475 /* Must be run at the end to prevent creation of fsin/fcos ops */
476 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
481 NIR_PASS(progress
, nir
, nir_opt_dce
);
482 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
483 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
484 NIR_PASS(progress
, nir
, nir_copy_prop
);
487 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
489 /* We implement booleans as 32-bit 0/~0 */
490 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
492 /* Now that booleans are lowered, we can run out late opts */
493 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
495 /* Lower mods for float ops only. Integer ops don't support modifiers
496 * (saturate doesn't make sense on integers, neg/abs require dedicated
499 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
500 NIR_PASS(progress
, nir
, nir_copy_prop
);
501 NIR_PASS(progress
, nir
, nir_opt_dce
);
503 /* Take us out of SSA */
504 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
505 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
507 /* We are a vector architecture; write combine where possible */
508 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
509 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
511 NIR_PASS(progress
, nir
, nir_opt_dce
);
514 /* Do not actually emit a load; instead, cache the constant for inlining */
517 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
519 nir_ssa_def def
= instr
->def
;
521 float *v
= rzalloc_array(NULL
, float, 4);
522 nir_const_load_to_arr(v
, instr
, f32
);
524 /* Shifted for SSA, +1 for off-by-one */
525 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
528 /* Normally constants are embedded implicitly, but for I/O and such we have to
529 * explicitly emit a move with the constant source */
532 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
534 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
536 if (constant_value
) {
537 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
538 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
539 emit_mir_instruction(ctx
, ins
);
544 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
546 unsigned comp
= src
->swizzle
[0];
548 for (unsigned c
= 1; c
< nr_components
; ++c
) {
549 if (src
->swizzle
[c
] != comp
)
556 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
557 * output of a conditional test) into that register */
560 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
562 int condition
= nir_src_index(ctx
, src
);
564 /* Source to swizzle the desired component into w */
566 const midgard_vector_alu_src alu_src
= {
567 .swizzle
= SWIZZLE(component
, component
, component
, component
),
570 /* There is no boolean move instruction. Instead, we simulate a move by
571 * ANDing the condition with itself to get it into r31.w */
573 midgard_instruction ins
= {
576 /* We need to set the conditional as close as possible */
577 .precede_break
= true,
578 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
579 .mask
= 1 << COMPONENT_W
,
584 .dest
= SSA_FIXED_REGISTER(31),
588 .op
= midgard_alu_op_iand
,
589 .outmod
= midgard_outmod_int_wrap
,
590 .reg_mode
= midgard_reg_mode_32
,
591 .dest_override
= midgard_dest_override_none
,
592 .src1
= vector_alu_srco_unsigned(alu_src
),
593 .src2
= vector_alu_srco_unsigned(alu_src
)
597 emit_mir_instruction(ctx
, ins
);
600 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
604 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
606 int condition
= nir_src_index(ctx
, &src
->src
);
608 /* Source to swizzle the desired component into w */
610 const midgard_vector_alu_src alu_src
= {
611 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
614 /* There is no boolean move instruction. Instead, we simulate a move by
615 * ANDing the condition with itself to get it into r31.w */
617 midgard_instruction ins
= {
619 .precede_break
= true,
620 .mask
= mask_of(nr_comp
),
624 .dest
= SSA_FIXED_REGISTER(31),
627 .op
= midgard_alu_op_iand
,
628 .outmod
= midgard_outmod_int_wrap
,
629 .reg_mode
= midgard_reg_mode_32
,
630 .dest_override
= midgard_dest_override_none
,
631 .src1
= vector_alu_srco_unsigned(alu_src
),
632 .src2
= vector_alu_srco_unsigned(alu_src
)
636 emit_mir_instruction(ctx
, ins
);
641 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
642 * pinning to eliminate this move in all known cases */
645 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
647 int offset
= nir_src_index(ctx
, src
);
649 midgard_instruction ins
= {
651 .mask
= 1 << COMPONENT_W
,
653 .src0
= SSA_UNUSED_1
,
655 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
658 .op
= midgard_alu_op_imov
,
659 .outmod
= midgard_outmod_int_wrap
,
660 .reg_mode
= midgard_reg_mode_32
,
661 .dest_override
= midgard_dest_override_none
,
662 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
663 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
667 emit_mir_instruction(ctx
, ins
);
670 #define ALU_CASE(nir, _op) \
672 op = midgard_alu_op_##_op; \
673 assert(src_bitsize == dst_bitsize); \
676 #define ALU_CASE_BCAST(nir, _op, count) \
678 op = midgard_alu_op_##_op; \
679 broadcast_swizzle = count; \
680 assert(src_bitsize == dst_bitsize); \
683 nir_is_fzero_constant(nir_src src
)
685 if (!nir_src_is_const(src
))
688 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
689 if (nir_src_comp_as_float(src
, c
) != 0.0)
696 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
697 * special treatment override this anyway. */
699 static midgard_reg_mode
700 reg_mode_for_nir(nir_alu_instr
*instr
)
702 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
704 switch (src_bitsize
) {
706 return midgard_reg_mode_8
;
708 return midgard_reg_mode_16
;
710 return midgard_reg_mode_32
;
712 return midgard_reg_mode_64
;
714 unreachable("Invalid bit size");
719 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
721 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
722 * is handled elsewhere */
724 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
725 midgard_emit_derivatives(ctx
, instr
);
729 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
731 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
732 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
733 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
735 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
736 * supported. A few do not and are commented for now. Also, there are a
737 * number of NIR ops which Midgard does not support and need to be
738 * lowered, also TODO. This switch block emits the opcode and calling
739 * convention of the Midgard instruction; actual packing is done in
744 /* Number of components valid to check for the instruction (the rest
745 * will be forced to the last), or 0 to use as-is. Relevant as
746 * ball-type instructions have a channel count in NIR but are all vec4
749 unsigned broadcast_swizzle
= 0;
751 /* What register mode should we operate in? */
752 midgard_reg_mode reg_mode
=
753 reg_mode_for_nir(instr
);
755 /* Do we need a destination override? Used for inline
758 midgard_dest_override dest_override
=
759 midgard_dest_override_none
;
761 /* Should we use a smaller respective source and sign-extend? */
763 bool half_1
= false, sext_1
= false;
764 bool half_2
= false, sext_2
= false;
766 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
767 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
770 ALU_CASE(fadd
, fadd
);
771 ALU_CASE(fmul
, fmul
);
772 ALU_CASE(fmin
, fmin
);
773 ALU_CASE(fmax
, fmax
);
774 ALU_CASE(imin
, imin
);
775 ALU_CASE(imax
, imax
);
776 ALU_CASE(umin
, umin
);
777 ALU_CASE(umax
, umax
);
778 ALU_CASE(ffloor
, ffloor
);
779 ALU_CASE(fround_even
, froundeven
);
780 ALU_CASE(ftrunc
, ftrunc
);
781 ALU_CASE(fceil
, fceil
);
782 ALU_CASE(fdot3
, fdot3
);
783 ALU_CASE(fdot4
, fdot4
);
784 ALU_CASE(iadd
, iadd
);
785 ALU_CASE(isub
, isub
);
786 ALU_CASE(imul
, imul
);
788 /* Zero shoved as second-arg */
789 ALU_CASE(iabs
, iabsdiff
);
793 ALU_CASE(feq32
, feq
);
794 ALU_CASE(fne32
, fne
);
795 ALU_CASE(flt32
, flt
);
796 ALU_CASE(ieq32
, ieq
);
797 ALU_CASE(ine32
, ine
);
798 ALU_CASE(ilt32
, ilt
);
799 ALU_CASE(ult32
, ult
);
801 /* We don't have a native b2f32 instruction. Instead, like many
802 * GPUs, we exploit booleans as 0/~0 for false/true, and
803 * correspondingly AND
804 * by 1.0 to do the type conversion. For the moment, prime us
807 * iand [whatever], #0
809 * At the end of emit_alu (as MIR), we'll fix-up the constant
812 ALU_CASE(b2f32
, iand
);
813 ALU_CASE(b2i32
, iand
);
815 /* Likewise, we don't have a dedicated f2b32 instruction, but
816 * we can do a "not equal to 0.0" test. */
818 ALU_CASE(f2b32
, fne
);
819 ALU_CASE(i2b32
, ine
);
821 ALU_CASE(frcp
, frcp
);
822 ALU_CASE(frsq
, frsqrt
);
823 ALU_CASE(fsqrt
, fsqrt
);
824 ALU_CASE(fexp2
, fexp2
);
825 ALU_CASE(flog2
, flog2
);
827 ALU_CASE(f2i32
, f2i_rtz
);
828 ALU_CASE(f2u32
, f2u_rtz
);
829 ALU_CASE(i2f32
, i2f_rtz
);
830 ALU_CASE(u2f32
, u2f_rtz
);
832 ALU_CASE(f2i16
, f2i_rtz
);
833 ALU_CASE(f2u16
, f2u_rtz
);
834 ALU_CASE(i2f16
, i2f_rtz
);
835 ALU_CASE(u2f16
, u2f_rtz
);
837 ALU_CASE(fsin
, fsin
);
838 ALU_CASE(fcos
, fcos
);
840 /* We'll set invert */
841 ALU_CASE(inot
, imov
);
842 ALU_CASE(iand
, iand
);
844 ALU_CASE(ixor
, ixor
);
845 ALU_CASE(ishl
, ishl
);
846 ALU_CASE(ishr
, iasr
);
847 ALU_CASE(ushr
, ilsr
);
849 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
850 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
851 ALU_CASE(b32all_fequal4
, fball_eq
);
853 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
854 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
855 ALU_CASE(b32any_fnequal4
, fbany_neq
);
857 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
858 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
859 ALU_CASE(b32all_iequal4
, iball_eq
);
861 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
862 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
863 ALU_CASE(b32any_inequal4
, ibany_neq
);
865 /* Source mods will be shoved in later */
866 ALU_CASE(fabs
, fmov
);
867 ALU_CASE(fneg
, fmov
);
868 ALU_CASE(fsat
, fmov
);
870 /* For size conversion, we use a move. Ideally though we would squash
871 * these ops together; maybe that has to happen after in NIR as part of
872 * propagation...? An earlier algebraic pass ensured we step down by
873 * only / exactly one size. If stepping down, we use a dest override to
874 * reduce the size; if stepping up, we use a larger-sized move with a
875 * half source and a sign/zero-extension modifier */
880 /* If we end up upscale, we'll need a sign-extend on the
881 * operand (the second argument) */
887 op
= midgard_alu_op_imov
;
889 if (dst_bitsize
== (src_bitsize
* 2)) {
893 /* Use a greater register mode */
895 } else if (src_bitsize
== (dst_bitsize
* 2)) {
896 /* Converting down */
897 dest_override
= midgard_dest_override_lower
;
904 assert(src_bitsize
== 32);
906 op
= midgard_alu_op_fmov
;
907 dest_override
= midgard_dest_override_lower
;
912 assert(src_bitsize
== 16);
914 op
= midgard_alu_op_fmov
;
921 /* For greater-or-equal, we lower to less-or-equal and flip the
929 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
930 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
931 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
932 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
935 /* Swap via temporary */
936 nir_alu_src temp
= instr
->src
[1];
937 instr
->src
[1] = instr
->src
[0];
938 instr
->src
[0] = temp
;
943 case nir_op_b32csel
: {
944 /* Midgard features both fcsel and icsel, depending on
945 * the type of the arguments/output. However, as long
946 * as we're careful we can _always_ use icsel and
947 * _never_ need fcsel, since the latter does additional
948 * floating-point-specific processing whereas the
949 * former just moves bits on the wire. It's not obvious
950 * why these are separate opcodes, save for the ability
951 * to do things like sat/pos/abs/neg for free */
953 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
954 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
956 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
959 /* Emit the condition into r31 */
962 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
964 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
966 /* The condition is the first argument; move the other
967 * arguments up one to be a binary instruction for
970 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
975 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
980 /* Midgard can perform certain modifiers on output of an ALU op */
983 if (midgard_is_integer_out_op(op
)) {
984 outmod
= midgard_outmod_int_wrap
;
986 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
987 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
990 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
992 if (instr
->op
== nir_op_fmax
) {
993 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
994 op
= midgard_alu_op_fmov
;
996 outmod
= midgard_outmod_pos
;
997 instr
->src
[0] = instr
->src
[1];
998 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
999 op
= midgard_alu_op_fmov
;
1001 outmod
= midgard_outmod_pos
;
1005 /* Fetch unit, quirks, etc information */
1006 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1007 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1009 /* src0 will always exist afaik, but src1 will not for 1-argument
1010 * instructions. The latter can only be fetched if the instruction
1011 * needs it, or else we may segfault. */
1013 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1014 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1016 /* Rather than use the instruction generation helpers, we do it
1017 * ourselves here to avoid the mess */
1019 midgard_instruction ins
= {
1022 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1023 .src1
= quirk_flipped_r24
? src0
: src1
,
1028 nir_alu_src
*nirmods
[2] = { NULL
};
1030 if (nr_inputs
== 2) {
1031 nirmods
[0] = &instr
->src
[0];
1032 nirmods
[1] = &instr
->src
[1];
1033 } else if (nr_inputs
== 1) {
1034 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1039 /* These were lowered to a move, so apply the corresponding mod */
1041 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1042 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1044 if (instr
->op
== nir_op_fneg
)
1045 s
->negate
= !s
->negate
;
1047 if (instr
->op
== nir_op_fabs
)
1051 bool is_int
= midgard_is_integer_op(op
);
1053 ins
.mask
= mask_of(nr_components
);
1055 midgard_vector_alu alu
= {
1057 .reg_mode
= reg_mode
,
1058 .dest_override
= dest_override
,
1061 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1062 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1065 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1068 ins
.mask
&= instr
->dest
.write_mask
;
1072 /* Late fixup for emulated instructions */
1074 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1075 /* Presently, our second argument is an inline #0 constant.
1076 * Switch over to an embedded 1.0 constant (that can't fit
1077 * inline, since we're 32-bit, not 16-bit like the inline
1080 ins
.ssa_args
.inline_constant
= false;
1081 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1082 ins
.has_constants
= true;
1084 if (instr
->op
== nir_op_b2f32
) {
1085 ins
.constants
[0] = 1.0f
;
1087 /* Type pun it into place */
1089 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1092 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1093 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1094 /* Lots of instructions need a 0 plonked in */
1095 ins
.ssa_args
.inline_constant
= false;
1096 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1097 ins
.has_constants
= true;
1098 ins
.constants
[0] = 0.0f
;
1099 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1100 } else if (instr
->op
== nir_op_inot
) {
1104 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1105 /* To avoid duplicating the lookup tables (probably), true LUT
1106 * instructions can only operate as if they were scalars. Lower
1107 * them here by changing the component. */
1109 uint8_t original_swizzle
[4];
1110 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1111 unsigned orig_mask
= ins
.mask
;
1113 for (int i
= 0; i
< nr_components
; ++i
) {
1114 /* Mask the associated component, dropping the
1115 * instruction if needed */
1118 ins
.mask
&= orig_mask
;
1123 for (int j
= 0; j
< 4; ++j
)
1124 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1126 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1127 emit_mir_instruction(ctx
, ins
);
1130 emit_mir_instruction(ctx
, ins
);
1136 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1137 * optimized) versions of UBO #0 */
1141 compiler_context
*ctx
,
1144 nir_src
*indirect_offset
,
1147 /* TODO: half-floats */
1149 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1151 /* TODO: Don't split */
1152 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1153 ins
.load_store
.address
= offset
>> 3;
1155 if (indirect_offset
) {
1156 emit_indirect_offset(ctx
, indirect_offset
);
1157 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1159 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1162 emit_mir_instruction(ctx
, ins
);
1167 compiler_context
*ctx
,
1168 unsigned dest
, unsigned offset
,
1169 unsigned nr_comp
, unsigned component
,
1170 nir_src
*indirect_offset
, nir_alu_type type
)
1172 /* XXX: Half-floats? */
1173 /* TODO: swizzle, mask */
1175 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1176 ins
.mask
= mask_of(nr_comp
);
1177 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1179 midgard_varying_parameter p
= {
1181 .interpolation
= midgard_interp_default
,
1182 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1186 memcpy(&u
, &p
, sizeof(p
));
1187 ins
.load_store
.varying_parameters
= u
;
1189 if (indirect_offset
) {
1190 /* We need to add in the dynamic index, moved to r27.w */
1191 emit_indirect_offset(ctx
, indirect_offset
);
1192 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1194 /* Just a direct load */
1195 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1198 /* Use the type appropriate load */
1202 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1205 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1207 case nir_type_float
:
1208 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1211 unreachable("Attempted to load unknown type");
1215 emit_mir_instruction(ctx
, ins
);
1219 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1223 /* Figure out which uniform this is */
1224 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1225 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1227 /* Sysvals are prefix uniforms */
1228 unsigned uniform
= ((uintptr_t) val
) - 1;
1230 /* Emit the read itself -- this is never indirect */
1231 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1235 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1237 unsigned offset
= 0, reg
;
1239 switch (instr
->intrinsic
) {
1240 case nir_intrinsic_discard_if
:
1241 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1245 case nir_intrinsic_discard
: {
1246 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1247 struct midgard_instruction discard
= v_branch(conditional
, false);
1248 discard
.branch
.target_type
= TARGET_DISCARD
;
1249 emit_mir_instruction(ctx
, discard
);
1253 case nir_intrinsic_load_uniform
:
1254 case nir_intrinsic_load_ubo
:
1255 case nir_intrinsic_load_input
: {
1256 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1257 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1259 /* Get the base type of the intrinsic */
1260 /* TODO: Infer type? Does it matter? */
1262 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1263 t
= nir_alu_type_get_base_type(t
);
1266 offset
= nir_intrinsic_base(instr
);
1269 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1271 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1273 bool direct
= nir_src_is_const(*src_offset
);
1276 offset
+= nir_src_as_uint(*src_offset
);
1278 /* We may need to apply a fractional offset */
1279 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1280 nir_intrinsic_component(instr
) : 0;
1281 reg
= nir_dest_index(ctx
, &instr
->dest
);
1283 if (is_uniform
&& !ctx
->is_blend
) {
1284 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1285 } else if (is_ubo
) {
1286 nir_src index
= instr
->src
[0];
1288 /* We don't yet support indirect UBOs. For indirect
1289 * block numbers (if that's possible), we don't know
1290 * enough about the hardware yet. For indirect sources,
1291 * we know what we need but we need to add some NIR
1292 * support for lowering correctly with respect to
1295 assert(nir_src_is_const(index
));
1296 assert(nir_src_is_const(*src_offset
));
1298 /* TODO: Alignment */
1299 assert((offset
& 0xF) == 0);
1301 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1302 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1303 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1304 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1305 } else if (ctx
->is_blend
) {
1306 /* For blend shaders, load the input color, which is
1307 * preloaded to r0 */
1309 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1310 emit_mir_instruction(ctx
, move
);
1311 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1312 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1313 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1314 ins
.mask
= mask_of(nr_comp
);
1316 /* Use the type appropriate load */
1320 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1323 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1325 case nir_type_float
:
1326 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1329 unreachable("Attempted to load unknown type");
1333 emit_mir_instruction(ctx
, ins
);
1335 DBG("Unknown load\n");
1342 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1344 case nir_intrinsic_load_raw_output_pan
:
1345 reg
= nir_dest_index(ctx
, &instr
->dest
);
1346 assert(ctx
->is_blend
);
1348 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1349 emit_mir_instruction(ctx
, ins
);
1352 case nir_intrinsic_load_blend_const_color_rgba
: {
1353 assert(ctx
->is_blend
);
1354 reg
= nir_dest_index(ctx
, &instr
->dest
);
1356 /* Blend constants are embedded directly in the shader and
1357 * patched in, so we use some magic routing */
1359 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1360 ins
.has_constants
= true;
1361 ins
.has_blend_constant
= true;
1362 emit_mir_instruction(ctx
, ins
);
1366 case nir_intrinsic_store_output
:
1367 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1369 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1371 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1373 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1374 /* gl_FragColor is not emitted with load/store
1375 * instructions. Instead, it gets plonked into
1376 * r0 at the end of the shader and we do the
1377 * framebuffer writeout dance. TODO: Defer
1380 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1381 emit_mir_instruction(ctx
, move
);
1383 /* Save the index we're writing to for later reference
1384 * in the epilogue */
1386 ctx
->fragment_output
= reg
;
1387 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1388 /* We should have been vectorized, though we don't
1389 * currently check that st_vary is emitted only once
1390 * per slot (this is relevant, since there's not a mask
1391 * parameter available on the store [set to 0 by the
1392 * blob]). We do respect the component by adjusting the
1393 * swizzle. If this is a constant source, we'll need to
1394 * emit that explicitly. */
1396 emit_explicit_constant(ctx
, reg
, reg
);
1398 unsigned component
= nir_intrinsic_component(instr
);
1400 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1401 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1402 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1403 emit_mir_instruction(ctx
, st
);
1405 DBG("Unknown store\n");
1411 /* Special case of store_output for lowered blend shaders */
1412 case nir_intrinsic_store_raw_output_pan
:
1413 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1414 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1416 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1417 emit_mir_instruction(ctx
, move
);
1418 ctx
->fragment_output
= reg
;
1422 case nir_intrinsic_load_alpha_ref_float
:
1423 assert(instr
->dest
.is_ssa
);
1425 float ref_value
= ctx
->alpha_ref
;
1427 /* See emit_load_const */
1428 float *v
= ralloc_array(NULL
, float, 4);
1429 memcpy(v
, &ref_value
, sizeof(float));
1430 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (instr
->dest
.ssa
.index
<< 1) + 1, v
);
1433 case nir_intrinsic_load_viewport_scale
:
1434 case nir_intrinsic_load_viewport_offset
:
1435 emit_sysval_read(ctx
, &instr
->instr
);
1439 printf ("Unhandled intrinsic\n");
1446 midgard_tex_format(enum glsl_sampler_dim dim
)
1449 case GLSL_SAMPLER_DIM_1D
:
1450 case GLSL_SAMPLER_DIM_BUF
:
1453 case GLSL_SAMPLER_DIM_2D
:
1454 case GLSL_SAMPLER_DIM_EXTERNAL
:
1457 case GLSL_SAMPLER_DIM_3D
:
1460 case GLSL_SAMPLER_DIM_CUBE
:
1461 return MALI_TEX_CUBE
;
1464 DBG("Unknown sampler dim type\n");
1470 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1474 pan_attach_constant_bias(
1475 compiler_context
*ctx
,
1477 midgard_texture_word
*word
)
1479 /* To attach as constant, it has to *be* constant */
1481 if (!nir_src_is_const(lod
))
1484 float f
= nir_src_as_float(lod
);
1486 /* Break into fixed-point */
1488 float lod_frac
= f
- lod_int
;
1490 /* Carry over negative fractions */
1491 if (lod_frac
< 0.0) {
1497 word
->bias
= float_to_ubyte(lod_frac
);
1498 word
->bias_int
= lod_int
;
1503 static enum mali_sampler_type
1504 midgard_sampler_type(nir_alu_type t
) {
1505 switch (nir_alu_type_get_base_type(t
))
1507 case nir_type_float
:
1508 return MALI_SAMPLER_FLOAT
;
1510 return MALI_SAMPLER_SIGNED
;
1512 return MALI_SAMPLER_UNSIGNED
;
1514 unreachable("Unknown sampler type");
1519 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1520 unsigned midgard_texop
)
1523 //assert (!instr->sampler);
1524 //assert (!instr->texture_array_size);
1526 int texture_index
= instr
->texture_index
;
1527 int sampler_index
= texture_index
;
1529 /* No helper to build texture words -- we do it all here */
1530 midgard_instruction ins
= {
1531 .type
= TAG_TEXTURE_4
,
1534 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1539 .op
= midgard_texop
,
1540 .format
= midgard_tex_format(instr
->sampler_dim
),
1541 .texture_handle
= texture_index
,
1542 .sampler_handle
= sampler_index
,
1543 .swizzle
= SWIZZLE_XYZW
,
1544 .in_reg_swizzle
= SWIZZLE_XYZW
,
1550 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1554 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1555 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1556 midgard_vector_alu_src alu_src
= blank_alu_src
;
1558 switch (instr
->src
[i
].src_type
) {
1559 case nir_tex_src_coord
: {
1560 emit_explicit_constant(ctx
, index
, index
);
1562 /* Texelfetch coordinates uses all four elements
1563 * (xyz/index) regardless of texture dimensionality,
1564 * which means it's necessary to zero the unused
1565 * components to keep everything happy */
1567 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1568 unsigned old_index
= index
;
1570 index
= make_compiler_temp(ctx
);
1572 /* mov index, old_index */
1573 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1575 emit_mir_instruction(ctx
, mov
);
1577 /* mov index.zw, #0 */
1578 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1579 blank_alu_src
, index
);
1580 mov
.has_constants
= true;
1581 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1582 emit_mir_instruction(ctx
, mov
);
1585 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1586 /* texelFetch is undefined on samplerCube */
1587 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1589 /* For cubemaps, we use a special ld/st op to
1590 * select the face and copy the xy into the
1591 * texture register */
1593 unsigned temp
= make_compiler_temp(ctx
);
1595 midgard_instruction st
= m_st_cubemap_coords(temp
, 0);
1596 st
.ssa_args
.src0
= index
;
1597 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1598 st
.mask
= 0x3; /* xy */
1599 st
.load_store
.swizzle
= alu_src
.swizzle
;
1600 emit_mir_instruction(ctx
, st
);
1602 ins
.ssa_args
.src0
= temp
;
1604 ins
.ssa_args
.src0
= index
;
1607 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1608 /* Array component in w but NIR wants it in z */
1609 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1615 case nir_tex_src_bias
:
1616 case nir_tex_src_lod
: {
1617 /* Try as a constant if we can */
1619 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1620 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1623 ins
.texture
.lod_register
= true;
1624 ins
.ssa_args
.src1
= index
;
1625 emit_explicit_constant(ctx
, index
, index
);
1631 unreachable("Unknown texture source type\n");
1635 emit_mir_instruction(ctx
, ins
);
1637 /* Used for .cont and .last hinting */
1638 ctx
->texture_op_count
++;
1642 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1644 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1645 * generic tex in some cases (which confuses the hardware) */
1647 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1649 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1650 instr
->op
= nir_texop_txl
;
1652 switch (instr
->op
) {
1655 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1658 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1661 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1664 emit_sysval_read(ctx
, &instr
->instr
);
1667 unreachable("Unhanlded texture op");
1672 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1674 switch (instr
->type
) {
1675 case nir_jump_break
: {
1676 /* Emit a branch out of the loop */
1677 struct midgard_instruction br
= v_branch(false, false);
1678 br
.branch
.target_type
= TARGET_BREAK
;
1679 br
.branch
.target_break
= ctx
->current_loop_depth
;
1680 emit_mir_instruction(ctx
, br
);
1685 DBG("Unknown jump type %d\n", instr
->type
);
1691 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1693 switch (instr
->type
) {
1694 case nir_instr_type_load_const
:
1695 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1698 case nir_instr_type_intrinsic
:
1699 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1702 case nir_instr_type_alu
:
1703 emit_alu(ctx
, nir_instr_as_alu(instr
));
1706 case nir_instr_type_tex
:
1707 emit_tex(ctx
, nir_instr_as_tex(instr
));
1710 case nir_instr_type_jump
:
1711 emit_jump(ctx
, nir_instr_as_jump(instr
));
1714 case nir_instr_type_ssa_undef
:
1719 DBG("Unhandled instruction type\n");
1725 /* ALU instructions can inline or embed constants, which decreases register
1726 * pressure and saves space. */
1728 #define CONDITIONAL_ATTACH(src) { \
1729 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1732 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1733 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1738 inline_alu_constants(compiler_context
*ctx
)
1740 mir_foreach_instr(ctx
, alu
) {
1741 /* Other instructions cannot inline constants */
1742 if (alu
->type
!= TAG_ALU_4
) continue;
1744 /* If there is already a constant here, we can do nothing */
1745 if (alu
->has_constants
) continue;
1747 /* It makes no sense to inline constants on a branch */
1748 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1750 CONDITIONAL_ATTACH(src0
);
1752 if (!alu
->has_constants
) {
1753 CONDITIONAL_ATTACH(src1
)
1754 } else if (!alu
->inline_constant
) {
1755 /* Corner case: _two_ vec4 constants, for instance with a
1756 * csel. For this case, we can only use a constant
1757 * register for one, we'll have to emit a move for the
1758 * other. Note, if both arguments are constants, then
1759 * necessarily neither argument depends on the value of
1760 * any particular register. As the destination register
1761 * will be wiped, that means we can spill the constant
1762 * to the destination register.
1765 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1766 unsigned scratch
= alu
->ssa_args
.dest
;
1769 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1770 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1772 /* Force a break XXX Defer r31 writes */
1773 ins
.unit
= UNIT_VLUT
;
1775 /* Set the source */
1776 alu
->ssa_args
.src1
= scratch
;
1778 /* Inject us -before- the last instruction which set r31 */
1779 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1785 /* Midgard supports two types of constants, embedded constants (128-bit) and
1786 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1787 * constants can be demoted to inline constants, for space savings and
1788 * sometimes a performance boost */
1791 embedded_to_inline_constant(compiler_context
*ctx
)
1793 mir_foreach_instr(ctx
, ins
) {
1794 if (!ins
->has_constants
) continue;
1796 if (ins
->ssa_args
.inline_constant
) continue;
1798 /* Blend constants must not be inlined by definition */
1799 if (ins
->has_blend_constant
) continue;
1801 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1802 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1803 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1805 if (!(is_16
|| is_32
))
1808 /* src1 cannot be an inline constant due to encoding
1809 * restrictions. So, if possible we try to flip the arguments
1812 int op
= ins
->alu
.op
;
1814 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1816 /* These ops require an operational change to flip
1817 * their arguments TODO */
1818 case midgard_alu_op_flt
:
1819 case midgard_alu_op_fle
:
1820 case midgard_alu_op_ilt
:
1821 case midgard_alu_op_ile
:
1822 case midgard_alu_op_fcsel
:
1823 case midgard_alu_op_icsel
:
1824 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1829 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1830 /* Flip the SSA numbers */
1831 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1832 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1834 /* And flip the modifiers */
1838 src_temp
= ins
->alu
.src2
;
1839 ins
->alu
.src2
= ins
->alu
.src1
;
1840 ins
->alu
.src1
= src_temp
;
1844 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1845 /* Extract the source information */
1847 midgard_vector_alu_src
*src
;
1848 int q
= ins
->alu
.src2
;
1849 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1852 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1853 int component
= src
->swizzle
& 3;
1855 /* Scale constant appropriately, if we can legally */
1856 uint16_t scaled_constant
= 0;
1858 if (midgard_is_integer_op(op
) || is_16
) {
1859 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1860 scaled_constant
= (uint16_t) iconstants
[component
];
1862 /* Constant overflow after resize */
1863 if (scaled_constant
!= iconstants
[component
])
1866 float original
= (float) ins
->constants
[component
];
1867 scaled_constant
= _mesa_float_to_half(original
);
1869 /* Check for loss of precision. If this is
1870 * mediump, we don't care, but for a highp
1871 * shader, we need to pay attention. NIR
1872 * doesn't yet tell us which mode we're in!
1873 * Practically this prevents most constants
1874 * from being inlined, sadly. */
1876 float fp32
= _mesa_half_to_float(scaled_constant
);
1878 if (fp32
!= original
)
1882 /* We don't know how to handle these with a constant */
1884 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
1885 DBG("Bailing inline constant...\n");
1889 /* Make sure that the constant is not itself a
1890 * vector by checking if all accessed values
1891 * (by the swizzle) are the same. */
1893 uint32_t *cons
= (uint32_t *) ins
->constants
;
1894 uint32_t value
= cons
[component
];
1896 bool is_vector
= false;
1897 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
1899 for (int c
= 1; c
< 4; ++c
) {
1900 /* We only care if this component is actually used */
1901 if (!(mask
& (1 << c
)))
1904 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1906 if (test
!= value
) {
1915 /* Get rid of the embedded constant */
1916 ins
->has_constants
= false;
1917 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1918 ins
->ssa_args
.inline_constant
= true;
1919 ins
->inline_constant
= scaled_constant
;
1924 /* Dead code elimination for branches at the end of a block - only one branch
1925 * per block is legal semantically */
1928 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1930 bool branched
= false;
1932 mir_foreach_instr_in_block_safe(block
, ins
) {
1933 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1935 /* We ignore prepacked branches since the fragment epilogue is
1936 * just generally special */
1937 if (ins
->prepacked_branch
) continue;
1939 /* Discards are similarly special and may not correspond to the
1942 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1945 /* We already branched, so this is dead */
1946 mir_remove_instruction(ins
);
1953 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1954 * the move can be propagated away entirely */
1957 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
1960 if (comp
== midgard_outmod_none
)
1963 if (*outmod
== midgard_outmod_none
) {
1968 /* TODO: Compose rules */
1973 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
1975 bool progress
= false;
1977 mir_foreach_instr_in_block_safe(block
, ins
) {
1978 if (ins
->type
!= TAG_ALU_4
) continue;
1979 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
1980 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
1982 /* TODO: Registers? */
1983 unsigned src
= ins
->ssa_args
.src1
;
1984 if (src
& IS_REG
) continue;
1985 assert(!mir_has_multiple_writes(ctx
, src
));
1987 /* There might be a source modifier, too */
1988 if (mir_nontrivial_source2_mod(ins
)) continue;
1990 /* Backpropagate the modifier */
1991 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1992 if (v
->type
!= TAG_ALU_4
) continue;
1993 if (v
->ssa_args
.dest
!= src
) continue;
1995 /* Can we even take a float outmod? */
1996 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
1998 midgard_outmod_float temp
= v
->alu
.outmod
;
1999 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2001 /* Throw in the towel.. */
2002 if (!progress
) break;
2004 /* Otherwise, transfer the modifier */
2005 v
->alu
.outmod
= temp
;
2006 ins
->alu
.outmod
= midgard_outmod_none
;
2016 emit_fragment_epilogue(compiler_context
*ctx
)
2018 emit_explicit_constant(ctx
, ctx
->fragment_output
, SSA_FIXED_REGISTER(0));
2020 /* Perform the actual fragment writeout. We have two writeout/branch
2021 * instructions, forming a loop until writeout is successful as per the
2022 * docs. TODO: gl_FragDepth */
2024 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2025 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2028 static midgard_block
*
2029 emit_block(compiler_context
*ctx
, nir_block
*block
)
2031 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2032 list_addtail(&this_block
->link
, &ctx
->blocks
);
2034 this_block
->is_scheduled
= false;
2037 ctx
->texture_index
[0] = -1;
2038 ctx
->texture_index
[1] = -1;
2040 /* Add us as a successor to the block we are following */
2041 if (ctx
->current_block
)
2042 midgard_block_add_successor(ctx
->current_block
, this_block
);
2044 /* Set up current block */
2045 list_inithead(&this_block
->instructions
);
2046 ctx
->current_block
= this_block
;
2048 nir_foreach_instr(instr
, block
) {
2049 emit_instr(ctx
, instr
);
2050 ++ctx
->instruction_count
;
2053 inline_alu_constants(ctx
);
2054 embedded_to_inline_constant(ctx
);
2056 /* Append fragment shader epilogue (value writeout) */
2057 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2058 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2059 emit_fragment_epilogue(ctx
);
2063 if (block
== nir_start_block(ctx
->func
->impl
))
2064 ctx
->initial_block
= this_block
;
2066 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2067 ctx
->final_block
= this_block
;
2069 /* Allow the next control flow to access us retroactively, for
2071 ctx
->current_block
= this_block
;
2073 /* Document the fallthrough chain */
2074 ctx
->previous_source_block
= this_block
;
2079 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2082 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2084 /* Conditional branches expect the condition in r31.w; emit a move for
2085 * that in the _previous_ block (which is the current block). */
2086 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2088 /* Speculatively emit the branch, but we can't fill it in until later */
2089 EMIT(branch
, true, true);
2090 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2092 /* Emit the two subblocks */
2093 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2095 /* Emit a jump from the end of the then block to the end of the else */
2096 EMIT(branch
, false, false);
2097 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2099 /* Emit second block, and check if it's empty */
2101 int else_idx
= ctx
->block_count
;
2102 int count_in
= ctx
->instruction_count
;
2103 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2104 int after_else_idx
= ctx
->block_count
;
2106 /* Now that we have the subblocks emitted, fix up the branches */
2111 if (ctx
->instruction_count
== count_in
) {
2112 /* The else block is empty, so don't emit an exit jump */
2113 mir_remove_instruction(then_exit
);
2114 then_branch
->branch
.target_block
= after_else_idx
;
2116 then_branch
->branch
.target_block
= else_idx
;
2117 then_exit
->branch
.target_block
= after_else_idx
;
2122 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2124 /* Remember where we are */
2125 midgard_block
*start_block
= ctx
->current_block
;
2127 /* Allocate a loop number, growing the current inner loop depth */
2128 int loop_idx
= ++ctx
->current_loop_depth
;
2130 /* Get index from before the body so we can loop back later */
2131 int start_idx
= ctx
->block_count
;
2133 /* Emit the body itself */
2134 emit_cf_list(ctx
, &nloop
->body
);
2136 /* Branch back to loop back */
2137 struct midgard_instruction br_back
= v_branch(false, false);
2138 br_back
.branch
.target_block
= start_idx
;
2139 emit_mir_instruction(ctx
, br_back
);
2141 /* Mark down that branch in the graph. Note that we're really branching
2142 * to the block *after* we started in. TODO: Why doesn't the branch
2143 * itself have an off-by-one then...? */
2144 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2146 /* Find the index of the block about to follow us (note: we don't add
2147 * one; blocks are 0-indexed so we get a fencepost problem) */
2148 int break_block_idx
= ctx
->block_count
;
2150 /* Fix up the break statements we emitted to point to the right place,
2151 * now that we can allocate a block number for them */
2153 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2154 mir_foreach_instr_in_block(block
, ins
) {
2155 if (ins
->type
!= TAG_ALU_4
) continue;
2156 if (!ins
->compact_branch
) continue;
2157 if (ins
->prepacked_branch
) continue;
2159 /* We found a branch -- check the type to see if we need to do anything */
2160 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2162 /* It's a break! Check if it's our break */
2163 if (ins
->branch
.target_break
!= loop_idx
) continue;
2165 /* Okay, cool, we're breaking out of this loop.
2166 * Rewrite from a break to a goto */
2168 ins
->branch
.target_type
= TARGET_GOTO
;
2169 ins
->branch
.target_block
= break_block_idx
;
2173 /* Now that we've finished emitting the loop, free up the depth again
2174 * so we play nice with recursion amid nested loops */
2175 --ctx
->current_loop_depth
;
2177 /* Dump loop stats */
2181 static midgard_block
*
2182 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2184 midgard_block
*start_block
= NULL
;
2186 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2187 switch (node
->type
) {
2188 case nir_cf_node_block
: {
2189 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2192 start_block
= block
;
2197 case nir_cf_node_if
:
2198 emit_if(ctx
, nir_cf_node_as_if(node
));
2201 case nir_cf_node_loop
:
2202 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2205 case nir_cf_node_function
:
2214 /* Due to lookahead, we need to report the first tag executed in the command
2215 * stream and in branch targets. An initial block might be empty, so iterate
2216 * until we find one that 'works' */
2219 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2221 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2223 unsigned first_tag
= 0;
2226 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2228 if (initial_bundle
) {
2229 first_tag
= initial_bundle
->tag
;
2233 /* Initial block is empty, try the next block */
2234 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2235 } while(initial_block
!= NULL
);
2242 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2244 struct util_dynarray
*compiled
= &program
->compiled
;
2246 midgard_debug
= debug_get_option_midgard_debug();
2248 compiler_context ictx
= {
2251 .stage
= nir
->info
.stage
,
2254 .is_blend
= is_blend
,
2255 .blend_constant_offset
= 0,
2257 .alpha_ref
= program
->alpha_ref
2260 compiler_context
*ctx
= &ictx
;
2262 /* Start off with a safe cutoff, allowing usage of all 16 work
2263 * registers. Later, we'll promote uniform reads to uniform registers
2264 * if we determine it is beneficial to do so */
2265 ctx
->uniform_cutoff
= 8;
2267 /* Initialize at a global (not block) level hash tables */
2269 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2270 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2271 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2273 /* Record the varying mapping for the command stream's bookkeeping */
2275 struct exec_list
*varyings
=
2276 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2278 unsigned max_varying
= 0;
2279 nir_foreach_variable(var
, varyings
) {
2280 unsigned loc
= var
->data
.driver_location
;
2281 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2283 for (int c
= 0; c
< sz
; ++c
) {
2284 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2285 max_varying
= MAX2(max_varying
, loc
+ c
);
2289 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2290 * (so we don't accidentally duplicate the epilogue since mesa/st has
2291 * messed with our I/O quite a bit already) */
2293 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2295 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2296 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2297 NIR_PASS_V(nir
, nir_clamp_psiz
, 1.0, 1024.0);
2300 NIR_PASS_V(nir
, nir_lower_var_copies
);
2301 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2302 NIR_PASS_V(nir
, nir_split_var_copies
);
2303 NIR_PASS_V(nir
, nir_lower_var_copies
);
2304 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2305 NIR_PASS_V(nir
, nir_lower_var_copies
);
2306 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2308 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2310 /* Optimisation passes */
2314 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2315 nir_print_shader(nir
, stdout
);
2318 /* Assign sysvals and counts, now that we're sure
2319 * (post-optimisation) */
2321 midgard_nir_assign_sysvals(ctx
, nir
);
2323 program
->uniform_count
= nir
->num_uniforms
;
2324 program
->sysval_count
= ctx
->sysval_count
;
2325 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2327 nir_foreach_function(func
, nir
) {
2331 list_inithead(&ctx
->blocks
);
2332 ctx
->block_count
= 0;
2335 emit_cf_list(ctx
, &func
->impl
->body
);
2336 emit_block(ctx
, func
->impl
->end_block
);
2338 break; /* TODO: Multi-function shaders */
2341 util_dynarray_init(compiled
, NULL
);
2343 /* MIR-level optimizations */
2345 bool progress
= false;
2350 mir_foreach_block(ctx
, block
) {
2351 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2352 progress
|= midgard_opt_copy_prop(ctx
, block
);
2353 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2354 progress
|= midgard_opt_combine_projection(ctx
, block
);
2355 progress
|= midgard_opt_varying_projection(ctx
, block
);
2359 mir_foreach_block(ctx
, block
) {
2360 midgard_lower_invert(ctx
, block
);
2361 midgard_lower_derivatives(ctx
, block
);
2364 /* Nested control-flow can result in dead branches at the end of the
2365 * block. This messes with our analysis and is just dead code, so cull
2367 mir_foreach_block(ctx
, block
) {
2368 midgard_opt_cull_dead_branch(ctx
, block
);
2371 /* Ensure we were lowered */
2372 mir_foreach_instr_global(ctx
, ins
) {
2373 assert(!ins
->invert
);
2377 schedule_program(ctx
);
2379 /* Now that all the bundles are scheduled and we can calculate block
2380 * sizes, emit actual branch instructions rather than placeholders */
2382 int br_block_idx
= 0;
2384 mir_foreach_block(ctx
, block
) {
2385 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2386 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2387 midgard_instruction
*ins
= bundle
->instructions
[c
];
2389 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2391 if (ins
->prepacked_branch
) continue;
2393 /* Parse some basic branch info */
2394 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2395 bool is_conditional
= ins
->branch
.conditional
;
2396 bool is_inverted
= ins
->branch
.invert_conditional
;
2397 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2399 /* Determine the block we're jumping to */
2400 int target_number
= ins
->branch
.target_block
;
2402 /* Report the destination tag */
2403 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2405 /* Count up the number of quadwords we're
2406 * jumping over = number of quadwords until
2407 * (br_block_idx, target_number) */
2409 int quadword_offset
= 0;
2412 /* Jump to the end of the shader. We
2413 * need to include not only the
2414 * following blocks, but also the
2415 * contents of our current block (since
2416 * discard can come in the middle of
2419 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2421 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2422 quadword_offset
+= quadword_size(bun
->tag
);
2425 mir_foreach_block_from(ctx
, blk
, b
) {
2426 quadword_offset
+= b
->quadword_count
;
2429 } else if (target_number
> br_block_idx
) {
2432 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2433 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2436 quadword_offset
+= blk
->quadword_count
;
2439 /* Jump backwards */
2441 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2442 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2445 quadword_offset
-= blk
->quadword_count
;
2449 /* Unconditional extended branches (far jumps)
2450 * have issues, so we always use a conditional
2451 * branch, setting the condition to always for
2452 * unconditional. For compact unconditional
2453 * branches, cond isn't used so it doesn't
2454 * matter what we pick. */
2456 midgard_condition cond
=
2457 !is_conditional
? midgard_condition_always
:
2458 is_inverted
? midgard_condition_false
:
2459 midgard_condition_true
;
2461 midgard_jmp_writeout_op op
=
2462 is_discard
? midgard_jmp_writeout_op_discard
:
2463 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2464 midgard_jmp_writeout_op_branch_cond
;
2467 midgard_branch_extended branch
=
2468 midgard_create_branch_extended(
2473 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2474 } else if (is_conditional
|| is_discard
) {
2475 midgard_branch_cond branch
= {
2477 .dest_tag
= dest_tag
,
2478 .offset
= quadword_offset
,
2482 assert(branch
.offset
== quadword_offset
);
2484 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2486 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2488 midgard_branch_uncond branch
= {
2490 .dest_tag
= dest_tag
,
2491 .offset
= quadword_offset
,
2495 assert(branch
.offset
== quadword_offset
);
2497 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2505 /* Emit flat binary from the instruction arrays. Iterate each block in
2506 * sequence. Save instruction boundaries such that lookahead tags can
2507 * be assigned easily */
2509 /* Cache _all_ bundles in source order for lookahead across failed branches */
2511 int bundle_count
= 0;
2512 mir_foreach_block(ctx
, block
) {
2513 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2515 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2517 mir_foreach_block(ctx
, block
) {
2518 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2519 source_order_bundles
[bundle_idx
++] = bundle
;
2523 int current_bundle
= 0;
2525 /* Midgard prefetches instruction types, so during emission we
2526 * need to lookahead. Unless this is the last instruction, in
2527 * which we return 1. Or if this is the second to last and the
2528 * last is an ALU, then it's also 1... */
2530 mir_foreach_block(ctx
, block
) {
2531 mir_foreach_bundle_in_block(block
, bundle
) {
2534 if (current_bundle
+ 1 < bundle_count
) {
2535 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2537 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2544 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2548 /* TODO: Free deeper */
2549 //util_dynarray_fini(&block->instructions);
2552 free(source_order_bundles
);
2554 /* Report the very first tag executed */
2555 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2557 /* Deal with off-by-one related to the fencepost problem */
2558 program
->work_register_count
= ctx
->work_registers
+ 1;
2559 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2561 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2562 program
->tls_size
= ctx
->tls_size
;
2564 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2565 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);
2567 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2568 unsigned nr_bundles
= 0, nr_ins
= 0, nr_quadwords
= 0;
2570 /* Count instructions and bundles */
2572 mir_foreach_instr_global(ctx
, ins
) {
2576 mir_foreach_block(ctx
, block
) {
2577 nr_bundles
+= util_dynarray_num_elements(
2578 &block
->bundles
, midgard_bundle
);
2580 nr_quadwords
+= block
->quadword_count
;
2583 /* Calculate thread count. There are certain cutoffs by
2584 * register count for thread count */
2586 unsigned nr_registers
= program
->work_register_count
;
2588 unsigned nr_threads
=
2589 (nr_registers
<= 4) ? 4 :
2590 (nr_registers
<= 8) ? 2 :
2595 fprintf(stderr
, "shader%d - %s shader: "
2596 "%u inst, %u bundles, %u quadwords, "
2597 "%u registers, %u threads, %u loops, "
2598 "%d:%d spills:fills\n",
2600 gl_shader_stage_name(ctx
->stage
),
2601 nr_ins
, nr_bundles
, nr_quadwords
,
2602 nr_registers
, nr_threads
,
2604 ctx
->spills
, ctx
->fills
);