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[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 do {
387 progress = false;
388
389 NIR_PASS(progress, nir, nir_lower_var_copies);
390 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
391
392 NIR_PASS(progress, nir, nir_copy_prop);
393 NIR_PASS(progress, nir, nir_opt_remove_phis);
394 NIR_PASS(progress, nir, nir_opt_dce);
395 NIR_PASS(progress, nir, nir_opt_dead_cf);
396 NIR_PASS(progress, nir, nir_opt_cse);
397 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
398 NIR_PASS(progress, nir, nir_opt_algebraic);
399 NIR_PASS(progress, nir, nir_opt_constant_folding);
400
401 if (lower_flrp != 0) {
402 bool lower_flrp_progress = false;
403 NIR_PASS(lower_flrp_progress,
404 nir,
405 nir_lower_flrp,
406 lower_flrp,
407 false /* always_precise */,
408 nir->options->lower_ffma);
409 if (lower_flrp_progress) {
410 NIR_PASS(progress, nir,
411 nir_opt_constant_folding);
412 progress = true;
413 }
414
415 /* Nothing should rematerialize any flrps, so we only
416 * need to do this lowering once.
417 */
418 lower_flrp = 0;
419 }
420
421 NIR_PASS(progress, nir, nir_opt_undef);
422 NIR_PASS(progress, nir, nir_undef_to_zero);
423
424 NIR_PASS(progress, nir, nir_opt_loop_unroll,
425 nir_var_shader_in |
426 nir_var_shader_out |
427 nir_var_function_temp);
428
429 NIR_PASS(progress, nir, nir_opt_vectorize);
430 } while (progress);
431
432 /* Must be run at the end to prevent creation of fsin/fcos ops */
433 NIR_PASS(progress, nir, midgard_nir_scale_trig);
434
435 do {
436 progress = false;
437
438 NIR_PASS(progress, nir, nir_opt_dce);
439 NIR_PASS(progress, nir, nir_opt_algebraic);
440 NIR_PASS(progress, nir, nir_opt_constant_folding);
441 NIR_PASS(progress, nir, nir_copy_prop);
442 } while (progress);
443
444 NIR_PASS(progress, nir, nir_opt_algebraic_late);
445 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
446
447 /* We implement booleans as 32-bit 0/~0 */
448 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
449
450 /* Now that booleans are lowered, we can run out late opts */
451 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
452 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
453
454 NIR_PASS(progress, nir, nir_copy_prop);
455 NIR_PASS(progress, nir, nir_opt_dce);
456
457 /* Take us out of SSA */
458 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
459 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
460
461 /* We are a vector architecture; write combine where possible */
462 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
463 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
464
465 NIR_PASS(progress, nir, nir_opt_dce);
466 }
467
468 /* Do not actually emit a load; instead, cache the constant for inlining */
469
470 static void
471 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
472 {
473 nir_ssa_def def = instr->def;
474
475 midgard_constants *consts = rzalloc(NULL, midgard_constants);
476
477 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
478
479 #define RAW_CONST_COPY(bits) \
480 nir_const_value_to_array(consts->u##bits, instr->value, \
481 instr->def.num_components, u##bits)
482
483 switch (instr->def.bit_size) {
484 case 64:
485 RAW_CONST_COPY(64);
486 break;
487 case 32:
488 RAW_CONST_COPY(32);
489 break;
490 case 16:
491 RAW_CONST_COPY(16);
492 break;
493 case 8:
494 RAW_CONST_COPY(8);
495 break;
496 default:
497 unreachable("Invalid bit_size for load_const instruction\n");
498 }
499
500 /* Shifted for SSA, +1 for off-by-one */
501 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
502 }
503
504 /* Normally constants are embedded implicitly, but for I/O and such we have to
505 * explicitly emit a move with the constant source */
506
507 static void
508 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
509 {
510 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
511
512 if (constant_value) {
513 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
514 attach_constants(ctx, &ins, constant_value, node + 1);
515 emit_mir_instruction(ctx, ins);
516 }
517 }
518
519 static bool
520 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
521 {
522 unsigned comp = src->swizzle[0];
523
524 for (unsigned c = 1; c < nr_components; ++c) {
525 if (src->swizzle[c] != comp)
526 return true;
527 }
528
529 return false;
530 }
531
532 #define ALU_CASE(nir, _op) \
533 case nir_op_##nir: \
534 op = midgard_alu_op_##_op; \
535 assert(src_bitsize == dst_bitsize); \
536 break;
537
538 #define ALU_CHECK_CMP(sext) \
539 assert(src_bitsize == 16 || src_bitsize == 32); \
540 assert(dst_bitsize == 16 || dst_bitsize == 32); \
541
542 #define ALU_CASE_BCAST(nir, _op, count) \
543 case nir_op_##nir: \
544 op = midgard_alu_op_##_op; \
545 broadcast_swizzle = count; \
546 ALU_CHECK_CMP(true); \
547 break;
548
549 #define ALU_CASE_CMP(nir, _op, sext) \
550 case nir_op_##nir: \
551 op = midgard_alu_op_##_op; \
552 ALU_CHECK_CMP(sext); \
553 break;
554
555 /* Analyze the sizes of the dest and inputs to determine reg mode. */
556
557 static midgard_reg_mode
558 reg_mode_for_nir(nir_alu_instr *instr)
559 {
560 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
561 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
562 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
563
564 /* We don't have fp16 LUTs, so we'll want to emit code like:
565 *
566 * vlut.fsinr hr0, hr0
567 *
568 * where both input and output are 16-bit but the operation is carried
569 * out in 32-bit
570 */
571
572 switch (instr->op) {
573 case nir_op_fsqrt:
574 case nir_op_frcp:
575 case nir_op_frsq:
576 case nir_op_fsin:
577 case nir_op_fcos:
578 case nir_op_fexp2:
579 case nir_op_flog2:
580 max_bitsize = MAX2(max_bitsize, 32);
581 default:
582 break;
583 }
584
585 switch (max_bitsize) {
586 case 8:
587 return midgard_reg_mode_8;
588 case 16:
589 return midgard_reg_mode_16;
590 case 32:
591 return midgard_reg_mode_32;
592 case 64:
593 return midgard_reg_mode_64;
594 default:
595 unreachable("Invalid bit size");
596 }
597 }
598
599 /* Compare mir_lower_invert */
600 static bool
601 nir_accepts_inot(nir_op op, unsigned src)
602 {
603 switch (op) {
604 case nir_op_ior:
605 case nir_op_iand: /* TODO: b2f16 */
606 case nir_op_ixor:
607 return true;
608 case nir_op_b32csel:
609 /* Only the condition */
610 return (src == 0);
611 default:
612 return false;
613 }
614 }
615
616 static bool
617 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
618 {
619 if (pan_has_dest_mod(dest, op)) {
620 assert((*dest)->is_ssa);
621 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
622 return true;
623 }
624
625 return false;
626 }
627
628 static void
629 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
630 {
631 nir_alu_src src = instr->src[i];
632
633 if (!is_int) {
634 if (pan_has_source_mod(&src, nir_op_fneg))
635 *neg = !(*neg);
636
637 if (pan_has_source_mod(&src, nir_op_fabs))
638 *abs = true;
639 }
640
641 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
642 *not = true;
643
644 unsigned bits = nir_src_bit_size(src.src);
645
646 ins->src[to] = nir_src_index(NULL, &src.src);
647 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
648
649 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
650 ins->swizzle[to][c] = src.swizzle[
651 (!bcast_count || c < bcast_count) ? c :
652 (bcast_count - 1)];
653 }
654 }
655
656 /* Midgard features both fcsel and icsel, depending on whether you want int or
657 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
658 * we should emit an int or float csel depending on what modifiers could be
659 * placed. In the absense of modifiers, this is probably arbitrary. */
660
661 static bool
662 mir_is_bcsel_float(nir_alu_instr *instr)
663 {
664 nir_op intmods[] = {
665 nir_op_i2i8, nir_op_i2i16,
666 nir_op_i2i32, nir_op_i2i64
667 };
668
669 nir_op floatmods[] = {
670 nir_op_fabs, nir_op_fneg,
671 nir_op_f2f16, nir_op_f2f32,
672 nir_op_f2f64
673 };
674
675 nir_op floatdestmods[] = {
676 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
677 nir_op_f2f16, nir_op_f2f32
678 };
679
680 signed score = 0;
681
682 for (unsigned i = 1; i < 3; ++i) {
683 nir_alu_src s = instr->src[i];
684 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
685 if (pan_has_source_mod(&s, intmods[q]))
686 score--;
687 }
688 }
689
690 for (unsigned i = 1; i < 3; ++i) {
691 nir_alu_src s = instr->src[i];
692 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
693 if (pan_has_source_mod(&s, floatmods[q]))
694 score++;
695 }
696 }
697
698 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
699 nir_dest *dest = &instr->dest.dest;
700 if (pan_has_dest_mod(&dest, floatdestmods[q]))
701 score++;
702 }
703
704 return (score > 0);
705 }
706
707 static void
708 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
709 {
710 nir_dest *dest = &instr->dest.dest;
711
712 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
713 return;
714
715 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
716 * is handled elsewhere */
717
718 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
719 midgard_emit_derivatives(ctx, instr);
720 return;
721 }
722
723 bool is_ssa = dest->is_ssa;
724
725 unsigned nr_components = nir_dest_num_components(*dest);
726 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
727 unsigned op = 0;
728
729 /* Number of components valid to check for the instruction (the rest
730 * will be forced to the last), or 0 to use as-is. Relevant as
731 * ball-type instructions have a channel count in NIR but are all vec4
732 * in Midgard */
733
734 unsigned broadcast_swizzle = 0;
735
736 /* What register mode should we operate in? */
737 midgard_reg_mode reg_mode =
738 reg_mode_for_nir(instr);
739
740 /* Should we swap arguments? */
741 bool flip_src12 = false;
742
743 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
744 unsigned dst_bitsize = nir_dest_bit_size(*dest);
745
746 switch (instr->op) {
747 ALU_CASE(fadd, fadd);
748 ALU_CASE(fmul, fmul);
749 ALU_CASE(fmin, fmin);
750 ALU_CASE(fmax, fmax);
751 ALU_CASE(imin, imin);
752 ALU_CASE(imax, imax);
753 ALU_CASE(umin, umin);
754 ALU_CASE(umax, umax);
755 ALU_CASE(ffloor, ffloor);
756 ALU_CASE(fround_even, froundeven);
757 ALU_CASE(ftrunc, ftrunc);
758 ALU_CASE(fceil, fceil);
759 ALU_CASE(fdot3, fdot3);
760 ALU_CASE(fdot4, fdot4);
761 ALU_CASE(iadd, iadd);
762 ALU_CASE(isub, isub);
763 ALU_CASE(imul, imul);
764
765 /* Zero shoved as second-arg */
766 ALU_CASE(iabs, iabsdiff);
767
768 ALU_CASE(mov, imov);
769
770 ALU_CASE_CMP(feq32, feq, false);
771 ALU_CASE_CMP(fne32, fne, false);
772 ALU_CASE_CMP(flt32, flt, false);
773 ALU_CASE_CMP(ieq32, ieq, true);
774 ALU_CASE_CMP(ine32, ine, true);
775 ALU_CASE_CMP(ilt32, ilt, true);
776 ALU_CASE_CMP(ult32, ult, false);
777
778 /* We don't have a native b2f32 instruction. Instead, like many
779 * GPUs, we exploit booleans as 0/~0 for false/true, and
780 * correspondingly AND
781 * by 1.0 to do the type conversion. For the moment, prime us
782 * to emit:
783 *
784 * iand [whatever], #0
785 *
786 * At the end of emit_alu (as MIR), we'll fix-up the constant
787 */
788
789 ALU_CASE_CMP(b2f32, iand, true);
790 ALU_CASE_CMP(b2f16, iand, true);
791 ALU_CASE_CMP(b2i32, iand, true);
792
793 /* Likewise, we don't have a dedicated f2b32 instruction, but
794 * we can do a "not equal to 0.0" test. */
795
796 ALU_CASE_CMP(f2b32, fne, false);
797 ALU_CASE_CMP(i2b32, ine, true);
798
799 ALU_CASE(frcp, frcp);
800 ALU_CASE(frsq, frsqrt);
801 ALU_CASE(fsqrt, fsqrt);
802 ALU_CASE(fexp2, fexp2);
803 ALU_CASE(flog2, flog2);
804
805 ALU_CASE(f2i64, f2i_rtz);
806 ALU_CASE(f2u64, f2u_rtz);
807 ALU_CASE(i2f64, i2f_rtz);
808 ALU_CASE(u2f64, u2f_rtz);
809
810 ALU_CASE(f2i32, f2i_rtz);
811 ALU_CASE(f2u32, f2u_rtz);
812 ALU_CASE(i2f32, i2f_rtz);
813 ALU_CASE(u2f32, u2f_rtz);
814
815 ALU_CASE(f2i16, f2i_rtz);
816 ALU_CASE(f2u16, f2u_rtz);
817 ALU_CASE(i2f16, i2f_rtz);
818 ALU_CASE(u2f16, u2f_rtz);
819
820 ALU_CASE(fsin, fsin);
821 ALU_CASE(fcos, fcos);
822
823 /* We'll get 0 in the second arg, so:
824 * ~a = ~(a | 0) = nor(a, 0) */
825 ALU_CASE(inot, inor);
826 ALU_CASE(iand, iand);
827 ALU_CASE(ior, ior);
828 ALU_CASE(ixor, ixor);
829 ALU_CASE(ishl, ishl);
830 ALU_CASE(ishr, iasr);
831 ALU_CASE(ushr, ilsr);
832
833 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
834 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
835 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
836
837 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
838 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
839 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
840
841 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
842 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
843 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
844
845 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
846 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
847 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
848
849 /* Source mods will be shoved in later */
850 ALU_CASE(fabs, fmov);
851 ALU_CASE(fneg, fmov);
852 ALU_CASE(fsat, fmov);
853 ALU_CASE(fsat_signed, fmov);
854 ALU_CASE(fclamp_pos, fmov);
855
856 /* For size conversion, we use a move. Ideally though we would squash
857 * these ops together; maybe that has to happen after in NIR as part of
858 * propagation...? An earlier algebraic pass ensured we step down by
859 * only / exactly one size. If stepping down, we use a dest override to
860 * reduce the size; if stepping up, we use a larger-sized move with a
861 * half source and a sign/zero-extension modifier */
862
863 case nir_op_i2i8:
864 case nir_op_i2i16:
865 case nir_op_i2i32:
866 case nir_op_i2i64:
867 case nir_op_u2u8:
868 case nir_op_u2u16:
869 case nir_op_u2u32:
870 case nir_op_u2u64:
871 case nir_op_f2f16:
872 case nir_op_f2f32:
873 case nir_op_f2f64: {
874 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
875 instr->op == nir_op_f2f64)
876 op = midgard_alu_op_fmov;
877 else
878 op = midgard_alu_op_imov;
879
880 break;
881 }
882
883 /* For greater-or-equal, we lower to less-or-equal and flip the
884 * arguments */
885
886 case nir_op_fge:
887 case nir_op_fge32:
888 case nir_op_ige32:
889 case nir_op_uge32: {
890 op =
891 instr->op == nir_op_fge ? midgard_alu_op_fle :
892 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
893 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
894 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
895 0;
896
897 flip_src12 = true;
898 ALU_CHECK_CMP(false);
899 break;
900 }
901
902 case nir_op_b32csel: {
903 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
904 bool is_float = mir_is_bcsel_float(instr);
905 op = is_float ?
906 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
907 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
908
909 break;
910 }
911
912 case nir_op_unpack_32_2x16:
913 case nir_op_unpack_32_4x8:
914 case nir_op_pack_32_2x16:
915 case nir_op_pack_32_4x8: {
916 op = midgard_alu_op_imov;
917 break;
918 }
919
920 default:
921 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
922 assert(0);
923 return;
924 }
925
926 /* Promote imov to fmov if it might help inline a constant */
927 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
928 && nir_src_bit_size(instr->src[0].src) == 32
929 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
930 nir_src_num_components(instr->src[0].src))) {
931 op = midgard_alu_op_fmov;
932 }
933
934 /* Midgard can perform certain modifiers on output of an ALU op */
935
936 unsigned outmod = 0;
937 bool is_int = midgard_is_integer_op(op);
938
939 if (midgard_is_integer_out_op(op)) {
940 outmod = midgard_outmod_int_wrap;
941 } else if (instr->op == nir_op_fsat) {
942 outmod = midgard_outmod_sat;
943 } else if (instr->op == nir_op_fsat_signed) {
944 outmod = midgard_outmod_sat_signed;
945 } else if (instr->op == nir_op_fclamp_pos) {
946 outmod = midgard_outmod_pos;
947 }
948
949 /* Fetch unit, quirks, etc information */
950 unsigned opcode_props = alu_opcode_props[op].props;
951 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
952
953 /* Look for floating point mods. We have the mods fsat, fsat_signed,
954 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
955 *
956 * fsat_signed(fpos(x)) = fsat(x)
957 * fsat_signed(fsat(x)) = fsat(x)
958 * fpos(fsat_signed(x)) = fsat(x)
959 * fpos(fsat(x)) = fsat(x)
960 * fsat(fsat_signed(x)) = fsat(x)
961 * fsat(fpos(x)) = fsat(x)
962 *
963 * So by cases any composition of output modifiers is equivalent to
964 * fsat alone.
965 */
966
967 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
968 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
969 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
970 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
971 bool prior = (outmod != midgard_outmod_none);
972 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
973
974 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
975 fpos ? midgard_outmod_pos :
976 ssat ? midgard_outmod_sat_signed :
977 outmod;
978 }
979
980 midgard_instruction ins = {
981 .type = TAG_ALU_4,
982 .dest = nir_dest_index(dest),
983 .dest_type = nir_op_infos[instr->op].output_type
984 | nir_dest_bit_size(*dest),
985 };
986
987 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
988 ins.src[i] = ~0;
989
990 if (quirk_flipped_r24) {
991 ins.src[0] = ~0;
992 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
993 } else {
994 for (unsigned i = 0; i < nr_inputs; ++i) {
995 unsigned to = i;
996
997 if (instr->op == nir_op_b32csel) {
998 /* The condition is the first argument; move
999 * the other arguments up one to be a binary
1000 * instruction for Midgard with the condition
1001 * last */
1002
1003 if (i == 0)
1004 to = 2;
1005 else if (flip_src12)
1006 to = 2 - i;
1007 else
1008 to = i - 1;
1009 } else if (flip_src12) {
1010 to = 1 - to;
1011 }
1012
1013 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1014
1015 /* (!c) ? a : b = c ? b : a */
1016 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1017 ins.src_invert[2] = false;
1018 flip_src12 ^= true;
1019 }
1020 }
1021 }
1022
1023 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1024 /* Lowered to move */
1025 if (instr->op == nir_op_fneg)
1026 ins.src_neg[1] ^= true;
1027
1028 if (instr->op == nir_op_fabs)
1029 ins.src_abs[1] = true;
1030 }
1031
1032 ins.mask = mask_of(nr_components);
1033
1034 midgard_vector_alu alu = {
1035 .op = op,
1036 .reg_mode = reg_mode,
1037 .outmod = outmod,
1038 };
1039
1040 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1041 * components that don't exist. Note modifier => SSA => !reg => no
1042 * writemask, so we don't have to worry about writemasks here.*/
1043
1044 if (!is_ssa)
1045 ins.mask &= instr->dest.write_mask;
1046
1047 ins.alu = alu;
1048
1049 /* Late fixup for emulated instructions */
1050
1051 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1052 /* Presently, our second argument is an inline #0 constant.
1053 * Switch over to an embedded 1.0 constant (that can't fit
1054 * inline, since we're 32-bit, not 16-bit like the inline
1055 * constants) */
1056
1057 ins.has_inline_constant = false;
1058 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1059 ins.src_types[1] = nir_type_float32;
1060 ins.has_constants = true;
1061
1062 if (instr->op == nir_op_b2f32)
1063 ins.constants.f32[0] = 1.0f;
1064 else
1065 ins.constants.i32[0] = 1;
1066
1067 for (unsigned c = 0; c < 16; ++c)
1068 ins.swizzle[1][c] = 0;
1069 } else if (instr->op == nir_op_b2f16) {
1070 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1071 ins.src_types[1] = nir_type_float16;
1072 ins.has_constants = true;
1073 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1074
1075 for (unsigned c = 0; c < 16; ++c)
1076 ins.swizzle[1][c] = 0;
1077 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1078 /* Lots of instructions need a 0 plonked in */
1079 ins.has_inline_constant = false;
1080 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1081 ins.src_types[1] = nir_type_uint32;
1082 ins.has_constants = true;
1083 ins.constants.u32[0] = 0;
1084
1085 for (unsigned c = 0; c < 16; ++c)
1086 ins.swizzle[1][c] = 0;
1087 } else if (instr->op == nir_op_pack_32_2x16) {
1088 ins.dest_type = nir_type_uint16;
1089 ins.mask = mask_of(nr_components * 2);
1090 } else if (instr->op == nir_op_pack_32_4x8) {
1091 ins.dest_type = nir_type_uint8;
1092 ins.mask = mask_of(nr_components * 4);
1093 } else if (instr->op == nir_op_unpack_32_2x16) {
1094 ins.dest_type = nir_type_uint32;
1095 ins.mask = mask_of(nr_components >> 1);
1096 } else if (instr->op == nir_op_unpack_32_4x8) {
1097 ins.dest_type = nir_type_uint32;
1098 ins.mask = mask_of(nr_components >> 2);
1099 }
1100
1101 /* Arrange for creation of iandnot/iornot */
1102 if (ins.src_invert[0] && !ins.src_invert[1]) {
1103 mir_flip(&ins);
1104 ins.src_invert[0] = false;
1105 ins.src_invert[1] = true;
1106 }
1107
1108 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1109 /* To avoid duplicating the lookup tables (probably), true LUT
1110 * instructions can only operate as if they were scalars. Lower
1111 * them here by changing the component. */
1112
1113 unsigned orig_mask = ins.mask;
1114
1115 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1116 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1117
1118 for (int i = 0; i < nr_components; ++i) {
1119 /* Mask the associated component, dropping the
1120 * instruction if needed */
1121
1122 ins.mask = 1 << i;
1123 ins.mask &= orig_mask;
1124
1125 if (!ins.mask)
1126 continue;
1127
1128 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1129 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1130
1131 emit_mir_instruction(ctx, ins);
1132 }
1133 } else {
1134 emit_mir_instruction(ctx, ins);
1135 }
1136 }
1137
1138 #undef ALU_CASE
1139
1140 static void
1141 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1142 {
1143 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1144 unsigned nir_mask = 0;
1145 unsigned dsize = 0;
1146
1147 if (is_read) {
1148 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1149 dsize = nir_dest_bit_size(intr->dest);
1150 } else {
1151 nir_mask = nir_intrinsic_write_mask(intr);
1152 dsize = 32;
1153 }
1154
1155 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1156 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1157 mir_set_bytemask(ins, bytemask);
1158 ins->dest_type = nir_type_uint | dsize;
1159 }
1160
1161 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1162 * optimized) versions of UBO #0 */
1163
1164 static midgard_instruction *
1165 emit_ubo_read(
1166 compiler_context *ctx,
1167 nir_instr *instr,
1168 unsigned dest,
1169 unsigned offset,
1170 nir_src *indirect_offset,
1171 unsigned indirect_shift,
1172 unsigned index)
1173 {
1174 /* TODO: half-floats */
1175
1176 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1177 ins.constants.u32[0] = offset;
1178
1179 if (instr->type == nir_instr_type_intrinsic)
1180 mir_set_intr_mask(instr, &ins, true);
1181
1182 if (indirect_offset) {
1183 ins.src[2] = nir_src_index(ctx, indirect_offset);
1184 ins.src_types[2] = nir_type_uint32;
1185 ins.load_store.arg_2 = (indirect_shift << 5);
1186 } else {
1187 ins.load_store.arg_2 = 0x1E;
1188 }
1189
1190 ins.load_store.arg_1 = index;
1191
1192 return emit_mir_instruction(ctx, ins);
1193 }
1194
1195 /* Globals are like UBOs if you squint. And shared memory is like globals if
1196 * you squint even harder */
1197
1198 static void
1199 emit_global(
1200 compiler_context *ctx,
1201 nir_instr *instr,
1202 bool is_read,
1203 unsigned srcdest,
1204 nir_src *offset,
1205 bool is_shared)
1206 {
1207 /* TODO: types */
1208
1209 midgard_instruction ins;
1210
1211 if (is_read)
1212 ins = m_ld_int4(srcdest, 0);
1213 else
1214 ins = m_st_int4(srcdest, 0);
1215
1216 mir_set_offset(ctx, &ins, offset, is_shared);
1217 mir_set_intr_mask(instr, &ins, is_read);
1218
1219 emit_mir_instruction(ctx, ins);
1220 }
1221
1222 static void
1223 emit_varying_read(
1224 compiler_context *ctx,
1225 unsigned dest, unsigned offset,
1226 unsigned nr_comp, unsigned component,
1227 nir_src *indirect_offset, nir_alu_type type, bool flat)
1228 {
1229 /* XXX: Half-floats? */
1230 /* TODO: swizzle, mask */
1231
1232 midgard_instruction ins = m_ld_vary_32(dest, offset);
1233 ins.mask = mask_of(nr_comp);
1234
1235 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1236 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1237
1238 midgard_varying_parameter p = {
1239 .is_varying = 1,
1240 .interpolation = midgard_interp_default,
1241 .flat = flat,
1242 };
1243
1244 unsigned u;
1245 memcpy(&u, &p, sizeof(p));
1246 ins.load_store.varying_parameters = u;
1247
1248 if (indirect_offset) {
1249 ins.src[2] = nir_src_index(ctx, indirect_offset);
1250 ins.src_types[2] = nir_type_uint32;
1251 } else
1252 ins.load_store.arg_2 = 0x1E;
1253
1254 ins.load_store.arg_1 = 0x9E;
1255
1256 /* Use the type appropriate load */
1257 switch (type) {
1258 case nir_type_uint:
1259 case nir_type_bool:
1260 ins.load_store.op = midgard_op_ld_vary_32u;
1261 break;
1262 case nir_type_int:
1263 ins.load_store.op = midgard_op_ld_vary_32i;
1264 break;
1265 case nir_type_float:
1266 ins.load_store.op = midgard_op_ld_vary_32;
1267 break;
1268 default:
1269 unreachable("Attempted to load unknown type");
1270 break;
1271 }
1272
1273 emit_mir_instruction(ctx, ins);
1274 }
1275
1276 static void
1277 emit_attr_read(
1278 compiler_context *ctx,
1279 unsigned dest, unsigned offset,
1280 unsigned nr_comp, nir_alu_type t)
1281 {
1282 midgard_instruction ins = m_ld_attr_32(dest, offset);
1283 ins.load_store.arg_1 = 0x1E;
1284 ins.load_store.arg_2 = 0x1E;
1285 ins.mask = mask_of(nr_comp);
1286
1287 /* Use the type appropriate load */
1288 switch (t) {
1289 case nir_type_uint:
1290 case nir_type_bool:
1291 ins.load_store.op = midgard_op_ld_attr_32u;
1292 break;
1293 case nir_type_int:
1294 ins.load_store.op = midgard_op_ld_attr_32i;
1295 break;
1296 case nir_type_float:
1297 ins.load_store.op = midgard_op_ld_attr_32;
1298 break;
1299 default:
1300 unreachable("Attempted to load unknown type");
1301 break;
1302 }
1303
1304 emit_mir_instruction(ctx, ins);
1305 }
1306
1307 static void
1308 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1309 unsigned nr_components, unsigned offset)
1310 {
1311 nir_dest nir_dest;
1312
1313 /* Figure out which uniform this is */
1314 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1315 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1316
1317 unsigned dest = nir_dest_index(&nir_dest);
1318
1319 /* Sysvals are prefix uniforms */
1320 unsigned uniform = ((uintptr_t) val) - 1;
1321
1322 /* Emit the read itself -- this is never indirect */
1323 midgard_instruction *ins =
1324 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1325
1326 ins->mask = mask_of(nr_components);
1327 }
1328
1329 static unsigned
1330 compute_builtin_arg(nir_op op)
1331 {
1332 switch (op) {
1333 case nir_intrinsic_load_work_group_id:
1334 return 0x14;
1335 case nir_intrinsic_load_local_invocation_id:
1336 return 0x10;
1337 default:
1338 unreachable("Invalid compute paramater loaded");
1339 }
1340 }
1341
1342 static void
1343 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1344 {
1345 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1346
1347 midgard_instruction *br = ctx->writeout_branch[rt];
1348
1349 assert(!br);
1350
1351 emit_explicit_constant(ctx, src, src);
1352
1353 struct midgard_instruction ins =
1354 v_branch(false, false);
1355
1356 ins.writeout = true;
1357
1358 /* Add dependencies */
1359 ins.src[0] = src;
1360 ins.src_types[0] = nir_type_uint32;
1361 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1362 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1363
1364 /* Emit the branch */
1365 br = emit_mir_instruction(ctx, ins);
1366 schedule_barrier(ctx);
1367 ctx->writeout_branch[rt] = br;
1368
1369 /* Push our current location = current block count - 1 = where we'll
1370 * jump to. Maybe a bit too clever for my own good */
1371
1372 br->branch.target_block = ctx->block_count - 1;
1373 }
1374
1375 static void
1376 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1377 {
1378 unsigned reg = nir_dest_index(&instr->dest);
1379 midgard_instruction ins = m_ld_compute_id(reg, 0);
1380 ins.mask = mask_of(3);
1381 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1382 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1383 emit_mir_instruction(ctx, ins);
1384 }
1385
1386 static unsigned
1387 vertex_builtin_arg(nir_op op)
1388 {
1389 switch (op) {
1390 case nir_intrinsic_load_vertex_id:
1391 return PAN_VERTEX_ID;
1392 case nir_intrinsic_load_instance_id:
1393 return PAN_INSTANCE_ID;
1394 default:
1395 unreachable("Invalid vertex builtin");
1396 }
1397 }
1398
1399 static void
1400 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1401 {
1402 unsigned reg = nir_dest_index(&instr->dest);
1403 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1404 }
1405
1406 static void
1407 emit_control_barrier(compiler_context *ctx)
1408 {
1409 midgard_instruction ins = {
1410 .type = TAG_TEXTURE_4,
1411 .dest = ~0,
1412 .src = { ~0, ~0, ~0, ~0 },
1413 .texture = {
1414 .op = TEXTURE_OP_BARRIER,
1415
1416 /* TODO: optimize */
1417 .barrier_buffer = 1,
1418 .barrier_shared = 1
1419 }
1420 };
1421
1422 emit_mir_instruction(ctx, ins);
1423 }
1424
1425 static const nir_variable *
1426 search_var(struct exec_list *vars, unsigned driver_loc)
1427 {
1428 nir_foreach_variable(var, vars) {
1429 if (var->data.driver_location == driver_loc)
1430 return var;
1431 }
1432
1433 return NULL;
1434 }
1435
1436 static unsigned
1437 mir_get_branch_cond(nir_src *src, bool *invert)
1438 {
1439 /* Wrap it. No swizzle since it's a scalar */
1440
1441 nir_alu_src alu = {
1442 .src = *src
1443 };
1444
1445 *invert = pan_has_source_mod(&alu, nir_op_inot);
1446 return nir_src_index(NULL, &alu.src);
1447 }
1448
1449 static void
1450 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1451 {
1452 unsigned offset = 0, reg;
1453
1454 switch (instr->intrinsic) {
1455 case nir_intrinsic_discard_if:
1456 case nir_intrinsic_discard: {
1457 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1458 struct midgard_instruction discard = v_branch(conditional, false);
1459 discard.branch.target_type = TARGET_DISCARD;
1460
1461 if (conditional) {
1462 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1463 &discard.branch.invert_conditional);
1464 discard.src_types[0] = nir_type_uint32;
1465 }
1466
1467 emit_mir_instruction(ctx, discard);
1468 schedule_barrier(ctx);
1469
1470 break;
1471 }
1472
1473 case nir_intrinsic_load_uniform:
1474 case nir_intrinsic_load_ubo:
1475 case nir_intrinsic_load_global:
1476 case nir_intrinsic_load_shared:
1477 case nir_intrinsic_load_input:
1478 case nir_intrinsic_load_interpolated_input: {
1479 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1480 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1481 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1482 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1483 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1484 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1485
1486 /* Get the base type of the intrinsic */
1487 /* TODO: Infer type? Does it matter? */
1488 nir_alu_type t =
1489 (is_ubo || is_global || is_shared) ? nir_type_uint :
1490 (is_interp) ? nir_type_float :
1491 nir_intrinsic_type(instr);
1492
1493 t = nir_alu_type_get_base_type(t);
1494
1495 if (!(is_ubo || is_global)) {
1496 offset = nir_intrinsic_base(instr);
1497 }
1498
1499 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1500
1501 nir_src *src_offset = nir_get_io_offset_src(instr);
1502
1503 bool direct = nir_src_is_const(*src_offset);
1504 nir_src *indirect_offset = direct ? NULL : src_offset;
1505
1506 if (direct)
1507 offset += nir_src_as_uint(*src_offset);
1508
1509 /* We may need to apply a fractional offset */
1510 int component = (is_flat || is_interp) ?
1511 nir_intrinsic_component(instr) : 0;
1512 reg = nir_dest_index(&instr->dest);
1513
1514 if (is_uniform && !ctx->is_blend) {
1515 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1516 } else if (is_ubo) {
1517 nir_src index = instr->src[0];
1518
1519 /* TODO: Is indirect block number possible? */
1520 assert(nir_src_is_const(index));
1521
1522 uint32_t uindex = nir_src_as_uint(index) + 1;
1523 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1524 } else if (is_global || is_shared) {
1525 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1526 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1527 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1528 } else if (ctx->is_blend) {
1529 /* For blend shaders, load the input color, which is
1530 * preloaded to r0 */
1531
1532 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1533 emit_mir_instruction(ctx, move);
1534 schedule_barrier(ctx);
1535 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1536 emit_attr_read(ctx, reg, offset, nr_comp, t);
1537 } else {
1538 DBG("Unknown load\n");
1539 assert(0);
1540 }
1541
1542 break;
1543 }
1544
1545 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1546 case nir_intrinsic_load_barycentric_pixel:
1547 case nir_intrinsic_load_barycentric_centroid:
1548 break;
1549
1550 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1551
1552 case nir_intrinsic_load_raw_output_pan:
1553 case nir_intrinsic_load_output_u8_as_fp16_pan:
1554 reg = nir_dest_index(&instr->dest);
1555 assert(ctx->is_blend);
1556
1557 /* T720 and below use different blend opcodes with slightly
1558 * different semantics than T760 and up */
1559
1560 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1561 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1562
1563 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1564 ld.load_store.op = old_blend ?
1565 midgard_op_ld_color_buffer_u8_as_fp16_old :
1566 midgard_op_ld_color_buffer_u8_as_fp16;
1567
1568 if (old_blend) {
1569 ld.load_store.address = 1;
1570 ld.load_store.arg_2 = 0x1E;
1571 }
1572
1573 for (unsigned c = 4; c < 16; ++c)
1574 ld.swizzle[0][c] = 0;
1575
1576 ld.dest_type = nir_type_float16;
1577 }
1578
1579 emit_mir_instruction(ctx, ld);
1580 break;
1581
1582 case nir_intrinsic_load_blend_const_color_rgba: {
1583 assert(ctx->is_blend);
1584 reg = nir_dest_index(&instr->dest);
1585
1586 /* Blend constants are embedded directly in the shader and
1587 * patched in, so we use some magic routing */
1588
1589 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1590 ins.has_constants = true;
1591 ins.has_blend_constant = true;
1592 emit_mir_instruction(ctx, ins);
1593 break;
1594 }
1595
1596 case nir_intrinsic_store_zs_output_pan: {
1597 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1598 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1599 MIDGARD_ZS_RT);
1600
1601 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1602
1603 if (!nir_intrinsic_component(instr))
1604 br->writeout_depth = true;
1605 if (nir_intrinsic_component(instr) ||
1606 instr->num_components)
1607 br->writeout_stencil = true;
1608 assert(br->writeout_depth | br->writeout_stencil);
1609 break;
1610 }
1611
1612 case nir_intrinsic_store_output:
1613 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1614
1615 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1616
1617 reg = nir_src_index(ctx, &instr->src[0]);
1618
1619 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1620 const nir_variable *var;
1621 enum midgard_rt_id rt;
1622
1623 var = search_var(&ctx->nir->outputs,
1624 nir_intrinsic_base(instr));
1625 assert(var);
1626 if (var->data.location == FRAG_RESULT_COLOR)
1627 rt = MIDGARD_COLOR_RT0;
1628 else if (var->data.location >= FRAG_RESULT_DATA0)
1629 rt = MIDGARD_COLOR_RT0 + var->data.location -
1630 FRAG_RESULT_DATA0;
1631 else
1632 assert(0);
1633
1634 emit_fragment_store(ctx, reg, rt);
1635 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1636 /* We should have been vectorized, though we don't
1637 * currently check that st_vary is emitted only once
1638 * per slot (this is relevant, since there's not a mask
1639 * parameter available on the store [set to 0 by the
1640 * blob]). We do respect the component by adjusting the
1641 * swizzle. If this is a constant source, we'll need to
1642 * emit that explicitly. */
1643
1644 emit_explicit_constant(ctx, reg, reg);
1645
1646 unsigned dst_component = nir_intrinsic_component(instr);
1647 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1648
1649 midgard_instruction st = m_st_vary_32(reg, offset);
1650 st.load_store.arg_1 = 0x9E;
1651 st.load_store.arg_2 = 0x1E;
1652
1653 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1654 case nir_type_uint:
1655 case nir_type_bool:
1656 st.load_store.op = midgard_op_st_vary_32u;
1657 break;
1658 case nir_type_int:
1659 st.load_store.op = midgard_op_st_vary_32i;
1660 break;
1661 case nir_type_float:
1662 st.load_store.op = midgard_op_st_vary_32;
1663 break;
1664 default:
1665 unreachable("Attempted to store unknown type");
1666 break;
1667 }
1668
1669 /* nir_intrinsic_component(store_intr) encodes the
1670 * destination component start. Source component offset
1671 * adjustment is taken care of in
1672 * install_registers_instr(), when offset_swizzle() is
1673 * called.
1674 */
1675 unsigned src_component = COMPONENT_X;
1676
1677 assert(nr_comp > 0);
1678 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1679 st.swizzle[0][i] = src_component;
1680 if (i >= dst_component && i < dst_component + nr_comp - 1)
1681 src_component++;
1682 }
1683
1684 emit_mir_instruction(ctx, st);
1685 } else {
1686 DBG("Unknown store\n");
1687 assert(0);
1688 }
1689
1690 break;
1691
1692 /* Special case of store_output for lowered blend shaders */
1693 case nir_intrinsic_store_raw_output_pan:
1694 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1695 reg = nir_src_index(ctx, &instr->src[0]);
1696
1697 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1698 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1699 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1700 * of:
1701 *
1702 * imov r0.xyzw, r0.xxxx
1703 */
1704
1705 unsigned expanded = make_compiler_temp(ctx);
1706
1707 midgard_instruction splatter = v_mov(reg, expanded);
1708
1709 for (unsigned c = 0; c < 16; ++c)
1710 splatter.swizzle[1][c] = 0;
1711
1712 emit_mir_instruction(ctx, splatter);
1713 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1714 } else
1715 emit_fragment_store(ctx, reg, ctx->blend_rt);
1716
1717 break;
1718
1719 case nir_intrinsic_store_global:
1720 case nir_intrinsic_store_shared:
1721 reg = nir_src_index(ctx, &instr->src[0]);
1722 emit_explicit_constant(ctx, reg, reg);
1723
1724 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1725 break;
1726
1727 case nir_intrinsic_load_ssbo_address:
1728 emit_sysval_read(ctx, &instr->instr, 1, 0);
1729 break;
1730
1731 case nir_intrinsic_get_buffer_size:
1732 emit_sysval_read(ctx, &instr->instr, 1, 8);
1733 break;
1734
1735 case nir_intrinsic_load_viewport_scale:
1736 case nir_intrinsic_load_viewport_offset:
1737 case nir_intrinsic_load_num_work_groups:
1738 case nir_intrinsic_load_sampler_lod_parameters_pan:
1739 emit_sysval_read(ctx, &instr->instr, 3, 0);
1740 break;
1741
1742 case nir_intrinsic_load_work_group_id:
1743 case nir_intrinsic_load_local_invocation_id:
1744 emit_compute_builtin(ctx, instr);
1745 break;
1746
1747 case nir_intrinsic_load_vertex_id:
1748 case nir_intrinsic_load_instance_id:
1749 emit_vertex_builtin(ctx, instr);
1750 break;
1751
1752 case nir_intrinsic_memory_barrier_buffer:
1753 case nir_intrinsic_memory_barrier_shared:
1754 break;
1755
1756 case nir_intrinsic_control_barrier:
1757 schedule_barrier(ctx);
1758 emit_control_barrier(ctx);
1759 schedule_barrier(ctx);
1760 break;
1761
1762 default:
1763 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1764 assert(0);
1765 break;
1766 }
1767 }
1768
1769 static unsigned
1770 midgard_tex_format(enum glsl_sampler_dim dim)
1771 {
1772 switch (dim) {
1773 case GLSL_SAMPLER_DIM_1D:
1774 case GLSL_SAMPLER_DIM_BUF:
1775 return MALI_TEX_1D;
1776
1777 case GLSL_SAMPLER_DIM_2D:
1778 case GLSL_SAMPLER_DIM_EXTERNAL:
1779 case GLSL_SAMPLER_DIM_RECT:
1780 return MALI_TEX_2D;
1781
1782 case GLSL_SAMPLER_DIM_3D:
1783 return MALI_TEX_3D;
1784
1785 case GLSL_SAMPLER_DIM_CUBE:
1786 return MALI_TEX_CUBE;
1787
1788 default:
1789 DBG("Unknown sampler dim type\n");
1790 assert(0);
1791 return 0;
1792 }
1793 }
1794
1795 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1796 * was successful */
1797
1798 static bool
1799 pan_attach_constant_bias(
1800 compiler_context *ctx,
1801 nir_src lod,
1802 midgard_texture_word *word)
1803 {
1804 /* To attach as constant, it has to *be* constant */
1805
1806 if (!nir_src_is_const(lod))
1807 return false;
1808
1809 float f = nir_src_as_float(lod);
1810
1811 /* Break into fixed-point */
1812 signed lod_int = f;
1813 float lod_frac = f - lod_int;
1814
1815 /* Carry over negative fractions */
1816 if (lod_frac < 0.0) {
1817 lod_int--;
1818 lod_frac += 1.0;
1819 }
1820
1821 /* Encode */
1822 word->bias = float_to_ubyte(lod_frac);
1823 word->bias_int = lod_int;
1824
1825 return true;
1826 }
1827
1828 static void
1829 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1830 unsigned midgard_texop)
1831 {
1832 /* TODO */
1833 //assert (!instr->sampler);
1834
1835 int texture_index = instr->texture_index;
1836 int sampler_index = texture_index;
1837
1838 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1839 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1840
1841 midgard_instruction ins = {
1842 .type = TAG_TEXTURE_4,
1843 .mask = 0xF,
1844 .dest = nir_dest_index(&instr->dest),
1845 .src = { ~0, ~0, ~0, ~0 },
1846 .dest_type = dest_type,
1847 .swizzle = SWIZZLE_IDENTITY_4,
1848 .texture = {
1849 .op = midgard_texop,
1850 .format = midgard_tex_format(instr->sampler_dim),
1851 .texture_handle = texture_index,
1852 .sampler_handle = sampler_index,
1853 .shadow = instr->is_shadow,
1854 }
1855 };
1856
1857 if (instr->is_shadow && !instr->is_new_style_shadow)
1858 for (int i = 0; i < 4; ++i)
1859 ins.swizzle[0][i] = COMPONENT_X;
1860
1861 /* We may need a temporary for the coordinate */
1862
1863 bool needs_temp_coord =
1864 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1865 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1866 (instr->is_shadow);
1867
1868 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1869
1870 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1871 int index = nir_src_index(ctx, &instr->src[i].src);
1872 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1873 unsigned sz = nir_src_bit_size(instr->src[i].src);
1874 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1875
1876 switch (instr->src[i].src_type) {
1877 case nir_tex_src_coord: {
1878 emit_explicit_constant(ctx, index, index);
1879
1880 unsigned coord_mask = mask_of(instr->coord_components);
1881
1882 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1883
1884 if (flip_zw)
1885 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1886
1887 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1888 /* texelFetch is undefined on samplerCube */
1889 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1890
1891 /* For cubemaps, we use a special ld/st op to
1892 * select the face and copy the xy into the
1893 * texture register */
1894
1895 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1896 ld.src[1] = index;
1897 ld.src_types[1] = T;
1898 ld.mask = 0x3; /* xy */
1899 ld.load_store.arg_1 = 0x20;
1900 ld.swizzle[1][3] = COMPONENT_X;
1901 emit_mir_instruction(ctx, ld);
1902
1903 /* xyzw -> xyxx */
1904 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1905 ins.swizzle[1][3] = COMPONENT_X;
1906 } else if (needs_temp_coord) {
1907 /* mov coord_temp, coords */
1908 midgard_instruction mov = v_mov(index, coords);
1909 mov.mask = coord_mask;
1910
1911 if (flip_zw)
1912 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1913
1914 emit_mir_instruction(ctx, mov);
1915 } else {
1916 coords = index;
1917 }
1918
1919 ins.src[1] = coords;
1920 ins.src_types[1] = T;
1921
1922 /* Texelfetch coordinates uses all four elements
1923 * (xyz/index) regardless of texture dimensionality,
1924 * which means it's necessary to zero the unused
1925 * components to keep everything happy */
1926
1927 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1928 /* mov index.zw, #0, or generalized */
1929 midgard_instruction mov =
1930 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1931 mov.has_constants = true;
1932 mov.mask = coord_mask ^ 0xF;
1933 emit_mir_instruction(ctx, mov);
1934 }
1935
1936 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1937 /* Array component in w but NIR wants it in z,
1938 * but if we have a temp coord we already fixed
1939 * that up */
1940
1941 if (nr_components == 3) {
1942 ins.swizzle[1][2] = COMPONENT_Z;
1943 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1944 } else if (nr_components == 2) {
1945 ins.swizzle[1][2] =
1946 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1947 ins.swizzle[1][3] = COMPONENT_X;
1948 } else
1949 unreachable("Invalid texture 2D components");
1950 }
1951
1952 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1953 /* We zeroed */
1954 ins.swizzle[1][2] = COMPONENT_Z;
1955 ins.swizzle[1][3] = COMPONENT_W;
1956 }
1957
1958 break;
1959 }
1960
1961 case nir_tex_src_bias:
1962 case nir_tex_src_lod: {
1963 /* Try as a constant if we can */
1964
1965 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1966 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1967 break;
1968
1969 ins.texture.lod_register = true;
1970 ins.src[2] = index;
1971 ins.src_types[2] = T;
1972
1973 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1974 ins.swizzle[2][c] = COMPONENT_X;
1975
1976 emit_explicit_constant(ctx, index, index);
1977
1978 break;
1979 };
1980
1981 case nir_tex_src_offset: {
1982 ins.texture.offset_register = true;
1983 ins.src[3] = index;
1984 ins.src_types[3] = T;
1985
1986 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1987 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1988
1989 emit_explicit_constant(ctx, index, index);
1990 break;
1991 };
1992
1993 case nir_tex_src_comparator: {
1994 unsigned comp = COMPONENT_Z;
1995
1996 /* mov coord_temp.foo, coords */
1997 midgard_instruction mov = v_mov(index, coords);
1998 mov.mask = 1 << comp;
1999
2000 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2001 mov.swizzle[1][i] = COMPONENT_X;
2002
2003 emit_mir_instruction(ctx, mov);
2004 break;
2005 }
2006
2007 default: {
2008 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2009 assert(0);
2010 }
2011 }
2012 }
2013
2014 emit_mir_instruction(ctx, ins);
2015 }
2016
2017 static void
2018 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2019 {
2020 switch (instr->op) {
2021 case nir_texop_tex:
2022 case nir_texop_txb:
2023 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2024 break;
2025 case nir_texop_txl:
2026 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2027 break;
2028 case nir_texop_txf:
2029 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2030 break;
2031 case nir_texop_txs:
2032 emit_sysval_read(ctx, &instr->instr, 4, 0);
2033 break;
2034 default: {
2035 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2036 assert(0);
2037 }
2038 }
2039 }
2040
2041 static void
2042 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2043 {
2044 switch (instr->type) {
2045 case nir_jump_break: {
2046 /* Emit a branch out of the loop */
2047 struct midgard_instruction br = v_branch(false, false);
2048 br.branch.target_type = TARGET_BREAK;
2049 br.branch.target_break = ctx->current_loop_depth;
2050 emit_mir_instruction(ctx, br);
2051 break;
2052 }
2053
2054 default:
2055 DBG("Unknown jump type %d\n", instr->type);
2056 break;
2057 }
2058 }
2059
2060 static void
2061 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2062 {
2063 switch (instr->type) {
2064 case nir_instr_type_load_const:
2065 emit_load_const(ctx, nir_instr_as_load_const(instr));
2066 break;
2067
2068 case nir_instr_type_intrinsic:
2069 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2070 break;
2071
2072 case nir_instr_type_alu:
2073 emit_alu(ctx, nir_instr_as_alu(instr));
2074 break;
2075
2076 case nir_instr_type_tex:
2077 emit_tex(ctx, nir_instr_as_tex(instr));
2078 break;
2079
2080 case nir_instr_type_jump:
2081 emit_jump(ctx, nir_instr_as_jump(instr));
2082 break;
2083
2084 case nir_instr_type_ssa_undef:
2085 /* Spurious */
2086 break;
2087
2088 default:
2089 DBG("Unhandled instruction type\n");
2090 break;
2091 }
2092 }
2093
2094
2095 /* ALU instructions can inline or embed constants, which decreases register
2096 * pressure and saves space. */
2097
2098 #define CONDITIONAL_ATTACH(idx) { \
2099 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2100 \
2101 if (entry) { \
2102 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2103 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2104 } \
2105 }
2106
2107 static void
2108 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2109 {
2110 mir_foreach_instr_in_block(block, alu) {
2111 /* Other instructions cannot inline constants */
2112 if (alu->type != TAG_ALU_4) continue;
2113 if (alu->compact_branch) continue;
2114
2115 /* If there is already a constant here, we can do nothing */
2116 if (alu->has_constants) continue;
2117
2118 CONDITIONAL_ATTACH(0);
2119
2120 if (!alu->has_constants) {
2121 CONDITIONAL_ATTACH(1)
2122 } else if (!alu->inline_constant) {
2123 /* Corner case: _two_ vec4 constants, for instance with a
2124 * csel. For this case, we can only use a constant
2125 * register for one, we'll have to emit a move for the
2126 * other. */
2127
2128 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2129 unsigned scratch = make_compiler_temp(ctx);
2130
2131 if (entry) {
2132 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2133 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2134
2135 /* Set the source */
2136 alu->src[1] = scratch;
2137
2138 /* Inject us -before- the last instruction which set r31 */
2139 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2140 }
2141 }
2142 }
2143 }
2144
2145 /* Midgard supports two types of constants, embedded constants (128-bit) and
2146 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2147 * constants can be demoted to inline constants, for space savings and
2148 * sometimes a performance boost */
2149
2150 static void
2151 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2152 {
2153 mir_foreach_instr_in_block(block, ins) {
2154 if (!ins->has_constants) continue;
2155 if (ins->has_inline_constant) continue;
2156
2157 /* Blend constants must not be inlined by definition */
2158 if (ins->has_blend_constant) continue;
2159
2160 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2161 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2162 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2163
2164 if (!(is_16 || is_32))
2165 continue;
2166
2167 /* src1 cannot be an inline constant due to encoding
2168 * restrictions. So, if possible we try to flip the arguments
2169 * in that case */
2170
2171 int op = ins->alu.op;
2172
2173 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2174 alu_opcode_props[op].props & OP_COMMUTES) {
2175 mir_flip(ins);
2176 }
2177
2178 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2179 /* Component is from the swizzle. Take a nonzero component */
2180 assert(ins->mask);
2181 unsigned first_comp = ffs(ins->mask) - 1;
2182 unsigned component = ins->swizzle[1][first_comp];
2183
2184 /* Scale constant appropriately, if we can legally */
2185 uint16_t scaled_constant = 0;
2186
2187 if (is_16) {
2188 scaled_constant = ins->constants.u16[component];
2189 } else if (midgard_is_integer_op(op)) {
2190 scaled_constant = ins->constants.u32[component];
2191
2192 /* Constant overflow after resize */
2193 if (scaled_constant != ins->constants.u32[component])
2194 continue;
2195 } else {
2196 float original = ins->constants.f32[component];
2197 scaled_constant = _mesa_float_to_half(original);
2198
2199 /* Check for loss of precision. If this is
2200 * mediump, we don't care, but for a highp
2201 * shader, we need to pay attention. NIR
2202 * doesn't yet tell us which mode we're in!
2203 * Practically this prevents most constants
2204 * from being inlined, sadly. */
2205
2206 float fp32 = _mesa_half_to_float(scaled_constant);
2207
2208 if (fp32 != original)
2209 continue;
2210 }
2211
2212 /* Should've been const folded */
2213 if (ins->src_abs[1] || ins->src_neg[1])
2214 continue;
2215
2216 /* Make sure that the constant is not itself a vector
2217 * by checking if all accessed values are the same. */
2218
2219 const midgard_constants *cons = &ins->constants;
2220 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2221
2222 bool is_vector = false;
2223 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2224
2225 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2226 /* We only care if this component is actually used */
2227 if (!(mask & (1 << c)))
2228 continue;
2229
2230 uint32_t test = is_16 ?
2231 cons->u16[ins->swizzle[1][c]] :
2232 cons->u32[ins->swizzle[1][c]];
2233
2234 if (test != value) {
2235 is_vector = true;
2236 break;
2237 }
2238 }
2239
2240 if (is_vector)
2241 continue;
2242
2243 /* Get rid of the embedded constant */
2244 ins->has_constants = false;
2245 ins->src[1] = ~0;
2246 ins->has_inline_constant = true;
2247 ins->inline_constant = scaled_constant;
2248 }
2249 }
2250 }
2251
2252 /* Dead code elimination for branches at the end of a block - only one branch
2253 * per block is legal semantically */
2254
2255 static void
2256 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2257 {
2258 bool branched = false;
2259
2260 mir_foreach_instr_in_block_safe(block, ins) {
2261 if (!midgard_is_branch_unit(ins->unit)) continue;
2262
2263 if (branched)
2264 mir_remove_instruction(ins);
2265
2266 branched = true;
2267 }
2268 }
2269
2270 static unsigned
2271 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2272 {
2273 /* Loop to ourselves */
2274 midgard_instruction *br = ctx->writeout_branch[rt];
2275 struct midgard_instruction ins = v_branch(false, false);
2276 ins.writeout = true;
2277 ins.writeout_depth = br->writeout_depth;
2278 ins.writeout_stencil = br->writeout_stencil;
2279 ins.branch.target_block = ctx->block_count - 1;
2280 ins.constants.u32[0] = br->constants.u32[0];
2281 emit_mir_instruction(ctx, ins);
2282
2283 ctx->current_block->epilogue = true;
2284 schedule_barrier(ctx);
2285 return ins.branch.target_block;
2286 }
2287
2288 static midgard_block *
2289 emit_block(compiler_context *ctx, nir_block *block)
2290 {
2291 midgard_block *this_block = ctx->after_block;
2292 ctx->after_block = NULL;
2293
2294 if (!this_block)
2295 this_block = create_empty_block(ctx);
2296
2297 list_addtail(&this_block->base.link, &ctx->blocks);
2298
2299 this_block->scheduled = false;
2300 ++ctx->block_count;
2301
2302 /* Set up current block */
2303 list_inithead(&this_block->base.instructions);
2304 ctx->current_block = this_block;
2305
2306 nir_foreach_instr(instr, block) {
2307 emit_instr(ctx, instr);
2308 ++ctx->instruction_count;
2309 }
2310
2311 return this_block;
2312 }
2313
2314 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2315
2316 static void
2317 emit_if(struct compiler_context *ctx, nir_if *nif)
2318 {
2319 midgard_block *before_block = ctx->current_block;
2320
2321 /* Speculatively emit the branch, but we can't fill it in until later */
2322 bool inv = false;
2323 EMIT(branch, true, true);
2324 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2325 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2326 then_branch->src_types[0] = nir_type_uint32;
2327 then_branch->branch.invert_conditional = !inv;
2328
2329 /* Emit the two subblocks. */
2330 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2331 midgard_block *end_then_block = ctx->current_block;
2332
2333 /* Emit a jump from the end of the then block to the end of the else */
2334 EMIT(branch, false, false);
2335 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2336
2337 /* Emit second block, and check if it's empty */
2338
2339 int else_idx = ctx->block_count;
2340 int count_in = ctx->instruction_count;
2341 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2342 midgard_block *end_else_block = ctx->current_block;
2343 int after_else_idx = ctx->block_count;
2344
2345 /* Now that we have the subblocks emitted, fix up the branches */
2346
2347 assert(then_block);
2348 assert(else_block);
2349
2350 if (ctx->instruction_count == count_in) {
2351 /* The else block is empty, so don't emit an exit jump */
2352 mir_remove_instruction(then_exit);
2353 then_branch->branch.target_block = after_else_idx;
2354 } else {
2355 then_branch->branch.target_block = else_idx;
2356 then_exit->branch.target_block = after_else_idx;
2357 }
2358
2359 /* Wire up the successors */
2360
2361 ctx->after_block = create_empty_block(ctx);
2362
2363 pan_block_add_successor(&before_block->base, &then_block->base);
2364 pan_block_add_successor(&before_block->base, &else_block->base);
2365
2366 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2367 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2368 }
2369
2370 static void
2371 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2372 {
2373 /* Remember where we are */
2374 midgard_block *start_block = ctx->current_block;
2375
2376 /* Allocate a loop number, growing the current inner loop depth */
2377 int loop_idx = ++ctx->current_loop_depth;
2378
2379 /* Get index from before the body so we can loop back later */
2380 int start_idx = ctx->block_count;
2381
2382 /* Emit the body itself */
2383 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2384
2385 /* Branch back to loop back */
2386 struct midgard_instruction br_back = v_branch(false, false);
2387 br_back.branch.target_block = start_idx;
2388 emit_mir_instruction(ctx, br_back);
2389
2390 /* Mark down that branch in the graph. */
2391 pan_block_add_successor(&start_block->base, &loop_block->base);
2392 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2393
2394 /* Find the index of the block about to follow us (note: we don't add
2395 * one; blocks are 0-indexed so we get a fencepost problem) */
2396 int break_block_idx = ctx->block_count;
2397
2398 /* Fix up the break statements we emitted to point to the right place,
2399 * now that we can allocate a block number for them */
2400 ctx->after_block = create_empty_block(ctx);
2401
2402 mir_foreach_block_from(ctx, start_block, _block) {
2403 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2404 if (ins->type != TAG_ALU_4) continue;
2405 if (!ins->compact_branch) continue;
2406
2407 /* We found a branch -- check the type to see if we need to do anything */
2408 if (ins->branch.target_type != TARGET_BREAK) continue;
2409
2410 /* It's a break! Check if it's our break */
2411 if (ins->branch.target_break != loop_idx) continue;
2412
2413 /* Okay, cool, we're breaking out of this loop.
2414 * Rewrite from a break to a goto */
2415
2416 ins->branch.target_type = TARGET_GOTO;
2417 ins->branch.target_block = break_block_idx;
2418
2419 pan_block_add_successor(_block, &ctx->after_block->base);
2420 }
2421 }
2422
2423 /* Now that we've finished emitting the loop, free up the depth again
2424 * so we play nice with recursion amid nested loops */
2425 --ctx->current_loop_depth;
2426
2427 /* Dump loop stats */
2428 ++ctx->loop_count;
2429 }
2430
2431 static midgard_block *
2432 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2433 {
2434 midgard_block *start_block = NULL;
2435
2436 foreach_list_typed(nir_cf_node, node, node, list) {
2437 switch (node->type) {
2438 case nir_cf_node_block: {
2439 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2440
2441 if (!start_block)
2442 start_block = block;
2443
2444 break;
2445 }
2446
2447 case nir_cf_node_if:
2448 emit_if(ctx, nir_cf_node_as_if(node));
2449 break;
2450
2451 case nir_cf_node_loop:
2452 emit_loop(ctx, nir_cf_node_as_loop(node));
2453 break;
2454
2455 case nir_cf_node_function:
2456 assert(0);
2457 break;
2458 }
2459 }
2460
2461 return start_block;
2462 }
2463
2464 /* Due to lookahead, we need to report the first tag executed in the command
2465 * stream and in branch targets. An initial block might be empty, so iterate
2466 * until we find one that 'works' */
2467
2468 static unsigned
2469 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2470 {
2471 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2472
2473 mir_foreach_block_from(ctx, initial_block, _v) {
2474 midgard_block *v = (midgard_block *) _v;
2475 if (v->quadword_count) {
2476 midgard_bundle *initial_bundle =
2477 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2478
2479 return initial_bundle->tag;
2480 }
2481 }
2482
2483 /* Default to a tag 1 which will break from the shader, in case we jump
2484 * to the exit block (i.e. `return` in a compute shader) */
2485
2486 return 1;
2487 }
2488
2489 /* For each fragment writeout instruction, generate a writeout loop to
2490 * associate with it */
2491
2492 static void
2493 mir_add_writeout_loops(compiler_context *ctx)
2494 {
2495 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2496 midgard_instruction *br = ctx->writeout_branch[rt];
2497 if (!br) continue;
2498
2499 unsigned popped = br->branch.target_block;
2500 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2501 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2502 br->branch.target_type = TARGET_GOTO;
2503
2504 /* If we have more RTs, we'll need to restore back after our
2505 * loop terminates */
2506
2507 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2508 midgard_instruction uncond = v_branch(false, false);
2509 uncond.branch.target_block = popped;
2510 uncond.branch.target_type = TARGET_GOTO;
2511 emit_mir_instruction(ctx, uncond);
2512 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2513 schedule_barrier(ctx);
2514 } else {
2515 /* We're last, so we can terminate here */
2516 br->last_writeout = true;
2517 }
2518 }
2519 }
2520
2521 int
2522 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2523 {
2524 struct util_dynarray *compiled = &program->compiled;
2525
2526 midgard_debug = debug_get_option_midgard_debug();
2527
2528 /* TODO: Bound against what? */
2529 compiler_context *ctx = rzalloc(NULL, compiler_context);
2530
2531 ctx->nir = nir;
2532 ctx->stage = nir->info.stage;
2533 ctx->is_blend = is_blend;
2534 ctx->alpha_ref = program->alpha_ref;
2535 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2536 ctx->quirks = midgard_get_quirks(gpu_id);
2537
2538 /* Start off with a safe cutoff, allowing usage of all 16 work
2539 * registers. Later, we'll promote uniform reads to uniform registers
2540 * if we determine it is beneficial to do so */
2541 ctx->uniform_cutoff = 8;
2542
2543 /* Initialize at a global (not block) level hash tables */
2544
2545 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2546 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2547
2548 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2549 * (so we don't accidentally duplicate the epilogue since mesa/st has
2550 * messed with our I/O quite a bit already) */
2551
2552 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2553
2554 if (ctx->stage == MESA_SHADER_VERTEX) {
2555 NIR_PASS_V(nir, nir_lower_viewport_transform);
2556 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2557 }
2558
2559 NIR_PASS_V(nir, nir_lower_var_copies);
2560 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2561 NIR_PASS_V(nir, nir_split_var_copies);
2562 NIR_PASS_V(nir, nir_lower_var_copies);
2563 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2564 NIR_PASS_V(nir, nir_lower_var_copies);
2565 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2566
2567 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2568 NIR_PASS_V(nir, nir_lower_ssbo);
2569 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2570
2571 /* Optimisation passes */
2572
2573 optimise_nir(nir, ctx->quirks);
2574
2575 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2576 nir_print_shader(nir, stdout);
2577 }
2578
2579 /* Assign sysvals and counts, now that we're sure
2580 * (post-optimisation) */
2581
2582 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2583 program->sysval_count = ctx->sysvals.sysval_count;
2584 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2585
2586 nir_foreach_function(func, nir) {
2587 if (!func->impl)
2588 continue;
2589
2590 list_inithead(&ctx->blocks);
2591 ctx->block_count = 0;
2592 ctx->func = func;
2593 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2594
2595 emit_cf_list(ctx, &func->impl->body);
2596 free(ctx->already_emitted);
2597 break; /* TODO: Multi-function shaders */
2598 }
2599
2600 util_dynarray_init(compiled, NULL);
2601
2602 /* Per-block lowering before opts */
2603
2604 mir_foreach_block(ctx, _block) {
2605 midgard_block *block = (midgard_block *) _block;
2606 inline_alu_constants(ctx, block);
2607 embedded_to_inline_constant(ctx, block);
2608 }
2609 /* MIR-level optimizations */
2610
2611 bool progress = false;
2612
2613 do {
2614 progress = false;
2615 progress |= midgard_opt_dead_code_eliminate(ctx);
2616
2617 mir_foreach_block(ctx, _block) {
2618 midgard_block *block = (midgard_block *) _block;
2619 progress |= midgard_opt_copy_prop(ctx, block);
2620 progress |= midgard_opt_combine_projection(ctx, block);
2621 progress |= midgard_opt_varying_projection(ctx, block);
2622 }
2623 } while (progress);
2624
2625 mir_foreach_block(ctx, _block) {
2626 midgard_block *block = (midgard_block *) _block;
2627 midgard_lower_derivatives(ctx, block);
2628 midgard_cull_dead_branch(ctx, block);
2629 }
2630
2631 if (ctx->stage == MESA_SHADER_FRAGMENT)
2632 mir_add_writeout_loops(ctx);
2633
2634 /* Analyze now that the code is known but before scheduling creates
2635 * pipeline registers which are harder to track */
2636 mir_analyze_helper_terminate(ctx);
2637 mir_analyze_helper_requirements(ctx);
2638
2639 /* Schedule! */
2640 midgard_schedule_program(ctx);
2641 mir_ra(ctx);
2642
2643 /* Now that all the bundles are scheduled and we can calculate block
2644 * sizes, emit actual branch instructions rather than placeholders */
2645
2646 int br_block_idx = 0;
2647
2648 mir_foreach_block(ctx, _block) {
2649 midgard_block *block = (midgard_block *) _block;
2650 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2651 for (int c = 0; c < bundle->instruction_count; ++c) {
2652 midgard_instruction *ins = bundle->instructions[c];
2653
2654 if (!midgard_is_branch_unit(ins->unit)) continue;
2655
2656 /* Parse some basic branch info */
2657 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2658 bool is_conditional = ins->branch.conditional;
2659 bool is_inverted = ins->branch.invert_conditional;
2660 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2661 bool is_writeout = ins->writeout;
2662
2663 /* Determine the block we're jumping to */
2664 int target_number = ins->branch.target_block;
2665
2666 /* Report the destination tag */
2667 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2668
2669 /* Count up the number of quadwords we're
2670 * jumping over = number of quadwords until
2671 * (br_block_idx, target_number) */
2672
2673 int quadword_offset = 0;
2674
2675 if (is_discard) {
2676 /* Ignored */
2677 } else if (target_number > br_block_idx) {
2678 /* Jump forward */
2679
2680 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2681 midgard_block *blk = mir_get_block(ctx, idx);
2682 assert(blk);
2683
2684 quadword_offset += blk->quadword_count;
2685 }
2686 } else {
2687 /* Jump backwards */
2688
2689 for (int idx = br_block_idx; idx >= target_number; --idx) {
2690 midgard_block *blk = mir_get_block(ctx, idx);
2691 assert(blk);
2692
2693 quadword_offset -= blk->quadword_count;
2694 }
2695 }
2696
2697 /* Unconditional extended branches (far jumps)
2698 * have issues, so we always use a conditional
2699 * branch, setting the condition to always for
2700 * unconditional. For compact unconditional
2701 * branches, cond isn't used so it doesn't
2702 * matter what we pick. */
2703
2704 midgard_condition cond =
2705 !is_conditional ? midgard_condition_always :
2706 is_inverted ? midgard_condition_false :
2707 midgard_condition_true;
2708
2709 midgard_jmp_writeout_op op =
2710 is_discard ? midgard_jmp_writeout_op_discard :
2711 is_writeout ? midgard_jmp_writeout_op_writeout :
2712 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2713 midgard_jmp_writeout_op_branch_cond;
2714
2715 if (!is_compact) {
2716 midgard_branch_extended branch =
2717 midgard_create_branch_extended(
2718 cond, op,
2719 dest_tag,
2720 quadword_offset);
2721
2722 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2723 } else if (is_conditional || is_discard) {
2724 midgard_branch_cond branch = {
2725 .op = op,
2726 .dest_tag = dest_tag,
2727 .offset = quadword_offset,
2728 .cond = cond
2729 };
2730
2731 assert(branch.offset == quadword_offset);
2732
2733 memcpy(&ins->br_compact, &branch, sizeof(branch));
2734 } else {
2735 assert(op == midgard_jmp_writeout_op_branch_uncond);
2736
2737 midgard_branch_uncond branch = {
2738 .op = op,
2739 .dest_tag = dest_tag,
2740 .offset = quadword_offset,
2741 .unknown = 1
2742 };
2743
2744 assert(branch.offset == quadword_offset);
2745
2746 memcpy(&ins->br_compact, &branch, sizeof(branch));
2747 }
2748 }
2749 }
2750
2751 ++br_block_idx;
2752 }
2753
2754 /* Emit flat binary from the instruction arrays. Iterate each block in
2755 * sequence. Save instruction boundaries such that lookahead tags can
2756 * be assigned easily */
2757
2758 /* Cache _all_ bundles in source order for lookahead across failed branches */
2759
2760 int bundle_count = 0;
2761 mir_foreach_block(ctx, _block) {
2762 midgard_block *block = (midgard_block *) _block;
2763 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2764 }
2765 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2766 int bundle_idx = 0;
2767 mir_foreach_block(ctx, _block) {
2768 midgard_block *block = (midgard_block *) _block;
2769 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2770 source_order_bundles[bundle_idx++] = bundle;
2771 }
2772 }
2773
2774 int current_bundle = 0;
2775
2776 /* Midgard prefetches instruction types, so during emission we
2777 * need to lookahead. Unless this is the last instruction, in
2778 * which we return 1. */
2779
2780 mir_foreach_block(ctx, _block) {
2781 midgard_block *block = (midgard_block *) _block;
2782 mir_foreach_bundle_in_block(block, bundle) {
2783 int lookahead = 1;
2784
2785 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2786 lookahead = source_order_bundles[current_bundle + 1]->tag;
2787
2788 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2789 ++current_bundle;
2790 }
2791
2792 /* TODO: Free deeper */
2793 //util_dynarray_fini(&block->instructions);
2794 }
2795
2796 free(source_order_bundles);
2797
2798 /* Report the very first tag executed */
2799 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2800
2801 /* Deal with off-by-one related to the fencepost problem */
2802 program->work_register_count = ctx->work_registers + 1;
2803 program->uniform_cutoff = ctx->uniform_cutoff;
2804
2805 program->blend_patch_offset = ctx->blend_constant_offset;
2806 program->tls_size = ctx->tls_size;
2807
2808 if (midgard_debug & MIDGARD_DBG_SHADERS)
2809 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2810
2811 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2812 unsigned nr_bundles = 0, nr_ins = 0;
2813
2814 /* Count instructions and bundles */
2815
2816 mir_foreach_block(ctx, _block) {
2817 midgard_block *block = (midgard_block *) _block;
2818 nr_bundles += util_dynarray_num_elements(
2819 &block->bundles, midgard_bundle);
2820
2821 mir_foreach_bundle_in_block(block, bun)
2822 nr_ins += bun->instruction_count;
2823 }
2824
2825 /* Calculate thread count. There are certain cutoffs by
2826 * register count for thread count */
2827
2828 unsigned nr_registers = program->work_register_count;
2829
2830 unsigned nr_threads =
2831 (nr_registers <= 4) ? 4 :
2832 (nr_registers <= 8) ? 2 :
2833 1;
2834
2835 /* Dump stats */
2836
2837 fprintf(stderr, "shader%d - %s shader: "
2838 "%u inst, %u bundles, %u quadwords, "
2839 "%u registers, %u threads, %u loops, "
2840 "%u:%u spills:fills\n",
2841 SHADER_DB_COUNT++,
2842 gl_shader_stage_name(ctx->stage),
2843 nr_ins, nr_bundles, ctx->quadword_count,
2844 nr_registers, nr_threads,
2845 ctx->loop_count,
2846 ctx->spills, ctx->fills);
2847 }
2848
2849 ralloc_free(ctx);
2850
2851 return 0;
2852 }