2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
51 #include "midgard_quirks.h"
53 #include "disassemble.h"
55 static const struct debug_named_value debug_options
[] = {
56 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
64 unsigned SHADER_DB_COUNT
= 0;
66 int midgard_debug
= 0;
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
74 midgard_is_branch_unit(unsigned unit
)
76 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 static midgard_block
*
80 create_empty_block(compiler_context
*ctx
)
82 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
84 blk
->predecessors
= _mesa_set_create(blk
,
86 _mesa_key_pointer_equal
);
88 blk
->source_id
= ctx
->block_source_count
++;
94 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
100 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
101 if (block
->successors
[i
] == successor
)
105 block
->successors
[block
->nr_successors
++] = successor
;
106 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
108 /* Note the predecessor in the other direction */
109 _mesa_set_add(successor
->predecessors
, block
);
113 schedule_barrier(compiler_context
*ctx
)
115 midgard_block
*temp
= ctx
->after_block
;
116 ctx
->after_block
= create_empty_block(ctx
);
118 list_addtail(&ctx
->after_block
->link
, &ctx
->blocks
);
119 list_inithead(&ctx
->after_block
->instructions
);
120 midgard_block_add_successor(ctx
->current_block
, ctx
->after_block
);
121 ctx
->current_block
= ctx
->after_block
;
122 ctx
->after_block
= temp
;
125 /* Helpers to generate midgard_instruction's using macro magic, since every
126 * driver seems to do it that way */
128 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
130 #define M_LOAD_STORE(name, store) \
131 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
132 midgard_instruction i = { \
133 .type = TAG_LOAD_STORE_4, \
136 .src = { ~0, ~0, ~0 }, \
137 .swizzle = SWIZZLE_IDENTITY_4, \
139 .op = midgard_op_##name, \
152 #define M_LOAD(name) M_LOAD_STORE(name, false)
153 #define M_STORE(name) M_LOAD_STORE(name, true)
155 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
156 * the corresponding Midgard source */
158 static midgard_vector_alu_src
159 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
160 bool half
, bool sext
)
162 /* Figure out how many components there are so we can adjust.
163 * Specifically we want to broadcast the last channel so things like
167 if (broadcast_count
&& src
) {
168 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
170 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
171 src
->swizzle
[c
] = last_component
;
175 midgard_vector_alu_src alu_src
= {
182 alu_src
.mod
= midgard_int_normal
;
184 /* Sign/zero-extend if needed */
188 midgard_int_sign_extend
189 : midgard_int_zero_extend
;
192 /* These should have been lowered away */
194 assert(!(src
->abs
|| src
->negate
));
197 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
203 /* load/store instructions have both 32-bit and 16-bit variants, depending on
204 * whether we are using vectors composed of highp or mediump. At the moment, we
205 * don't support half-floats -- this requires changes in other parts of the
206 * compiler -- therefore the 16-bit versions are commented out. */
208 //M_LOAD(ld_attr_16);
210 //M_LOAD(ld_vary_16);
215 M_LOAD(ld_color_buffer_8
);
216 //M_STORE(st_vary_16);
218 M_LOAD(ld_cubemap_coords
);
219 M_LOAD(ld_compute_id
);
221 static midgard_instruction
222 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
224 midgard_branch_cond branch
= {
232 memcpy(&compact
, &branch
, sizeof(branch
));
234 midgard_instruction ins
= {
236 .unit
= ALU_ENAB_BR_COMPACT
,
237 .prepacked_branch
= true,
238 .compact_branch
= true,
239 .br_compact
= compact
,
241 .src
= { ~0, ~0, ~0 },
244 if (op
== midgard_jmp_writeout_op_writeout
)
250 static midgard_instruction
251 v_branch(bool conditional
, bool invert
)
253 midgard_instruction ins
= {
255 .unit
= ALU_ENAB_BRANCH
,
256 .compact_branch
= true,
258 .conditional
= conditional
,
259 .invert_conditional
= invert
262 .src
= { ~0, ~0, ~0 },
268 static midgard_branch_extended
269 midgard_create_branch_extended( midgard_condition cond
,
270 midgard_jmp_writeout_op op
,
272 signed quadword_offset
)
274 /* The condition code is actually a LUT describing a function to
275 * combine multiple condition codes. However, we only support a single
276 * condition code at the moment, so we just duplicate over a bunch of
279 uint16_t duplicated_cond
=
289 midgard_branch_extended branch
= {
291 .dest_tag
= dest_tag
,
292 .offset
= quadword_offset
,
293 .cond
= duplicated_cond
300 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
302 ins
->has_constants
= true;
303 memcpy(&ins
->constants
, constants
, 16);
307 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
309 return glsl_count_attribute_slots(type
, false);
312 /* Lower fdot2 to a vector multiplication followed by channel addition */
314 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
316 if (alu
->op
!= nir_op_fdot2
)
319 b
->cursor
= nir_before_instr(&alu
->instr
);
321 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
322 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
324 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
326 nir_ssa_def
*sum
= nir_fadd(b
,
327 nir_channel(b
, product
, 0),
328 nir_channel(b
, product
, 1));
330 /* Replace the fdot2 with this sum */
331 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
335 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
337 /* This is way too meta */
338 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
339 unsigned idx_idx
= is_store
? 1 : 0;
341 nir_src index
= instr
->src
[idx_idx
];
342 assert(nir_src_is_const(index
));
343 uint32_t uindex
= nir_src_as_uint(index
);
345 return PAN_SYSVAL(SSBO
, uindex
);
349 midgard_sysval_for_sampler(nir_intrinsic_instr
*instr
)
351 /* TODO: indirect samplers !!! */
352 nir_src index
= instr
->src
[0];
353 assert(nir_src_is_const(index
));
354 uint32_t uindex
= nir_src_as_uint(index
);
356 return PAN_SYSVAL(SAMPLER
, uindex
);
360 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
362 switch (instr
->intrinsic
) {
363 case nir_intrinsic_load_viewport_scale
:
364 return PAN_SYSVAL_VIEWPORT_SCALE
;
365 case nir_intrinsic_load_viewport_offset
:
366 return PAN_SYSVAL_VIEWPORT_OFFSET
;
367 case nir_intrinsic_load_num_work_groups
:
368 return PAN_SYSVAL_NUM_WORK_GROUPS
;
369 case nir_intrinsic_load_ssbo
:
370 case nir_intrinsic_store_ssbo
:
371 return midgard_sysval_for_ssbo(instr
);
372 case nir_intrinsic_load_sampler_lod_parameters_pan
:
373 return midgard_sysval_for_sampler(instr
);
379 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
382 nir_intrinsic_instr
*intr
;
383 nir_dest
*dst
= NULL
;
387 bool is_store
= false;
389 switch (instr
->type
) {
390 case nir_instr_type_intrinsic
:
391 intr
= nir_instr_as_intrinsic(instr
);
392 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
394 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
396 case nir_instr_type_tex
:
397 tex
= nir_instr_as_tex(instr
);
398 if (tex
->op
!= nir_texop_txs
)
401 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
402 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
403 nir_tex_instr_dest_size(tex
) -
404 (tex
->is_array
? 1 : 0),
412 if (dest
&& dst
&& !is_store
)
413 *dest
= nir_dest_index(ctx
, dst
);
419 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
423 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
427 /* We have a sysval load; check if it's already been assigned */
429 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
432 /* It hasn't -- so assign it now! */
434 unsigned id
= ctx
->sysval_count
++;
435 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
436 ctx
->sysvals
[id
] = sysval
;
440 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
442 ctx
->sysval_count
= 0;
444 nir_foreach_function(function
, shader
) {
445 if (!function
->impl
) continue;
447 nir_foreach_block(block
, function
->impl
) {
448 nir_foreach_instr_safe(instr
, block
) {
449 midgard_nir_assign_sysval_body(ctx
, instr
);
456 midgard_nir_lower_fdot2(nir_shader
*shader
)
458 bool progress
= false;
460 nir_foreach_function(function
, shader
) {
461 if (!function
->impl
) continue;
464 nir_builder
*b
= &_b
;
465 nir_builder_init(b
, function
->impl
);
467 nir_foreach_block(block
, function
->impl
) {
468 nir_foreach_instr_safe(instr
, block
) {
469 if (instr
->type
!= nir_instr_type_alu
) continue;
471 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
472 midgard_nir_lower_fdot2_body(b
, alu
);
478 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
485 /* Flushes undefined values to zero */
488 optimise_nir(nir_shader
*nir
, unsigned quirks
)
491 unsigned lower_flrp
=
492 (nir
->options
->lower_flrp16
? 16 : 0) |
493 (nir
->options
->lower_flrp32
? 32 : 0) |
494 (nir
->options
->lower_flrp64
? 64 : 0);
496 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
497 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
498 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
500 nir_lower_tex_options lower_tex_options
= {
501 .lower_txs_lod
= true,
505 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
507 /* T720 is broken. */
509 if (quirks
& MIDGARD_BROKEN_LOD
)
510 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
515 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
516 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
518 NIR_PASS(progress
, nir
, nir_copy_prop
);
519 NIR_PASS(progress
, nir
, nir_opt_dce
);
520 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
521 NIR_PASS(progress
, nir
, nir_opt_cse
);
522 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
523 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
524 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
526 if (lower_flrp
!= 0) {
527 bool lower_flrp_progress
= false;
528 NIR_PASS(lower_flrp_progress
,
532 false /* always_precise */,
533 nir
->options
->lower_ffma
);
534 if (lower_flrp_progress
) {
535 NIR_PASS(progress
, nir
,
536 nir_opt_constant_folding
);
540 /* Nothing should rematerialize any flrps, so we only
541 * need to do this lowering once.
546 NIR_PASS(progress
, nir
, nir_opt_undef
);
547 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
549 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
552 nir_var_function_temp
);
554 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
557 /* Must be run at the end to prevent creation of fsin/fcos ops */
558 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
563 NIR_PASS(progress
, nir
, nir_opt_dce
);
564 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
565 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
566 NIR_PASS(progress
, nir
, nir_copy_prop
);
569 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
571 /* We implement booleans as 32-bit 0/~0 */
572 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
574 /* Now that booleans are lowered, we can run out late opts */
575 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
577 /* Lower mods for float ops only. Integer ops don't support modifiers
578 * (saturate doesn't make sense on integers, neg/abs require dedicated
581 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
582 NIR_PASS(progress
, nir
, nir_copy_prop
);
583 NIR_PASS(progress
, nir
, nir_opt_dce
);
585 /* Take us out of SSA */
586 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
587 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
589 /* We are a vector architecture; write combine where possible */
590 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
591 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
593 NIR_PASS(progress
, nir
, nir_opt_dce
);
596 /* Do not actually emit a load; instead, cache the constant for inlining */
599 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
601 nir_ssa_def def
= instr
->def
;
603 float *v
= rzalloc_array(NULL
, float, 4);
604 nir_const_value_to_array(v
, instr
->value
, instr
->def
.num_components
, f32
);
606 /* Shifted for SSA, +1 for off-by-one */
607 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
610 /* Normally constants are embedded implicitly, but for I/O and such we have to
611 * explicitly emit a move with the constant source */
614 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
616 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
618 if (constant_value
) {
619 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
620 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
621 emit_mir_instruction(ctx
, ins
);
626 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
628 unsigned comp
= src
->swizzle
[0];
630 for (unsigned c
= 1; c
< nr_components
; ++c
) {
631 if (src
->swizzle
[c
] != comp
)
638 #define ALU_CASE(nir, _op) \
640 op = midgard_alu_op_##_op; \
641 assert(src_bitsize == dst_bitsize); \
644 #define ALU_CASE_BCAST(nir, _op, count) \
646 op = midgard_alu_op_##_op; \
647 broadcast_swizzle = count; \
648 assert(src_bitsize == dst_bitsize); \
651 nir_is_fzero_constant(nir_src src
)
653 if (!nir_src_is_const(src
))
656 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
657 if (nir_src_comp_as_float(src
, c
) != 0.0)
664 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
665 * special treatment override this anyway. */
667 static midgard_reg_mode
668 reg_mode_for_nir(nir_alu_instr
*instr
)
670 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
672 switch (src_bitsize
) {
674 return midgard_reg_mode_8
;
676 return midgard_reg_mode_16
;
678 return midgard_reg_mode_32
;
680 return midgard_reg_mode_64
;
682 unreachable("Invalid bit size");
687 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
689 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
690 * is handled elsewhere */
692 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
693 midgard_emit_derivatives(ctx
, instr
);
697 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
699 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
700 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
701 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
703 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
704 * supported. A few do not and are commented for now. Also, there are a
705 * number of NIR ops which Midgard does not support and need to be
706 * lowered, also TODO. This switch block emits the opcode and calling
707 * convention of the Midgard instruction; actual packing is done in
712 /* Number of components valid to check for the instruction (the rest
713 * will be forced to the last), or 0 to use as-is. Relevant as
714 * ball-type instructions have a channel count in NIR but are all vec4
717 unsigned broadcast_swizzle
= 0;
719 /* What register mode should we operate in? */
720 midgard_reg_mode reg_mode
=
721 reg_mode_for_nir(instr
);
723 /* Do we need a destination override? Used for inline
726 midgard_dest_override dest_override
=
727 midgard_dest_override_none
;
729 /* Should we use a smaller respective source and sign-extend? */
731 bool half_1
= false, sext_1
= false;
732 bool half_2
= false, sext_2
= false;
734 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
735 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
738 ALU_CASE(fadd
, fadd
);
739 ALU_CASE(fmul
, fmul
);
740 ALU_CASE(fmin
, fmin
);
741 ALU_CASE(fmax
, fmax
);
742 ALU_CASE(imin
, imin
);
743 ALU_CASE(imax
, imax
);
744 ALU_CASE(umin
, umin
);
745 ALU_CASE(umax
, umax
);
746 ALU_CASE(ffloor
, ffloor
);
747 ALU_CASE(fround_even
, froundeven
);
748 ALU_CASE(ftrunc
, ftrunc
);
749 ALU_CASE(fceil
, fceil
);
750 ALU_CASE(fdot3
, fdot3
);
751 ALU_CASE(fdot4
, fdot4
);
752 ALU_CASE(iadd
, iadd
);
753 ALU_CASE(isub
, isub
);
754 ALU_CASE(imul
, imul
);
756 /* Zero shoved as second-arg */
757 ALU_CASE(iabs
, iabsdiff
);
761 ALU_CASE(feq32
, feq
);
762 ALU_CASE(fne32
, fne
);
763 ALU_CASE(flt32
, flt
);
764 ALU_CASE(ieq32
, ieq
);
765 ALU_CASE(ine32
, ine
);
766 ALU_CASE(ilt32
, ilt
);
767 ALU_CASE(ult32
, ult
);
769 /* We don't have a native b2f32 instruction. Instead, like many
770 * GPUs, we exploit booleans as 0/~0 for false/true, and
771 * correspondingly AND
772 * by 1.0 to do the type conversion. For the moment, prime us
775 * iand [whatever], #0
777 * At the end of emit_alu (as MIR), we'll fix-up the constant
780 ALU_CASE(b2f32
, iand
);
781 ALU_CASE(b2i32
, iand
);
783 /* Likewise, we don't have a dedicated f2b32 instruction, but
784 * we can do a "not equal to 0.0" test. */
786 ALU_CASE(f2b32
, fne
);
787 ALU_CASE(i2b32
, ine
);
789 ALU_CASE(frcp
, frcp
);
790 ALU_CASE(frsq
, frsqrt
);
791 ALU_CASE(fsqrt
, fsqrt
);
792 ALU_CASE(fexp2
, fexp2
);
793 ALU_CASE(flog2
, flog2
);
795 ALU_CASE(f2i32
, f2i_rtz
);
796 ALU_CASE(f2u32
, f2u_rtz
);
797 ALU_CASE(i2f32
, i2f_rtz
);
798 ALU_CASE(u2f32
, u2f_rtz
);
800 ALU_CASE(f2i16
, f2i_rtz
);
801 ALU_CASE(f2u16
, f2u_rtz
);
802 ALU_CASE(i2f16
, i2f_rtz
);
803 ALU_CASE(u2f16
, u2f_rtz
);
805 ALU_CASE(fsin
, fsin
);
806 ALU_CASE(fcos
, fcos
);
808 /* We'll set invert */
809 ALU_CASE(inot
, imov
);
810 ALU_CASE(iand
, iand
);
812 ALU_CASE(ixor
, ixor
);
813 ALU_CASE(ishl
, ishl
);
814 ALU_CASE(ishr
, iasr
);
815 ALU_CASE(ushr
, ilsr
);
817 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
818 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
819 ALU_CASE(b32all_fequal4
, fball_eq
);
821 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
822 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
823 ALU_CASE(b32any_fnequal4
, fbany_neq
);
825 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
826 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
827 ALU_CASE(b32all_iequal4
, iball_eq
);
829 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
830 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
831 ALU_CASE(b32any_inequal4
, ibany_neq
);
833 /* Source mods will be shoved in later */
834 ALU_CASE(fabs
, fmov
);
835 ALU_CASE(fneg
, fmov
);
836 ALU_CASE(fsat
, fmov
);
838 /* For size conversion, we use a move. Ideally though we would squash
839 * these ops together; maybe that has to happen after in NIR as part of
840 * propagation...? An earlier algebraic pass ensured we step down by
841 * only / exactly one size. If stepping down, we use a dest override to
842 * reduce the size; if stepping up, we use a larger-sized move with a
843 * half source and a sign/zero-extension modifier */
849 /* If we end up upscale, we'll need a sign-extend on the
850 * operand (the second argument) */
858 op
= midgard_alu_op_imov
;
860 if (dst_bitsize
== (src_bitsize
* 2)) {
864 /* Use a greater register mode */
866 } else if (src_bitsize
== (dst_bitsize
* 2)) {
867 /* Converting down */
868 dest_override
= midgard_dest_override_lower
;
875 assert(src_bitsize
== 32);
877 op
= midgard_alu_op_fmov
;
878 dest_override
= midgard_dest_override_lower
;
883 assert(src_bitsize
== 16);
885 op
= midgard_alu_op_fmov
;
892 /* For greater-or-equal, we lower to less-or-equal and flip the
900 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
901 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
902 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
903 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
906 /* Swap via temporary */
907 nir_alu_src temp
= instr
->src
[1];
908 instr
->src
[1] = instr
->src
[0];
909 instr
->src
[0] = temp
;
914 case nir_op_b32csel
: {
915 /* Midgard features both fcsel and icsel, depending on
916 * the type of the arguments/output. However, as long
917 * as we're careful we can _always_ use icsel and
918 * _never_ need fcsel, since the latter does additional
919 * floating-point-specific processing whereas the
920 * former just moves bits on the wire. It's not obvious
921 * why these are separate opcodes, save for the ability
922 * to do things like sat/pos/abs/neg for free */
924 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
925 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
927 /* The condition is the first argument; move the other
928 * arguments up one to be a binary instruction for
929 * Midgard with the condition last */
931 nir_alu_src temp
= instr
->src
[2];
933 instr
->src
[2] = instr
->src
[0];
934 instr
->src
[0] = instr
->src
[1];
935 instr
->src
[1] = temp
;
941 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
946 /* Midgard can perform certain modifiers on output of an ALU op */
949 if (midgard_is_integer_out_op(op
)) {
950 outmod
= midgard_outmod_int_wrap
;
952 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
953 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
956 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
958 if (instr
->op
== nir_op_fmax
) {
959 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
960 op
= midgard_alu_op_fmov
;
962 outmod
= midgard_outmod_pos
;
963 instr
->src
[0] = instr
->src
[1];
964 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
965 op
= midgard_alu_op_fmov
;
967 outmod
= midgard_outmod_pos
;
971 /* Fetch unit, quirks, etc information */
972 unsigned opcode_props
= alu_opcode_props
[op
].props
;
973 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
975 /* src0 will always exist afaik, but src1 will not for 1-argument
976 * instructions. The latter can only be fetched if the instruction
977 * needs it, or else we may segfault. */
979 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
980 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
981 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
982 assert(nr_inputs
<= 3);
984 /* Rather than use the instruction generation helpers, we do it
985 * ourselves here to avoid the mess */
987 midgard_instruction ins
= {
990 quirk_flipped_r24
? ~0 : src0
,
991 quirk_flipped_r24
? src0
: src1
,
997 nir_alu_src
*nirmods
[3] = { NULL
};
999 if (nr_inputs
>= 2) {
1000 nirmods
[0] = &instr
->src
[0];
1001 nirmods
[1] = &instr
->src
[1];
1002 } else if (nr_inputs
== 1) {
1003 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1009 nirmods
[2] = &instr
->src
[2];
1011 /* These were lowered to a move, so apply the corresponding mod */
1013 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1014 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1016 if (instr
->op
== nir_op_fneg
)
1017 s
->negate
= !s
->negate
;
1019 if (instr
->op
== nir_op_fabs
)
1023 bool is_int
= midgard_is_integer_op(op
);
1025 ins
.mask
= mask_of(nr_components
);
1027 midgard_vector_alu alu
= {
1029 .reg_mode
= reg_mode
,
1030 .dest_override
= dest_override
,
1033 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1034 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1037 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1040 ins
.mask
&= instr
->dest
.write_mask
;
1042 for (unsigned m
= 0; m
< 3; ++m
) {
1046 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
1047 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
1049 /* Replicate. TODO: remove when vec16 lands */
1050 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
1051 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
1054 if (nr_inputs
== 3) {
1055 /* Conditions can't have mods */
1056 assert(!nirmods
[2]->abs
);
1057 assert(!nirmods
[2]->negate
);
1062 /* Late fixup for emulated instructions */
1064 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1065 /* Presently, our second argument is an inline #0 constant.
1066 * Switch over to an embedded 1.0 constant (that can't fit
1067 * inline, since we're 32-bit, not 16-bit like the inline
1070 ins
.has_inline_constant
= false;
1071 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1072 ins
.has_constants
= true;
1074 if (instr
->op
== nir_op_b2f32
) {
1076 memcpy(&ins
.constants
, &f
, sizeof(float));
1078 ins
.constants
[0] = 1;
1082 for (unsigned c
= 0; c
< 16; ++c
)
1083 ins
.swizzle
[1][c
] = 0;
1084 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1085 /* Lots of instructions need a 0 plonked in */
1086 ins
.has_inline_constant
= false;
1087 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1088 ins
.has_constants
= true;
1089 ins
.constants
[0] = 0;
1091 for (unsigned c
= 0; c
< 16; ++c
)
1092 ins
.swizzle
[1][c
] = 0;
1093 } else if (instr
->op
== nir_op_inot
) {
1097 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1098 /* To avoid duplicating the lookup tables (probably), true LUT
1099 * instructions can only operate as if they were scalars. Lower
1100 * them here by changing the component. */
1102 unsigned orig_mask
= ins
.mask
;
1104 for (int i
= 0; i
< nr_components
; ++i
) {
1105 /* Mask the associated component, dropping the
1106 * instruction if needed */
1109 ins
.mask
&= orig_mask
;
1114 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1115 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1117 emit_mir_instruction(ctx
, ins
);
1120 emit_mir_instruction(ctx
, ins
);
1127 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1129 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1130 unsigned nir_mask
= 0;
1134 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1135 dsize
= nir_dest_bit_size(intr
->dest
);
1137 nir_mask
= nir_intrinsic_write_mask(intr
);
1141 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1142 unsigned bytemask
= mir_to_bytemask(mir_mode_for_destsize(dsize
), nir_mask
);
1143 mir_set_bytemask(ins
, bytemask
);
1146 ins
->load_64
= true;
1149 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1150 * optimized) versions of UBO #0 */
1152 midgard_instruction
*
1154 compiler_context
*ctx
,
1158 nir_src
*indirect_offset
,
1161 /* TODO: half-floats */
1163 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1164 ins
.constants
[0] = offset
;
1165 mir_set_intr_mask(instr
, &ins
, true);
1167 if (indirect_offset
) {
1168 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1169 ins
.load_store
.arg_2
= 0x80;
1171 ins
.load_store
.arg_2
= 0x1E;
1174 ins
.load_store
.arg_1
= index
;
1176 return emit_mir_instruction(ctx
, ins
);
1179 /* SSBO reads are like UBO reads if you squint */
1183 compiler_context
*ctx
,
1188 nir_src
*indirect_offset
,
1193 midgard_instruction ins
;
1196 ins
= m_ld_int4(srcdest
, offset
);
1198 ins
= m_st_int4(srcdest
, offset
);
1200 /* SSBO reads use a generic memory read interface, so we need the
1201 * address of the SSBO as the first argument. This is a sysval. */
1203 unsigned addr
= make_compiler_temp(ctx
);
1204 emit_sysval_read(ctx
, instr
, addr
, 2);
1206 /* The source array:
1208 * src[0] = store ? value : unused
1212 * We would like arg_1 = the address and
1213 * arg_2 = the offset.
1218 /* TODO: What is this? It looks superficially like a shift << 5, but
1219 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1220 * indirect offset. */
1222 if (indirect_offset
) {
1223 ins
.load_store
.arg_1
|= 0xE0;
1224 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1226 ins
.load_store
.arg_2
= 0x7E;
1229 /* TODO: Bounds check */
1231 /* Finally, we emit the direct offset */
1233 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1234 ins
.load_store
.address
= (offset
>> 9);
1235 mir_set_intr_mask(instr
, &ins
, is_read
);
1237 emit_mir_instruction(ctx
, ins
);
1242 compiler_context
*ctx
,
1243 unsigned dest
, unsigned offset
,
1244 unsigned nr_comp
, unsigned component
,
1245 nir_src
*indirect_offset
, nir_alu_type type
)
1247 /* XXX: Half-floats? */
1248 /* TODO: swizzle, mask */
1250 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1251 ins
.mask
= mask_of(nr_comp
);
1253 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1254 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1256 midgard_varying_parameter p
= {
1258 .interpolation
= midgard_interp_default
,
1259 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1263 memcpy(&u
, &p
, sizeof(p
));
1264 ins
.load_store
.varying_parameters
= u
;
1266 if (indirect_offset
)
1267 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1269 ins
.load_store
.arg_2
= 0x1E;
1271 ins
.load_store
.arg_1
= 0x9E;
1273 /* Use the type appropriate load */
1277 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1280 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1282 case nir_type_float
:
1283 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1286 unreachable("Attempted to load unknown type");
1290 emit_mir_instruction(ctx
, ins
);
1294 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1295 unsigned nr_components
)
1299 /* Figure out which uniform this is */
1300 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1301 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1303 if (dest_override
>= 0)
1304 dest
= dest_override
;
1306 /* Sysvals are prefix uniforms */
1307 unsigned uniform
= ((uintptr_t) val
) - 1;
1309 /* Emit the read itself -- this is never indirect */
1310 midgard_instruction
*ins
=
1311 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0);
1313 ins
->mask
= mask_of(nr_components
);
1317 compute_builtin_arg(nir_op op
)
1320 case nir_intrinsic_load_work_group_id
:
1322 case nir_intrinsic_load_local_invocation_id
:
1325 unreachable("Invalid compute paramater loaded");
1329 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1330 * Handle MRT here */
1333 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1335 emit_explicit_constant(ctx
, src
, src
);
1337 /* If we're doing MRT, we need to specify the render target */
1339 midgard_instruction rt_move
= {
1344 /* We'll write to r1.z */
1345 rt_move
= v_mov(~0, SSA_FIXED_REGISTER(1));
1346 rt_move
.mask
= 1 << COMPONENT_Z
;
1347 rt_move
.unit
= UNIT_SADD
;
1349 /* r1.z = (rt * 0x100) */
1350 rt_move
.has_inline_constant
= true;
1351 rt_move
.inline_constant
= (rt
* 0x100);
1354 ctx
->work_registers
= MAX2(ctx
->work_registers
, 1);
1357 emit_mir_instruction(ctx
, rt_move
);
1360 /* Next, generate the branch. For R render targets in the writeout, the
1361 * i'th render target jumps to pseudo-offset [2(R-1) + i] */
1363 unsigned outputs
= ctx
->is_blend
? 1 : ctx
->nir
->num_outputs
;
1364 unsigned offset
= (2 * (outputs
- 1)) + rt
;
1366 struct midgard_instruction ins
=
1367 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, offset
, midgard_condition_always
);
1369 /* Add dependencies */
1371 ins
.src
[1] = rt_move
.dest
;
1373 /* Emit the branch */
1374 emit_mir_instruction(ctx
, ins
);
1378 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1380 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1381 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1382 ins
.mask
= mask_of(3);
1383 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1384 emit_mir_instruction(ctx
, ins
);
1387 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1389 unsigned offset
= 0, reg
;
1391 switch (instr
->intrinsic
) {
1392 case nir_intrinsic_discard_if
:
1393 case nir_intrinsic_discard
: {
1394 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1395 struct midgard_instruction discard
= v_branch(conditional
, false);
1396 discard
.branch
.target_type
= TARGET_DISCARD
;
1399 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1401 emit_mir_instruction(ctx
, discard
);
1402 schedule_barrier(ctx
);
1407 case nir_intrinsic_load_uniform
:
1408 case nir_intrinsic_load_ubo
:
1409 case nir_intrinsic_load_ssbo
:
1410 case nir_intrinsic_load_input
: {
1411 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1412 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1413 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1415 /* Get the base type of the intrinsic */
1416 /* TODO: Infer type? Does it matter? */
1418 (is_ubo
|| is_ssbo
) ? nir_type_uint
: nir_intrinsic_type(instr
);
1419 t
= nir_alu_type_get_base_type(t
);
1421 if (!(is_ubo
|| is_ssbo
)) {
1422 offset
= nir_intrinsic_base(instr
);
1425 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1427 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1429 bool direct
= nir_src_is_const(*src_offset
);
1430 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1433 offset
+= nir_src_as_uint(*src_offset
);
1435 /* We may need to apply a fractional offset */
1436 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1437 nir_intrinsic_component(instr
) : 0;
1438 reg
= nir_dest_index(ctx
, &instr
->dest
);
1440 if (is_uniform
&& !ctx
->is_blend
) {
1441 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 0);
1442 } else if (is_ubo
) {
1443 nir_src index
= instr
->src
[0];
1445 /* We don't yet support indirect UBOs. For indirect
1446 * block numbers (if that's possible), we don't know
1447 * enough about the hardware yet. For indirect sources,
1448 * we know what we need but we need to add some NIR
1449 * support for lowering correctly with respect to
1452 assert(nir_src_is_const(index
));
1453 assert(nir_src_is_const(*src_offset
));
1455 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1456 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, NULL
, uindex
);
1457 } else if (is_ssbo
) {
1458 nir_src index
= instr
->src
[0];
1459 assert(nir_src_is_const(index
));
1460 uint32_t uindex
= nir_src_as_uint(index
);
1462 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1463 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1464 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1465 } else if (ctx
->is_blend
) {
1466 /* For blend shaders, load the input color, which is
1467 * preloaded to r0 */
1469 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1470 emit_mir_instruction(ctx
, move
);
1471 schedule_barrier(ctx
);
1472 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1473 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1474 ins
.load_store
.arg_1
= 0x1E;
1475 ins
.load_store
.arg_2
= 0x1E;
1476 ins
.mask
= mask_of(nr_comp
);
1478 /* Use the type appropriate load */
1482 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1485 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1487 case nir_type_float
:
1488 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1491 unreachable("Attempted to load unknown type");
1495 emit_mir_instruction(ctx
, ins
);
1497 DBG("Unknown load\n");
1504 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1506 case nir_intrinsic_load_raw_output_pan
:
1507 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1508 reg
= nir_dest_index(ctx
, &instr
->dest
);
1509 assert(ctx
->is_blend
);
1511 /* T720 and below use different blend opcodes with slightly
1512 * different semantics than T760 and up */
1514 midgard_instruction ld
= m_ld_color_buffer_8(reg
, 0);
1515 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1517 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1518 ld
.load_store
.op
= old_blend
?
1519 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1520 midgard_op_ld_color_buffer_u8_as_fp16
;
1523 ld
.load_store
.address
= 1;
1524 ld
.load_store
.arg_2
= 0x1E;
1527 for (unsigned c
= 2; c
< 16; ++c
)
1528 ld
.swizzle
[0][c
] = 0;
1531 emit_mir_instruction(ctx
, ld
);
1534 case nir_intrinsic_load_blend_const_color_rgba
: {
1535 assert(ctx
->is_blend
);
1536 reg
= nir_dest_index(ctx
, &instr
->dest
);
1538 /* Blend constants are embedded directly in the shader and
1539 * patched in, so we use some magic routing */
1541 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1542 ins
.has_constants
= true;
1543 ins
.has_blend_constant
= true;
1544 emit_mir_instruction(ctx
, ins
);
1548 case nir_intrinsic_store_output
:
1549 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1551 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1553 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1555 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1556 /* Determine number of render targets */
1557 emit_fragment_store(ctx
, reg
, offset
);
1558 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1559 /* We should have been vectorized, though we don't
1560 * currently check that st_vary is emitted only once
1561 * per slot (this is relevant, since there's not a mask
1562 * parameter available on the store [set to 0 by the
1563 * blob]). We do respect the component by adjusting the
1564 * swizzle. If this is a constant source, we'll need to
1565 * emit that explicitly. */
1567 emit_explicit_constant(ctx
, reg
, reg
);
1569 unsigned component
= nir_intrinsic_component(instr
);
1570 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1572 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1573 st
.load_store
.arg_1
= 0x9E;
1574 st
.load_store
.arg_2
= 0x1E;
1576 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
[0]); ++i
)
1577 st
.swizzle
[0][i
] = MIN2(i
+ component
, nr_comp
);
1579 emit_mir_instruction(ctx
, st
);
1581 DBG("Unknown store\n");
1587 /* Special case of store_output for lowered blend shaders */
1588 case nir_intrinsic_store_raw_output_pan
:
1589 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1590 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1591 emit_fragment_store(ctx
, reg
, 0);
1595 case nir_intrinsic_store_ssbo
:
1596 assert(nir_src_is_const(instr
->src
[1]));
1598 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1599 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1600 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1601 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1603 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1605 emit_explicit_constant(ctx
, reg
, reg
);
1606 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1609 case nir_intrinsic_load_viewport_scale
:
1610 case nir_intrinsic_load_viewport_offset
:
1611 case nir_intrinsic_load_num_work_groups
:
1612 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1613 emit_sysval_read(ctx
, &instr
->instr
, ~0, 3);
1616 case nir_intrinsic_load_work_group_id
:
1617 case nir_intrinsic_load_local_invocation_id
:
1618 emit_compute_builtin(ctx
, instr
);
1622 printf ("Unhandled intrinsic\n");
1629 midgard_tex_format(enum glsl_sampler_dim dim
)
1632 case GLSL_SAMPLER_DIM_1D
:
1633 case GLSL_SAMPLER_DIM_BUF
:
1636 case GLSL_SAMPLER_DIM_2D
:
1637 case GLSL_SAMPLER_DIM_EXTERNAL
:
1638 case GLSL_SAMPLER_DIM_RECT
:
1641 case GLSL_SAMPLER_DIM_3D
:
1644 case GLSL_SAMPLER_DIM_CUBE
:
1645 return MALI_TEX_CUBE
;
1648 DBG("Unknown sampler dim type\n");
1654 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1658 pan_attach_constant_bias(
1659 compiler_context
*ctx
,
1661 midgard_texture_word
*word
)
1663 /* To attach as constant, it has to *be* constant */
1665 if (!nir_src_is_const(lod
))
1668 float f
= nir_src_as_float(lod
);
1670 /* Break into fixed-point */
1672 float lod_frac
= f
- lod_int
;
1674 /* Carry over negative fractions */
1675 if (lod_frac
< 0.0) {
1681 word
->bias
= float_to_ubyte(lod_frac
);
1682 word
->bias_int
= lod_int
;
1687 static enum mali_sampler_type
1688 midgard_sampler_type(nir_alu_type t
) {
1689 switch (nir_alu_type_get_base_type(t
))
1691 case nir_type_float
:
1692 return MALI_SAMPLER_FLOAT
;
1694 return MALI_SAMPLER_SIGNED
;
1696 return MALI_SAMPLER_UNSIGNED
;
1698 unreachable("Unknown sampler type");
1703 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1704 unsigned midgard_texop
)
1707 //assert (!instr->sampler);
1708 //assert (!instr->texture_array_size);
1710 int texture_index
= instr
->texture_index
;
1711 int sampler_index
= texture_index
;
1713 /* No helper to build texture words -- we do it all here */
1714 midgard_instruction ins
= {
1715 .type
= TAG_TEXTURE_4
,
1717 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1718 .src
= { ~0, ~0, ~0 },
1719 .swizzle
= SWIZZLE_IDENTITY_4
,
1721 .op
= midgard_texop
,
1722 .format
= midgard_tex_format(instr
->sampler_dim
),
1723 .texture_handle
= texture_index
,
1724 .sampler_handle
= sampler_index
,
1730 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1734 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1735 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1736 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1738 switch (instr
->src
[i
].src_type
) {
1739 case nir_tex_src_coord
: {
1740 emit_explicit_constant(ctx
, index
, index
);
1742 /* Texelfetch coordinates uses all four elements
1743 * (xyz/index) regardless of texture dimensionality,
1744 * which means it's necessary to zero the unused
1745 * components to keep everything happy */
1747 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1748 unsigned old_index
= index
;
1750 index
= make_compiler_temp(ctx
);
1752 /* mov index, old_index */
1753 midgard_instruction mov
= v_mov(old_index
, index
);
1755 emit_mir_instruction(ctx
, mov
);
1757 /* mov index.zw, #0 */
1758 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), index
);
1759 mov
.has_constants
= true;
1760 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1761 emit_mir_instruction(ctx
, mov
);
1764 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1765 /* texelFetch is undefined on samplerCube */
1766 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1768 /* For cubemaps, we use a special ld/st op to
1769 * select the face and copy the xy into the
1770 * texture register */
1772 unsigned temp
= make_compiler_temp(ctx
);
1773 midgard_instruction ld
= m_ld_cubemap_coords(temp
, 0);
1775 ld
.mask
= 0x3; /* xy */
1776 ld
.load_store
.arg_1
= 0x20;
1777 ld
.swizzle
[1][3] = COMPONENT_X
;
1778 emit_mir_instruction(ctx
, ld
);
1782 ins
.swizzle
[1][2] = COMPONENT_X
;
1783 ins
.swizzle
[1][3] = COMPONENT_X
;
1788 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1789 /* Array component in w but NIR wants it in z */
1790 if (nr_components
== 3) {
1791 ins
.swizzle
[1][2] = COMPONENT_Z
;
1792 ins
.swizzle
[1][3] = COMPONENT_Z
;
1793 } else if (nr_components
== 2) {
1794 ins
.swizzle
[1][2] = COMPONENT_X
;
1795 ins
.swizzle
[1][3] = COMPONENT_X
;
1797 unreachable("Invalid texture 2D components");
1803 case nir_tex_src_bias
:
1804 case nir_tex_src_lod
: {
1805 /* Try as a constant if we can */
1807 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1808 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1811 ins
.texture
.lod_register
= true;
1813 emit_explicit_constant(ctx
, index
, index
);
1819 unreachable("Unknown texture source type\n");
1823 emit_mir_instruction(ctx
, ins
);
1825 /* Used for .cont and .last hinting */
1826 ctx
->texture_op_count
++;
1830 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1832 /* Fixup op, since only textureLod is permitted in VS on later Midgard
1833 * but NIR can give generic tex in some cases (which confuses the
1834 * hardware). Interestingly, early Midgard lines up with NIR */
1836 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1838 if (is_vertex
&& instr
->op
== nir_texop_tex
&& ctx
->quirks
& MIDGARD_EXPLICIT_LOD
)
1839 instr
->op
= nir_texop_txl
;
1841 switch (instr
->op
) {
1844 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1847 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1850 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1853 emit_sysval_read(ctx
, &instr
->instr
, ~0, 4);
1856 unreachable("Unhanlded texture op");
1861 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1863 switch (instr
->type
) {
1864 case nir_jump_break
: {
1865 /* Emit a branch out of the loop */
1866 struct midgard_instruction br
= v_branch(false, false);
1867 br
.branch
.target_type
= TARGET_BREAK
;
1868 br
.branch
.target_break
= ctx
->current_loop_depth
;
1869 emit_mir_instruction(ctx
, br
);
1874 DBG("Unknown jump type %d\n", instr
->type
);
1880 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1882 switch (instr
->type
) {
1883 case nir_instr_type_load_const
:
1884 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1887 case nir_instr_type_intrinsic
:
1888 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1891 case nir_instr_type_alu
:
1892 emit_alu(ctx
, nir_instr_as_alu(instr
));
1895 case nir_instr_type_tex
:
1896 emit_tex(ctx
, nir_instr_as_tex(instr
));
1899 case nir_instr_type_jump
:
1900 emit_jump(ctx
, nir_instr_as_jump(instr
));
1903 case nir_instr_type_ssa_undef
:
1908 DBG("Unhandled instruction type\n");
1914 /* ALU instructions can inline or embed constants, which decreases register
1915 * pressure and saves space. */
1917 #define CONDITIONAL_ATTACH(idx) { \
1918 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1921 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1922 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1927 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
1929 mir_foreach_instr_in_block(block
, alu
) {
1930 /* Other instructions cannot inline constants */
1931 if (alu
->type
!= TAG_ALU_4
) continue;
1932 if (alu
->compact_branch
) continue;
1934 /* If there is already a constant here, we can do nothing */
1935 if (alu
->has_constants
) continue;
1937 CONDITIONAL_ATTACH(0);
1939 if (!alu
->has_constants
) {
1940 CONDITIONAL_ATTACH(1)
1941 } else if (!alu
->inline_constant
) {
1942 /* Corner case: _two_ vec4 constants, for instance with a
1943 * csel. For this case, we can only use a constant
1944 * register for one, we'll have to emit a move for the
1945 * other. Note, if both arguments are constants, then
1946 * necessarily neither argument depends on the value of
1947 * any particular register. As the destination register
1948 * will be wiped, that means we can spill the constant
1949 * to the destination register.
1952 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
1953 unsigned scratch
= alu
->dest
;
1956 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
1957 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
1959 /* Set the source */
1960 alu
->src
[1] = scratch
;
1962 /* Inject us -before- the last instruction which set r31 */
1963 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
1969 /* Being a little silly with the names, but returns the op that is the bitwise
1970 * inverse of the op with the argument switched. I.e. (f and g are
1973 * f(a, b) = ~g(b, a)
1975 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
1977 * f(a, b) = ~g(b, a)
1978 * ~f(a, b) = g(b, a)
1979 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
1982 * Thus we define this function in pairs.
1985 static inline midgard_alu_op
1986 mir_contrapositive(midgard_alu_op op
)
1989 case midgard_alu_op_flt
:
1990 return midgard_alu_op_fle
;
1991 case midgard_alu_op_fle
:
1992 return midgard_alu_op_flt
;
1994 case midgard_alu_op_ilt
:
1995 return midgard_alu_op_ile
;
1996 case midgard_alu_op_ile
:
1997 return midgard_alu_op_ilt
;
2000 unreachable("No known contrapositive");
2004 /* Midgard supports two types of constants, embedded constants (128-bit) and
2005 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2006 * constants can be demoted to inline constants, for space savings and
2007 * sometimes a performance boost */
2010 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2012 mir_foreach_instr_in_block(block
, ins
) {
2013 if (!ins
->has_constants
) continue;
2014 if (ins
->has_inline_constant
) continue;
2016 /* Blend constants must not be inlined by definition */
2017 if (ins
->has_blend_constant
) continue;
2019 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2020 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2021 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2023 if (!(is_16
|| is_32
))
2026 /* src1 cannot be an inline constant due to encoding
2027 * restrictions. So, if possible we try to flip the arguments
2030 int op
= ins
->alu
.op
;
2032 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2033 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2036 /* Conditionals can be inverted */
2037 case midgard_alu_op_flt
:
2038 case midgard_alu_op_ilt
:
2039 case midgard_alu_op_fle
:
2040 case midgard_alu_op_ile
:
2041 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2046 case midgard_alu_op_fcsel
:
2047 case midgard_alu_op_icsel
:
2048 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2057 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2058 /* Extract the source information */
2060 midgard_vector_alu_src
*src
;
2061 int q
= ins
->alu
.src2
;
2062 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2065 /* Component is from the swizzle. Take a nonzero component */
2067 unsigned first_comp
= ffs(ins
->mask
) - 1;
2068 unsigned component
= ins
->swizzle
[1][first_comp
];
2070 /* Scale constant appropriately, if we can legally */
2071 uint16_t scaled_constant
= 0;
2073 if (midgard_is_integer_op(op
) || is_16
) {
2074 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2075 scaled_constant
= (uint16_t) iconstants
[component
];
2077 /* Constant overflow after resize */
2078 if (scaled_constant
!= iconstants
[component
])
2081 float *f
= (float *) ins
->constants
;
2082 float original
= f
[component
];
2083 scaled_constant
= _mesa_float_to_half(original
);
2085 /* Check for loss of precision. If this is
2086 * mediump, we don't care, but for a highp
2087 * shader, we need to pay attention. NIR
2088 * doesn't yet tell us which mode we're in!
2089 * Practically this prevents most constants
2090 * from being inlined, sadly. */
2092 float fp32
= _mesa_half_to_float(scaled_constant
);
2094 if (fp32
!= original
)
2098 /* We don't know how to handle these with a constant */
2100 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2101 DBG("Bailing inline constant...\n");
2105 /* Make sure that the constant is not itself a vector
2106 * by checking if all accessed values are the same. */
2108 uint32_t *cons
= ins
->constants
;
2109 uint32_t value
= cons
[component
];
2111 bool is_vector
= false;
2112 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2114 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2115 /* We only care if this component is actually used */
2116 if (!(mask
& (1 << c
)))
2119 uint32_t test
= cons
[ins
->swizzle
[1][c
]];
2121 if (test
!= value
) {
2130 /* Get rid of the embedded constant */
2131 ins
->has_constants
= false;
2133 ins
->has_inline_constant
= true;
2134 ins
->inline_constant
= scaled_constant
;
2139 /* Dead code elimination for branches at the end of a block - only one branch
2140 * per block is legal semantically */
2143 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2145 bool branched
= false;
2147 mir_foreach_instr_in_block_safe(block
, ins
) {
2148 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2151 mir_remove_instruction(ins
);
2157 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2158 * the move can be propagated away entirely */
2161 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2164 if (comp
== midgard_outmod_none
)
2167 if (*outmod
== midgard_outmod_none
) {
2172 /* TODO: Compose rules */
2177 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2179 bool progress
= false;
2181 mir_foreach_instr_in_block_safe(block
, ins
) {
2182 if (ins
->type
!= TAG_ALU_4
) continue;
2183 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2184 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2186 /* TODO: Registers? */
2187 unsigned src
= ins
->src
[1];
2188 if (src
& IS_REG
) continue;
2190 /* There might be a source modifier, too */
2191 if (mir_nontrivial_source2_mod(ins
)) continue;
2193 /* Backpropagate the modifier */
2194 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2195 if (v
->type
!= TAG_ALU_4
) continue;
2196 if (v
->dest
!= src
) continue;
2198 /* Can we even take a float outmod? */
2199 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2201 midgard_outmod_float temp
= v
->alu
.outmod
;
2202 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2204 /* Throw in the towel.. */
2205 if (!progress
) break;
2207 /* Otherwise, transfer the modifier */
2208 v
->alu
.outmod
= temp
;
2209 ins
->alu
.outmod
= midgard_outmod_none
;
2219 emit_fragment_epilogue(compiler_context
*ctx
)
2221 /* Just emit the last chunk with the branch */
2222 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, ~0, midgard_condition_always
);
2225 static midgard_block
*
2226 emit_block(compiler_context
*ctx
, nir_block
*block
)
2228 midgard_block
*this_block
= ctx
->after_block
;
2229 ctx
->after_block
= NULL
;
2232 this_block
= create_empty_block(ctx
);
2234 list_addtail(&this_block
->link
, &ctx
->blocks
);
2236 this_block
->is_scheduled
= false;
2239 /* Set up current block */
2240 list_inithead(&this_block
->instructions
);
2241 ctx
->current_block
= this_block
;
2243 nir_foreach_instr(instr
, block
) {
2244 emit_instr(ctx
, instr
);
2245 ++ctx
->instruction_count
;
2251 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2254 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2256 midgard_block
*before_block
= ctx
->current_block
;
2258 /* Speculatively emit the branch, but we can't fill it in until later */
2259 EMIT(branch
, true, true);
2260 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2261 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2263 /* Emit the two subblocks. */
2264 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2265 midgard_block
*end_then_block
= ctx
->current_block
;
2267 /* Emit a jump from the end of the then block to the end of the else */
2268 EMIT(branch
, false, false);
2269 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2271 /* Emit second block, and check if it's empty */
2273 int else_idx
= ctx
->block_count
;
2274 int count_in
= ctx
->instruction_count
;
2275 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2276 midgard_block
*end_else_block
= ctx
->current_block
;
2277 int after_else_idx
= ctx
->block_count
;
2279 /* Now that we have the subblocks emitted, fix up the branches */
2284 if (ctx
->instruction_count
== count_in
) {
2285 /* The else block is empty, so don't emit an exit jump */
2286 mir_remove_instruction(then_exit
);
2287 then_branch
->branch
.target_block
= after_else_idx
;
2289 then_branch
->branch
.target_block
= else_idx
;
2290 then_exit
->branch
.target_block
= after_else_idx
;
2293 /* Wire up the successors */
2295 ctx
->after_block
= create_empty_block(ctx
);
2297 midgard_block_add_successor(before_block
, then_block
);
2298 midgard_block_add_successor(before_block
, else_block
);
2300 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2301 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2305 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2307 /* Remember where we are */
2308 midgard_block
*start_block
= ctx
->current_block
;
2310 /* Allocate a loop number, growing the current inner loop depth */
2311 int loop_idx
= ++ctx
->current_loop_depth
;
2313 /* Get index from before the body so we can loop back later */
2314 int start_idx
= ctx
->block_count
;
2316 /* Emit the body itself */
2317 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2319 /* Branch back to loop back */
2320 struct midgard_instruction br_back
= v_branch(false, false);
2321 br_back
.branch
.target_block
= start_idx
;
2322 emit_mir_instruction(ctx
, br_back
);
2324 /* Mark down that branch in the graph. */
2325 midgard_block_add_successor(start_block
, loop_block
);
2326 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2328 /* Find the index of the block about to follow us (note: we don't add
2329 * one; blocks are 0-indexed so we get a fencepost problem) */
2330 int break_block_idx
= ctx
->block_count
;
2332 /* Fix up the break statements we emitted to point to the right place,
2333 * now that we can allocate a block number for them */
2334 ctx
->after_block
= create_empty_block(ctx
);
2336 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2337 mir_foreach_instr_in_block(block
, ins
) {
2338 if (ins
->type
!= TAG_ALU_4
) continue;
2339 if (!ins
->compact_branch
) continue;
2340 if (ins
->prepacked_branch
) continue;
2342 /* We found a branch -- check the type to see if we need to do anything */
2343 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2345 /* It's a break! Check if it's our break */
2346 if (ins
->branch
.target_break
!= loop_idx
) continue;
2348 /* Okay, cool, we're breaking out of this loop.
2349 * Rewrite from a break to a goto */
2351 ins
->branch
.target_type
= TARGET_GOTO
;
2352 ins
->branch
.target_block
= break_block_idx
;
2354 midgard_block_add_successor(block
, ctx
->after_block
);
2358 /* Now that we've finished emitting the loop, free up the depth again
2359 * so we play nice with recursion amid nested loops */
2360 --ctx
->current_loop_depth
;
2362 /* Dump loop stats */
2366 static midgard_block
*
2367 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2369 midgard_block
*start_block
= NULL
;
2371 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2372 switch (node
->type
) {
2373 case nir_cf_node_block
: {
2374 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2377 start_block
= block
;
2382 case nir_cf_node_if
:
2383 emit_if(ctx
, nir_cf_node_as_if(node
));
2386 case nir_cf_node_loop
:
2387 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2390 case nir_cf_node_function
:
2399 /* Due to lookahead, we need to report the first tag executed in the command
2400 * stream and in branch targets. An initial block might be empty, so iterate
2401 * until we find one that 'works' */
2404 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2406 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2408 unsigned first_tag
= 0;
2410 mir_foreach_block_from(ctx
, initial_block
, v
) {
2411 if (v
->quadword_count
) {
2412 midgard_bundle
*initial_bundle
=
2413 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2415 first_tag
= initial_bundle
->tag
;
2424 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
, unsigned gpu_id
)
2426 struct util_dynarray
*compiled
= &program
->compiled
;
2428 midgard_debug
= debug_get_option_midgard_debug();
2430 /* TODO: Bound against what? */
2431 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2434 ctx
->stage
= nir
->info
.stage
;
2435 ctx
->is_blend
= is_blend
;
2436 ctx
->alpha_ref
= program
->alpha_ref
;
2437 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2439 /* Start off with a safe cutoff, allowing usage of all 16 work
2440 * registers. Later, we'll promote uniform reads to uniform registers
2441 * if we determine it is beneficial to do so */
2442 ctx
->uniform_cutoff
= 8;
2444 /* Initialize at a global (not block) level hash tables */
2446 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2447 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2448 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2450 /* Record the varying mapping for the command stream's bookkeeping */
2452 struct exec_list
*varyings
=
2453 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2455 unsigned max_varying
= 0;
2456 nir_foreach_variable(var
, varyings
) {
2457 unsigned loc
= var
->data
.driver_location
;
2458 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2460 for (int c
= 0; c
< sz
; ++c
) {
2461 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2462 max_varying
= MAX2(max_varying
, loc
+ c
);
2466 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2467 * (so we don't accidentally duplicate the epilogue since mesa/st has
2468 * messed with our I/O quite a bit already) */
2470 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2472 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2473 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2474 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2477 NIR_PASS_V(nir
, nir_lower_var_copies
);
2478 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2479 NIR_PASS_V(nir
, nir_split_var_copies
);
2480 NIR_PASS_V(nir
, nir_lower_var_copies
);
2481 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2482 NIR_PASS_V(nir
, nir_lower_var_copies
);
2483 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2485 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2487 /* Optimisation passes */
2489 optimise_nir(nir
, ctx
->quirks
);
2491 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2492 nir_print_shader(nir
, stdout
);
2495 /* Assign sysvals and counts, now that we're sure
2496 * (post-optimisation) */
2498 midgard_nir_assign_sysvals(ctx
, nir
);
2500 program
->uniform_count
= nir
->num_uniforms
;
2501 program
->sysval_count
= ctx
->sysval_count
;
2502 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2504 nir_foreach_function(func
, nir
) {
2508 list_inithead(&ctx
->blocks
);
2509 ctx
->block_count
= 0;
2512 emit_cf_list(ctx
, &func
->impl
->body
);
2514 /* Emit empty exit block with successor */
2516 struct midgard_block
*semi_end
= ctx
->current_block
;
2518 struct midgard_block
*end
=
2519 emit_block(ctx
, func
->impl
->end_block
);
2521 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2522 emit_fragment_epilogue(ctx
);
2524 midgard_block_add_successor(semi_end
, end
);
2526 break; /* TODO: Multi-function shaders */
2529 util_dynarray_init(compiled
, NULL
);
2531 /* Per-block lowering before opts */
2533 mir_foreach_block(ctx
, block
) {
2534 inline_alu_constants(ctx
, block
);
2535 midgard_opt_promote_fmov(ctx
, block
);
2536 embedded_to_inline_constant(ctx
, block
);
2538 /* MIR-level optimizations */
2540 bool progress
= false;
2545 mir_foreach_block(ctx
, block
) {
2546 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2547 progress
|= midgard_opt_copy_prop(ctx
, block
);
2548 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2549 progress
|= midgard_opt_combine_projection(ctx
, block
);
2550 progress
|= midgard_opt_varying_projection(ctx
, block
);
2551 progress
|= midgard_opt_not_propagate(ctx
, block
);
2552 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2553 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2554 progress
|= midgard_opt_csel_invert(ctx
, block
);
2558 mir_foreach_block(ctx
, block
) {
2559 midgard_lower_invert(ctx
, block
);
2560 midgard_lower_derivatives(ctx
, block
);
2563 /* Nested control-flow can result in dead branches at the end of the
2564 * block. This messes with our analysis and is just dead code, so cull
2566 mir_foreach_block(ctx
, block
) {
2567 midgard_opt_cull_dead_branch(ctx
, block
);
2570 /* Ensure we were lowered */
2571 mir_foreach_instr_global(ctx
, ins
) {
2572 assert(!ins
->invert
);
2576 schedule_program(ctx
);
2578 /* Now that all the bundles are scheduled and we can calculate block
2579 * sizes, emit actual branch instructions rather than placeholders */
2581 int br_block_idx
= 0;
2583 mir_foreach_block(ctx
, block
) {
2584 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2585 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2586 midgard_instruction
*ins
= bundle
->instructions
[c
];
2588 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2590 if (ins
->prepacked_branch
) continue;
2592 /* Parse some basic branch info */
2593 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2594 bool is_conditional
= ins
->branch
.conditional
;
2595 bool is_inverted
= ins
->branch
.invert_conditional
;
2596 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2598 /* Determine the block we're jumping to */
2599 int target_number
= ins
->branch
.target_block
;
2601 /* Report the destination tag */
2602 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2604 /* Count up the number of quadwords we're
2605 * jumping over = number of quadwords until
2606 * (br_block_idx, target_number) */
2608 int quadword_offset
= 0;
2612 } else if (target_number
> br_block_idx
) {
2615 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2616 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2619 quadword_offset
+= blk
->quadword_count
;
2622 /* Jump backwards */
2624 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2625 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2628 quadword_offset
-= blk
->quadword_count
;
2632 /* Unconditional extended branches (far jumps)
2633 * have issues, so we always use a conditional
2634 * branch, setting the condition to always for
2635 * unconditional. For compact unconditional
2636 * branches, cond isn't used so it doesn't
2637 * matter what we pick. */
2639 midgard_condition cond
=
2640 !is_conditional
? midgard_condition_always
:
2641 is_inverted
? midgard_condition_false
:
2642 midgard_condition_true
;
2644 midgard_jmp_writeout_op op
=
2645 is_discard
? midgard_jmp_writeout_op_discard
:
2646 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2647 midgard_jmp_writeout_op_branch_cond
;
2650 midgard_branch_extended branch
=
2651 midgard_create_branch_extended(
2656 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2657 } else if (is_conditional
|| is_discard
) {
2658 midgard_branch_cond branch
= {
2660 .dest_tag
= dest_tag
,
2661 .offset
= quadword_offset
,
2665 assert(branch
.offset
== quadword_offset
);
2667 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2669 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2671 midgard_branch_uncond branch
= {
2673 .dest_tag
= dest_tag
,
2674 .offset
= quadword_offset
,
2678 assert(branch
.offset
== quadword_offset
);
2680 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2688 /* Emit flat binary from the instruction arrays. Iterate each block in
2689 * sequence. Save instruction boundaries such that lookahead tags can
2690 * be assigned easily */
2692 /* Cache _all_ bundles in source order for lookahead across failed branches */
2694 int bundle_count
= 0;
2695 mir_foreach_block(ctx
, block
) {
2696 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2698 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2700 mir_foreach_block(ctx
, block
) {
2701 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2702 source_order_bundles
[bundle_idx
++] = bundle
;
2706 int current_bundle
= 0;
2708 /* Midgard prefetches instruction types, so during emission we
2709 * need to lookahead. Unless this is the last instruction, in
2710 * which we return 1. Or if this is the second to last and the
2711 * last is an ALU, then it's also 1... */
2713 mir_foreach_block(ctx
, block
) {
2714 mir_foreach_bundle_in_block(block
, bundle
) {
2717 if (current_bundle
+ 1 < bundle_count
) {
2718 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2720 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2727 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2731 /* TODO: Free deeper */
2732 //util_dynarray_fini(&block->instructions);
2735 free(source_order_bundles
);
2737 /* Report the very first tag executed */
2738 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2740 /* Deal with off-by-one related to the fencepost problem */
2741 program
->work_register_count
= ctx
->work_registers
+ 1;
2742 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2744 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2745 program
->tls_size
= ctx
->tls_size
;
2747 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2748 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2750 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2751 unsigned nr_bundles
= 0, nr_ins
= 0;
2753 /* Count instructions and bundles */
2755 mir_foreach_block(ctx
, block
) {
2756 nr_bundles
+= util_dynarray_num_elements(
2757 &block
->bundles
, midgard_bundle
);
2759 mir_foreach_bundle_in_block(block
, bun
)
2760 nr_ins
+= bun
->instruction_count
;
2763 /* Calculate thread count. There are certain cutoffs by
2764 * register count for thread count */
2766 unsigned nr_registers
= program
->work_register_count
;
2768 unsigned nr_threads
=
2769 (nr_registers
<= 4) ? 4 :
2770 (nr_registers
<= 8) ? 2 :
2775 fprintf(stderr
, "shader%d - %s shader: "
2776 "%u inst, %u bundles, %u quadwords, "
2777 "%u registers, %u threads, %u loops, "
2778 "%u:%u spills:fills\n",
2780 gl_shader_stage_name(ctx
->stage
),
2781 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2782 nr_registers
, nr_threads
,
2784 ctx
->spills
, ctx
->fills
);