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ae03750b08e98b525801c09796cf886b32fa7636
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 if (broadcast_count && src) {
143 uint8_t last_component = src->swizzle[broadcast_count - 1];
144
145 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
146 src->swizzle[c] = last_component;
147 }
148 }
149
150 midgard_vector_alu_src alu_src = {
151 .rep_low = 0,
152 .rep_high = 0,
153 .half = half
154 };
155
156 if (is_int) {
157 alu_src.mod = midgard_int_normal;
158
159 /* Sign/zero-extend if needed */
160
161 if (half) {
162 alu_src.mod = sext ?
163 midgard_int_sign_extend
164 : midgard_int_zero_extend;
165 }
166
167 /* These should have been lowered away */
168 if (src)
169 assert(!(src->abs || src->negate));
170 } else {
171 if (src)
172 alu_src.mod = (src->abs << 0) | (src->negate << 1);
173 }
174
175 return alu_src;
176 }
177
178 M_LOAD(ld_attr_32, nir_type_uint32);
179 M_LOAD(ld_vary_32, nir_type_uint32);
180 M_LOAD(ld_ubo_int4, nir_type_uint32);
181 M_LOAD(ld_int4, nir_type_uint32);
182 M_STORE(st_int4, nir_type_uint32);
183 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
184 M_STORE(st_vary_32, nir_type_uint32);
185 M_LOAD(ld_cubemap_coords, nir_type_uint32);
186 M_LOAD(ld_compute_id, nir_type_uint32);
187
188 static midgard_instruction
189 v_branch(bool conditional, bool invert)
190 {
191 midgard_instruction ins = {
192 .type = TAG_ALU_4,
193 .unit = ALU_ENAB_BRANCH,
194 .compact_branch = true,
195 .branch = {
196 .conditional = conditional,
197 .invert_conditional = invert
198 },
199 .dest = ~0,
200 .src = { ~0, ~0, ~0, ~0 },
201 };
202
203 return ins;
204 }
205
206 static midgard_branch_extended
207 midgard_create_branch_extended( midgard_condition cond,
208 midgard_jmp_writeout_op op,
209 unsigned dest_tag,
210 signed quadword_offset)
211 {
212 /* The condition code is actually a LUT describing a function to
213 * combine multiple condition codes. However, we only support a single
214 * condition code at the moment, so we just duplicate over a bunch of
215 * times. */
216
217 uint16_t duplicated_cond =
218 (cond << 14) |
219 (cond << 12) |
220 (cond << 10) |
221 (cond << 8) |
222 (cond << 6) |
223 (cond << 4) |
224 (cond << 2) |
225 (cond << 0);
226
227 midgard_branch_extended branch = {
228 .op = op,
229 .dest_tag = dest_tag,
230 .offset = quadword_offset,
231 .cond = duplicated_cond
232 };
233
234 return branch;
235 }
236
237 static void
238 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
239 {
240 ins->has_constants = true;
241 memcpy(&ins->constants, constants, 16);
242 }
243
244 static int
245 glsl_type_size(const struct glsl_type *type, bool bindless)
246 {
247 return glsl_count_attribute_slots(type, false);
248 }
249
250 /* Lower fdot2 to a vector multiplication followed by channel addition */
251 static void
252 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
253 {
254 if (alu->op != nir_op_fdot2)
255 return;
256
257 b->cursor = nir_before_instr(&alu->instr);
258
259 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
260 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
261
262 nir_ssa_def *product = nir_fmul(b, src0, src1);
263
264 nir_ssa_def *sum = nir_fadd(b,
265 nir_channel(b, product, 0),
266 nir_channel(b, product, 1));
267
268 /* Replace the fdot2 with this sum */
269 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
270 }
271
272 static bool
273 midgard_nir_lower_fdot2(nir_shader *shader)
274 {
275 bool progress = false;
276
277 nir_foreach_function(function, shader) {
278 if (!function->impl) continue;
279
280 nir_builder _b;
281 nir_builder *b = &_b;
282 nir_builder_init(b, function->impl);
283
284 nir_foreach_block(block, function->impl) {
285 nir_foreach_instr_safe(instr, block) {
286 if (instr->type != nir_instr_type_alu) continue;
287
288 nir_alu_instr *alu = nir_instr_as_alu(instr);
289 midgard_nir_lower_fdot2_body(b, alu);
290
291 progress |= true;
292 }
293 }
294
295 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
296
297 }
298
299 return progress;
300 }
301
302 /* Midgard can't write depth and stencil separately. It has to happen in a
303 * single store operation containing both. Let's add a panfrost specific
304 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
305 * one.
306 */
307 static bool
308 midgard_nir_lower_zs_store(nir_shader *nir)
309 {
310 if (nir->info.stage != MESA_SHADER_FRAGMENT)
311 return false;
312
313 nir_variable *z_var = NULL, *s_var = NULL;
314
315 nir_foreach_variable(var, &nir->outputs) {
316 if (var->data.location == FRAG_RESULT_DEPTH)
317 z_var = var;
318 else if (var->data.location == FRAG_RESULT_STENCIL)
319 s_var = var;
320 }
321
322 if (!z_var && !s_var)
323 return false;
324
325 bool progress = false;
326
327 nir_foreach_function(function, nir) {
328 if (!function->impl) continue;
329
330 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
331
332 nir_foreach_block(block, function->impl) {
333 nir_foreach_instr_safe(instr, block) {
334 if (instr->type != nir_instr_type_intrinsic)
335 continue;
336
337 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
338 if (intr->intrinsic != nir_intrinsic_store_output)
339 continue;
340
341 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
342 assert(!z_store);
343 z_store = intr;
344 last_store = intr;
345 }
346
347 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
348 assert(!s_store);
349 s_store = intr;
350 last_store = intr;
351 }
352 }
353 }
354
355 if (!z_store && !s_store) continue;
356
357 nir_builder b;
358 nir_builder_init(&b, function->impl);
359
360 b.cursor = nir_before_instr(&last_store->instr);
361
362 nir_ssa_def *zs_store_src;
363
364 if (z_store && s_store) {
365 nir_ssa_def *srcs[2] = {
366 nir_ssa_for_src(&b, z_store->src[0], 1),
367 nir_ssa_for_src(&b, s_store->src[0], 1),
368 };
369
370 zs_store_src = nir_vec(&b, srcs, 2);
371 } else {
372 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
373 }
374
375 nir_intrinsic_instr *zs_store;
376
377 zs_store = nir_intrinsic_instr_create(b.shader,
378 nir_intrinsic_store_zs_output_pan);
379 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
380 zs_store->num_components = z_store && s_store ? 2 : 1;
381 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
382
383 /* Replace the Z and S store by a ZS store */
384 nir_builder_instr_insert(&b, &zs_store->instr);
385
386 if (z_store)
387 nir_instr_remove(&z_store->instr);
388
389 if (s_store)
390 nir_instr_remove(&s_store->instr);
391
392 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
393 progress = true;
394 }
395
396 return progress;
397 }
398
399 /* Flushes undefined values to zero */
400
401 static void
402 optimise_nir(nir_shader *nir, unsigned quirks)
403 {
404 bool progress;
405 unsigned lower_flrp =
406 (nir->options->lower_flrp16 ? 16 : 0) |
407 (nir->options->lower_flrp32 ? 32 : 0) |
408 (nir->options->lower_flrp64 ? 64 : 0);
409
410 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
411 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
412
413 nir_lower_tex_options lower_tex_options = {
414 .lower_txs_lod = true,
415 .lower_txp = ~0,
416 .lower_tex_without_implicit_lod =
417 (quirks & MIDGARD_EXPLICIT_LOD),
418
419 /* TODO: we have native gradient.. */
420 .lower_txd = true,
421 };
422
423 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
424
425 /* Must lower fdot2 after tex is lowered */
426 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
427
428 /* T720 is broken. */
429
430 if (quirks & MIDGARD_BROKEN_LOD)
431 NIR_PASS_V(nir, midgard_nir_lod_errata);
432
433 do {
434 progress = false;
435
436 NIR_PASS(progress, nir, nir_lower_var_copies);
437 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
438
439 NIR_PASS(progress, nir, nir_copy_prop);
440 NIR_PASS(progress, nir, nir_opt_remove_phis);
441 NIR_PASS(progress, nir, nir_opt_dce);
442 NIR_PASS(progress, nir, nir_opt_dead_cf);
443 NIR_PASS(progress, nir, nir_opt_cse);
444 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
445 NIR_PASS(progress, nir, nir_opt_algebraic);
446 NIR_PASS(progress, nir, nir_opt_constant_folding);
447
448 if (lower_flrp != 0) {
449 bool lower_flrp_progress = false;
450 NIR_PASS(lower_flrp_progress,
451 nir,
452 nir_lower_flrp,
453 lower_flrp,
454 false /* always_precise */,
455 nir->options->lower_ffma);
456 if (lower_flrp_progress) {
457 NIR_PASS(progress, nir,
458 nir_opt_constant_folding);
459 progress = true;
460 }
461
462 /* Nothing should rematerialize any flrps, so we only
463 * need to do this lowering once.
464 */
465 lower_flrp = 0;
466 }
467
468 NIR_PASS(progress, nir, nir_opt_undef);
469 NIR_PASS(progress, nir, nir_undef_to_zero);
470
471 NIR_PASS(progress, nir, nir_opt_loop_unroll,
472 nir_var_shader_in |
473 nir_var_shader_out |
474 nir_var_function_temp);
475
476 NIR_PASS(progress, nir, nir_opt_vectorize);
477 } while (progress);
478
479 /* Must be run at the end to prevent creation of fsin/fcos ops */
480 NIR_PASS(progress, nir, midgard_nir_scale_trig);
481
482 do {
483 progress = false;
484
485 NIR_PASS(progress, nir, nir_opt_dce);
486 NIR_PASS(progress, nir, nir_opt_algebraic);
487 NIR_PASS(progress, nir, nir_opt_constant_folding);
488 NIR_PASS(progress, nir, nir_copy_prop);
489 } while (progress);
490
491 NIR_PASS(progress, nir, nir_opt_algebraic_late);
492
493 /* We implement booleans as 32-bit 0/~0 */
494 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
495
496 /* Now that booleans are lowered, we can run out late opts */
497 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
498
499 /* Lower mods for float ops only. Integer ops don't support modifiers
500 * (saturate doesn't make sense on integers, neg/abs require dedicated
501 * instructions) */
502
503 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
504 NIR_PASS(progress, nir, nir_copy_prop);
505 NIR_PASS(progress, nir, nir_opt_dce);
506
507 /* Take us out of SSA */
508 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
509 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
510
511 /* We are a vector architecture; write combine where possible */
512 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
513 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
514
515 NIR_PASS(progress, nir, nir_opt_dce);
516 }
517
518 /* Do not actually emit a load; instead, cache the constant for inlining */
519
520 static void
521 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
522 {
523 nir_ssa_def def = instr->def;
524
525 midgard_constants *consts = rzalloc(NULL, midgard_constants);
526
527 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
528
529 #define RAW_CONST_COPY(bits) \
530 nir_const_value_to_array(consts->u##bits, instr->value, \
531 instr->def.num_components, u##bits)
532
533 switch (instr->def.bit_size) {
534 case 64:
535 RAW_CONST_COPY(64);
536 break;
537 case 32:
538 RAW_CONST_COPY(32);
539 break;
540 case 16:
541 RAW_CONST_COPY(16);
542 break;
543 case 8:
544 RAW_CONST_COPY(8);
545 break;
546 default:
547 unreachable("Invalid bit_size for load_const instruction\n");
548 }
549
550 /* Shifted for SSA, +1 for off-by-one */
551 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
552 }
553
554 /* Normally constants are embedded implicitly, but for I/O and such we have to
555 * explicitly emit a move with the constant source */
556
557 static void
558 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
559 {
560 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
561
562 if (constant_value) {
563 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
564 attach_constants(ctx, &ins, constant_value, node + 1);
565 emit_mir_instruction(ctx, ins);
566 }
567 }
568
569 static bool
570 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
571 {
572 unsigned comp = src->swizzle[0];
573
574 for (unsigned c = 1; c < nr_components; ++c) {
575 if (src->swizzle[c] != comp)
576 return true;
577 }
578
579 return false;
580 }
581
582 #define ALU_CASE(nir, _op) \
583 case nir_op_##nir: \
584 op = midgard_alu_op_##_op; \
585 assert(src_bitsize == dst_bitsize); \
586 break;
587
588 #define ALU_CASE_BCAST(nir, _op, count) \
589 case nir_op_##nir: \
590 op = midgard_alu_op_##_op; \
591 broadcast_swizzle = count; \
592 assert(src_bitsize == dst_bitsize); \
593 break;
594 static bool
595 nir_is_fzero_constant(nir_src src)
596 {
597 if (!nir_src_is_const(src))
598 return false;
599
600 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
601 if (nir_src_comp_as_float(src, c) != 0.0)
602 return false;
603 }
604
605 return true;
606 }
607
608 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
609 * special treatment override this anyway. */
610
611 static midgard_reg_mode
612 reg_mode_for_nir(nir_alu_instr *instr)
613 {
614 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
615
616 switch (src_bitsize) {
617 case 8:
618 return midgard_reg_mode_8;
619 case 16:
620 return midgard_reg_mode_16;
621 case 32:
622 return midgard_reg_mode_32;
623 case 64:
624 return midgard_reg_mode_64;
625 default:
626 unreachable("Invalid bit size");
627 }
628 }
629
630 static void
631 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to)
632 {
633 unsigned bits = nir_src_bit_size(instr->src[i].src);
634
635 ins->src[to] = nir_src_index(NULL, &instr->src[i].src);
636 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
637 }
638
639 static void
640 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
641 {
642 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
643 * is handled elsewhere */
644
645 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
646 midgard_emit_derivatives(ctx, instr);
647 return;
648 }
649
650 bool is_ssa = instr->dest.dest.is_ssa;
651
652 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
653 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
654 unsigned op = 0;
655
656 /* Number of components valid to check for the instruction (the rest
657 * will be forced to the last), or 0 to use as-is. Relevant as
658 * ball-type instructions have a channel count in NIR but are all vec4
659 * in Midgard */
660
661 unsigned broadcast_swizzle = 0;
662
663 /* What register mode should we operate in? */
664 midgard_reg_mode reg_mode =
665 reg_mode_for_nir(instr);
666
667 /* Do we need a destination override? Used for inline
668 * type conversion */
669
670 midgard_dest_override dest_override =
671 midgard_dest_override_none;
672
673 /* Should we use a smaller respective source and sign-extend? */
674
675 bool half_1 = false, sext_1 = false;
676 bool half_2 = false, sext_2 = false;
677
678 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
679 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
680
681 switch (instr->op) {
682 ALU_CASE(fadd, fadd);
683 ALU_CASE(fmul, fmul);
684 ALU_CASE(fmin, fmin);
685 ALU_CASE(fmax, fmax);
686 ALU_CASE(imin, imin);
687 ALU_CASE(imax, imax);
688 ALU_CASE(umin, umin);
689 ALU_CASE(umax, umax);
690 ALU_CASE(ffloor, ffloor);
691 ALU_CASE(fround_even, froundeven);
692 ALU_CASE(ftrunc, ftrunc);
693 ALU_CASE(fceil, fceil);
694 ALU_CASE(fdot3, fdot3);
695 ALU_CASE(fdot4, fdot4);
696 ALU_CASE(iadd, iadd);
697 ALU_CASE(isub, isub);
698 ALU_CASE(imul, imul);
699
700 /* Zero shoved as second-arg */
701 ALU_CASE(iabs, iabsdiff);
702
703 ALU_CASE(mov, imov);
704
705 ALU_CASE(feq32, feq);
706 ALU_CASE(fne32, fne);
707 ALU_CASE(flt32, flt);
708 ALU_CASE(ieq32, ieq);
709 ALU_CASE(ine32, ine);
710 ALU_CASE(ilt32, ilt);
711 ALU_CASE(ult32, ult);
712
713 /* We don't have a native b2f32 instruction. Instead, like many
714 * GPUs, we exploit booleans as 0/~0 for false/true, and
715 * correspondingly AND
716 * by 1.0 to do the type conversion. For the moment, prime us
717 * to emit:
718 *
719 * iand [whatever], #0
720 *
721 * At the end of emit_alu (as MIR), we'll fix-up the constant
722 */
723
724 ALU_CASE(b2f32, iand);
725 ALU_CASE(b2i32, iand);
726
727 /* Likewise, we don't have a dedicated f2b32 instruction, but
728 * we can do a "not equal to 0.0" test. */
729
730 ALU_CASE(f2b32, fne);
731 ALU_CASE(i2b32, ine);
732
733 ALU_CASE(frcp, frcp);
734 ALU_CASE(frsq, frsqrt);
735 ALU_CASE(fsqrt, fsqrt);
736 ALU_CASE(fexp2, fexp2);
737 ALU_CASE(flog2, flog2);
738
739 ALU_CASE(f2i64, f2i_rtz);
740 ALU_CASE(f2u64, f2u_rtz);
741 ALU_CASE(i2f64, i2f_rtz);
742 ALU_CASE(u2f64, u2f_rtz);
743
744 ALU_CASE(f2i32, f2i_rtz);
745 ALU_CASE(f2u32, f2u_rtz);
746 ALU_CASE(i2f32, i2f_rtz);
747 ALU_CASE(u2f32, u2f_rtz);
748
749 ALU_CASE(f2i16, f2i_rtz);
750 ALU_CASE(f2u16, f2u_rtz);
751 ALU_CASE(i2f16, i2f_rtz);
752 ALU_CASE(u2f16, u2f_rtz);
753
754 ALU_CASE(fsin, fsin);
755 ALU_CASE(fcos, fcos);
756
757 /* We'll set invert */
758 ALU_CASE(inot, imov);
759 ALU_CASE(iand, iand);
760 ALU_CASE(ior, ior);
761 ALU_CASE(ixor, ixor);
762 ALU_CASE(ishl, ishl);
763 ALU_CASE(ishr, iasr);
764 ALU_CASE(ushr, ilsr);
765
766 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
767 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
768 ALU_CASE(b32all_fequal4, fball_eq);
769
770 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
771 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
772 ALU_CASE(b32any_fnequal4, fbany_neq);
773
774 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
775 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
776 ALU_CASE(b32all_iequal4, iball_eq);
777
778 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
779 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
780 ALU_CASE(b32any_inequal4, ibany_neq);
781
782 /* Source mods will be shoved in later */
783 ALU_CASE(fabs, fmov);
784 ALU_CASE(fneg, fmov);
785 ALU_CASE(fsat, fmov);
786
787 /* For size conversion, we use a move. Ideally though we would squash
788 * these ops together; maybe that has to happen after in NIR as part of
789 * propagation...? An earlier algebraic pass ensured we step down by
790 * only / exactly one size. If stepping down, we use a dest override to
791 * reduce the size; if stepping up, we use a larger-sized move with a
792 * half source and a sign/zero-extension modifier */
793
794 case nir_op_i2i8:
795 case nir_op_i2i16:
796 case nir_op_i2i32:
797 case nir_op_i2i64:
798 /* If we end up upscale, we'll need a sign-extend on the
799 * operand (the second argument) */
800
801 sext_2 = true;
802 /* fallthrough */
803 case nir_op_u2u8:
804 case nir_op_u2u16:
805 case nir_op_u2u32:
806 case nir_op_u2u64:
807 case nir_op_f2f16:
808 case nir_op_f2f32:
809 case nir_op_f2f64: {
810 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
811 instr->op == nir_op_f2f64)
812 op = midgard_alu_op_fmov;
813 else
814 op = midgard_alu_op_imov;
815
816 if (dst_bitsize == (src_bitsize * 2)) {
817 /* Converting up */
818 half_2 = true;
819
820 /* Use a greater register mode */
821 reg_mode++;
822 } else if (src_bitsize == (dst_bitsize * 2)) {
823 /* Converting down */
824 dest_override = midgard_dest_override_lower;
825 }
826
827 break;
828 }
829
830 /* For greater-or-equal, we lower to less-or-equal and flip the
831 * arguments */
832
833 case nir_op_fge:
834 case nir_op_fge32:
835 case nir_op_ige32:
836 case nir_op_uge32: {
837 op =
838 instr->op == nir_op_fge ? midgard_alu_op_fle :
839 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
840 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
841 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
842 0;
843
844 /* Swap via temporary */
845 nir_alu_src temp = instr->src[1];
846 instr->src[1] = instr->src[0];
847 instr->src[0] = temp;
848
849 break;
850 }
851
852 case nir_op_b32csel: {
853 /* Midgard features both fcsel and icsel, depending on
854 * the type of the arguments/output. However, as long
855 * as we're careful we can _always_ use icsel and
856 * _never_ need fcsel, since the latter does additional
857 * floating-point-specific processing whereas the
858 * former just moves bits on the wire. It's not obvious
859 * why these are separate opcodes, save for the ability
860 * to do things like sat/pos/abs/neg for free */
861
862 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
863 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
864
865 /* The condition is the first argument; move the other
866 * arguments up one to be a binary instruction for
867 * Midgard with the condition last */
868
869 nir_alu_src temp = instr->src[2];
870
871 instr->src[2] = instr->src[0];
872 instr->src[0] = instr->src[1];
873 instr->src[1] = temp;
874
875 break;
876 }
877
878 default:
879 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
880 assert(0);
881 return;
882 }
883
884 /* Midgard can perform certain modifiers on output of an ALU op */
885 unsigned outmod;
886
887 if (midgard_is_integer_out_op(op)) {
888 outmod = midgard_outmod_int_wrap;
889 } else {
890 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
891 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
892 }
893
894 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
895
896 if (instr->op == nir_op_fmax) {
897 if (nir_is_fzero_constant(instr->src[0].src)) {
898 op = midgard_alu_op_fmov;
899 nr_inputs = 1;
900 outmod = midgard_outmod_pos;
901 instr->src[0] = instr->src[1];
902 } else if (nir_is_fzero_constant(instr->src[1].src)) {
903 op = midgard_alu_op_fmov;
904 nr_inputs = 1;
905 outmod = midgard_outmod_pos;
906 }
907 }
908
909 /* Fetch unit, quirks, etc information */
910 unsigned opcode_props = alu_opcode_props[op].props;
911 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
912
913 midgard_instruction ins = {
914 .type = TAG_ALU_4,
915 .dest = nir_dest_index(&instr->dest.dest),
916 .dest_type = nir_op_infos[instr->op].output_type
917 | nir_dest_bit_size(instr->dest.dest),
918 };
919
920 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
921 ins.src[i] = ~0;
922
923 if (quirk_flipped_r24) {
924 ins.src[0] = ~0;
925 mir_copy_src(&ins, instr, 0, 1);
926 } else {
927 for (unsigned i = 0; i < nr_inputs; ++i)
928 mir_copy_src(&ins, instr, i, quirk_flipped_r24 ? 1 : i);
929 }
930
931 nir_alu_src *nirmods[3] = { NULL };
932
933 if (nr_inputs >= 2) {
934 nirmods[0] = &instr->src[0];
935 nirmods[1] = &instr->src[1];
936 } else if (nr_inputs == 1) {
937 nirmods[quirk_flipped_r24] = &instr->src[0];
938 } else {
939 assert(0);
940 }
941
942 if (nr_inputs == 3)
943 nirmods[2] = &instr->src[2];
944
945 /* These were lowered to a move, so apply the corresponding mod */
946
947 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
948 nir_alu_src *s = nirmods[quirk_flipped_r24];
949
950 if (instr->op == nir_op_fneg)
951 s->negate = !s->negate;
952
953 if (instr->op == nir_op_fabs)
954 s->abs = !s->abs;
955 }
956
957 bool is_int = midgard_is_integer_op(op);
958
959 ins.mask = mask_of(nr_components);
960
961 midgard_vector_alu alu = {
962 .op = op,
963 .reg_mode = reg_mode,
964 .dest_override = dest_override,
965 .outmod = outmod,
966
967 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
968 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
969 };
970
971 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
972
973 if (!is_ssa)
974 ins.mask &= instr->dest.write_mask;
975
976 for (unsigned m = 0; m < 3; ++m) {
977 if (!nirmods[m])
978 continue;
979
980 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
981 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
982
983 /* Replicate. TODO: remove when vec16 lands */
984 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
985 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
986 }
987
988 if (nr_inputs == 3) {
989 /* Conditions can't have mods */
990 assert(!nirmods[2]->abs);
991 assert(!nirmods[2]->negate);
992 }
993
994 ins.alu = alu;
995
996 /* Late fixup for emulated instructions */
997
998 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
999 /* Presently, our second argument is an inline #0 constant.
1000 * Switch over to an embedded 1.0 constant (that can't fit
1001 * inline, since we're 32-bit, not 16-bit like the inline
1002 * constants) */
1003
1004 ins.has_inline_constant = false;
1005 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1006 ins.has_constants = true;
1007
1008 if (instr->op == nir_op_b2f32)
1009 ins.constants.f32[0] = 1.0f;
1010 else
1011 ins.constants.i32[0] = 1;
1012
1013 for (unsigned c = 0; c < 16; ++c)
1014 ins.swizzle[1][c] = 0;
1015 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1016 /* Lots of instructions need a 0 plonked in */
1017 ins.has_inline_constant = false;
1018 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1019 ins.has_constants = true;
1020 ins.constants.u32[0] = 0;
1021
1022 for (unsigned c = 0; c < 16; ++c)
1023 ins.swizzle[1][c] = 0;
1024 } else if (instr->op == nir_op_inot) {
1025 ins.invert = true;
1026 }
1027
1028 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1029 /* To avoid duplicating the lookup tables (probably), true LUT
1030 * instructions can only operate as if they were scalars. Lower
1031 * them here by changing the component. */
1032
1033 unsigned orig_mask = ins.mask;
1034
1035 for (int i = 0; i < nr_components; ++i) {
1036 /* Mask the associated component, dropping the
1037 * instruction if needed */
1038
1039 ins.mask = 1 << i;
1040 ins.mask &= orig_mask;
1041
1042 if (!ins.mask)
1043 continue;
1044
1045 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1046 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1047
1048 emit_mir_instruction(ctx, ins);
1049 }
1050 } else {
1051 emit_mir_instruction(ctx, ins);
1052 }
1053 }
1054
1055 #undef ALU_CASE
1056
1057 static void
1058 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1059 {
1060 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1061 unsigned nir_mask = 0;
1062 unsigned dsize = 0;
1063
1064 if (is_read) {
1065 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1066 dsize = nir_dest_bit_size(intr->dest);
1067 } else {
1068 nir_mask = nir_intrinsic_write_mask(intr);
1069 dsize = 32;
1070 }
1071
1072 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1073 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1074 mir_set_bytemask(ins, bytemask);
1075
1076 if (dsize == 64)
1077 ins->load_64 = true;
1078 }
1079
1080 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1081 * optimized) versions of UBO #0 */
1082
1083 static midgard_instruction *
1084 emit_ubo_read(
1085 compiler_context *ctx,
1086 nir_instr *instr,
1087 unsigned dest,
1088 unsigned offset,
1089 nir_src *indirect_offset,
1090 unsigned indirect_shift,
1091 unsigned index)
1092 {
1093 /* TODO: half-floats */
1094
1095 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1096 ins.constants.u32[0] = offset;
1097
1098 if (instr->type == nir_instr_type_intrinsic)
1099 mir_set_intr_mask(instr, &ins, true);
1100
1101 if (indirect_offset) {
1102 ins.src[2] = nir_src_index(ctx, indirect_offset);
1103 ins.load_store.arg_2 = (indirect_shift << 5);
1104 } else {
1105 ins.load_store.arg_2 = 0x1E;
1106 }
1107
1108 ins.load_store.arg_1 = index;
1109
1110 return emit_mir_instruction(ctx, ins);
1111 }
1112
1113 /* Globals are like UBOs if you squint. And shared memory is like globals if
1114 * you squint even harder */
1115
1116 static void
1117 emit_global(
1118 compiler_context *ctx,
1119 nir_instr *instr,
1120 bool is_read,
1121 unsigned srcdest,
1122 nir_src *offset,
1123 bool is_shared)
1124 {
1125 /* TODO: types */
1126
1127 midgard_instruction ins;
1128
1129 if (is_read)
1130 ins = m_ld_int4(srcdest, 0);
1131 else
1132 ins = m_st_int4(srcdest, 0);
1133
1134 mir_set_offset(ctx, &ins, offset, is_shared);
1135 mir_set_intr_mask(instr, &ins, is_read);
1136
1137 emit_mir_instruction(ctx, ins);
1138 }
1139
1140 static void
1141 emit_varying_read(
1142 compiler_context *ctx,
1143 unsigned dest, unsigned offset,
1144 unsigned nr_comp, unsigned component,
1145 nir_src *indirect_offset, nir_alu_type type, bool flat)
1146 {
1147 /* XXX: Half-floats? */
1148 /* TODO: swizzle, mask */
1149
1150 midgard_instruction ins = m_ld_vary_32(dest, offset);
1151 ins.mask = mask_of(nr_comp);
1152
1153 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1154 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1155
1156 midgard_varying_parameter p = {
1157 .is_varying = 1,
1158 .interpolation = midgard_interp_default,
1159 .flat = flat,
1160 };
1161
1162 unsigned u;
1163 memcpy(&u, &p, sizeof(p));
1164 ins.load_store.varying_parameters = u;
1165
1166 if (indirect_offset)
1167 ins.src[2] = nir_src_index(ctx, indirect_offset);
1168 else
1169 ins.load_store.arg_2 = 0x1E;
1170
1171 ins.load_store.arg_1 = 0x9E;
1172
1173 /* Use the type appropriate load */
1174 switch (type) {
1175 case nir_type_uint:
1176 case nir_type_bool:
1177 ins.load_store.op = midgard_op_ld_vary_32u;
1178 break;
1179 case nir_type_int:
1180 ins.load_store.op = midgard_op_ld_vary_32i;
1181 break;
1182 case nir_type_float:
1183 ins.load_store.op = midgard_op_ld_vary_32;
1184 break;
1185 default:
1186 unreachable("Attempted to load unknown type");
1187 break;
1188 }
1189
1190 emit_mir_instruction(ctx, ins);
1191 }
1192
1193 static void
1194 emit_attr_read(
1195 compiler_context *ctx,
1196 unsigned dest, unsigned offset,
1197 unsigned nr_comp, nir_alu_type t)
1198 {
1199 midgard_instruction ins = m_ld_attr_32(dest, offset);
1200 ins.load_store.arg_1 = 0x1E;
1201 ins.load_store.arg_2 = 0x1E;
1202 ins.mask = mask_of(nr_comp);
1203
1204 /* Use the type appropriate load */
1205 switch (t) {
1206 case nir_type_uint:
1207 case nir_type_bool:
1208 ins.load_store.op = midgard_op_ld_attr_32u;
1209 break;
1210 case nir_type_int:
1211 ins.load_store.op = midgard_op_ld_attr_32i;
1212 break;
1213 case nir_type_float:
1214 ins.load_store.op = midgard_op_ld_attr_32;
1215 break;
1216 default:
1217 unreachable("Attempted to load unknown type");
1218 break;
1219 }
1220
1221 emit_mir_instruction(ctx, ins);
1222 }
1223
1224 static void
1225 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1226 unsigned nr_components, unsigned offset)
1227 {
1228 nir_dest nir_dest;
1229
1230 /* Figure out which uniform this is */
1231 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1232 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1233
1234 unsigned dest = nir_dest_index(&nir_dest);
1235
1236 /* Sysvals are prefix uniforms */
1237 unsigned uniform = ((uintptr_t) val) - 1;
1238
1239 /* Emit the read itself -- this is never indirect */
1240 midgard_instruction *ins =
1241 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1242
1243 ins->mask = mask_of(nr_components);
1244 }
1245
1246 static unsigned
1247 compute_builtin_arg(nir_op op)
1248 {
1249 switch (op) {
1250 case nir_intrinsic_load_work_group_id:
1251 return 0x14;
1252 case nir_intrinsic_load_local_invocation_id:
1253 return 0x10;
1254 default:
1255 unreachable("Invalid compute paramater loaded");
1256 }
1257 }
1258
1259 static void
1260 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1261 {
1262 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1263
1264 midgard_instruction *br = ctx->writeout_branch[rt];
1265
1266 assert(!br);
1267
1268 emit_explicit_constant(ctx, src, src);
1269
1270 struct midgard_instruction ins =
1271 v_branch(false, false);
1272
1273 ins.writeout = true;
1274
1275 /* Add dependencies */
1276 ins.src[0] = src;
1277 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1278 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1279
1280 /* Emit the branch */
1281 br = emit_mir_instruction(ctx, ins);
1282 schedule_barrier(ctx);
1283 ctx->writeout_branch[rt] = br;
1284
1285 /* Push our current location = current block count - 1 = where we'll
1286 * jump to. Maybe a bit too clever for my own good */
1287
1288 br->branch.target_block = ctx->block_count - 1;
1289 }
1290
1291 static void
1292 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1293 {
1294 unsigned reg = nir_dest_index(&instr->dest);
1295 midgard_instruction ins = m_ld_compute_id(reg, 0);
1296 ins.mask = mask_of(3);
1297 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1298 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1299 emit_mir_instruction(ctx, ins);
1300 }
1301
1302 static unsigned
1303 vertex_builtin_arg(nir_op op)
1304 {
1305 switch (op) {
1306 case nir_intrinsic_load_vertex_id:
1307 return PAN_VERTEX_ID;
1308 case nir_intrinsic_load_instance_id:
1309 return PAN_INSTANCE_ID;
1310 default:
1311 unreachable("Invalid vertex builtin");
1312 }
1313 }
1314
1315 static void
1316 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1317 {
1318 unsigned reg = nir_dest_index(&instr->dest);
1319 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1320 }
1321
1322 static void
1323 emit_control_barrier(compiler_context *ctx)
1324 {
1325 midgard_instruction ins = {
1326 .type = TAG_TEXTURE_4,
1327 .src = { ~0, ~0, ~0, ~0 },
1328 .texture = {
1329 .op = TEXTURE_OP_BARRIER,
1330
1331 /* TODO: optimize */
1332 .barrier_buffer = 1,
1333 .barrier_shared = 1
1334 }
1335 };
1336
1337 emit_mir_instruction(ctx, ins);
1338 }
1339
1340 static const nir_variable *
1341 search_var(struct exec_list *vars, unsigned driver_loc)
1342 {
1343 nir_foreach_variable(var, vars) {
1344 if (var->data.driver_location == driver_loc)
1345 return var;
1346 }
1347
1348 return NULL;
1349 }
1350
1351 static void
1352 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1353 {
1354 unsigned offset = 0, reg;
1355
1356 switch (instr->intrinsic) {
1357 case nir_intrinsic_discard_if:
1358 case nir_intrinsic_discard: {
1359 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1360 struct midgard_instruction discard = v_branch(conditional, false);
1361 discard.branch.target_type = TARGET_DISCARD;
1362
1363 if (conditional)
1364 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1365
1366 emit_mir_instruction(ctx, discard);
1367 schedule_barrier(ctx);
1368
1369 break;
1370 }
1371
1372 case nir_intrinsic_load_uniform:
1373 case nir_intrinsic_load_ubo:
1374 case nir_intrinsic_load_global:
1375 case nir_intrinsic_load_shared:
1376 case nir_intrinsic_load_input:
1377 case nir_intrinsic_load_interpolated_input: {
1378 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1379 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1380 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1381 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1382 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1383 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1384
1385 /* Get the base type of the intrinsic */
1386 /* TODO: Infer type? Does it matter? */
1387 nir_alu_type t =
1388 (is_ubo || is_global || is_shared) ? nir_type_uint :
1389 (is_interp) ? nir_type_float :
1390 nir_intrinsic_type(instr);
1391
1392 t = nir_alu_type_get_base_type(t);
1393
1394 if (!(is_ubo || is_global)) {
1395 offset = nir_intrinsic_base(instr);
1396 }
1397
1398 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1399
1400 nir_src *src_offset = nir_get_io_offset_src(instr);
1401
1402 bool direct = nir_src_is_const(*src_offset);
1403 nir_src *indirect_offset = direct ? NULL : src_offset;
1404
1405 if (direct)
1406 offset += nir_src_as_uint(*src_offset);
1407
1408 /* We may need to apply a fractional offset */
1409 int component = (is_flat || is_interp) ?
1410 nir_intrinsic_component(instr) : 0;
1411 reg = nir_dest_index(&instr->dest);
1412
1413 if (is_uniform && !ctx->is_blend) {
1414 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1415 } else if (is_ubo) {
1416 nir_src index = instr->src[0];
1417
1418 /* TODO: Is indirect block number possible? */
1419 assert(nir_src_is_const(index));
1420
1421 uint32_t uindex = nir_src_as_uint(index) + 1;
1422 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1423 } else if (is_global || is_shared) {
1424 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1425 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1426 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1427 } else if (ctx->is_blend) {
1428 /* For blend shaders, load the input color, which is
1429 * preloaded to r0 */
1430
1431 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1432 emit_mir_instruction(ctx, move);
1433 schedule_barrier(ctx);
1434 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1435 emit_attr_read(ctx, reg, offset, nr_comp, t);
1436 } else {
1437 DBG("Unknown load\n");
1438 assert(0);
1439 }
1440
1441 break;
1442 }
1443
1444 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1445 case nir_intrinsic_load_barycentric_pixel:
1446 case nir_intrinsic_load_barycentric_centroid:
1447 break;
1448
1449 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1450
1451 case nir_intrinsic_load_raw_output_pan:
1452 case nir_intrinsic_load_output_u8_as_fp16_pan:
1453 reg = nir_dest_index(&instr->dest);
1454 assert(ctx->is_blend);
1455
1456 /* T720 and below use different blend opcodes with slightly
1457 * different semantics than T760 and up */
1458
1459 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1460 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1461
1462 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1463 ld.load_store.op = old_blend ?
1464 midgard_op_ld_color_buffer_u8_as_fp16_old :
1465 midgard_op_ld_color_buffer_u8_as_fp16;
1466
1467 if (old_blend) {
1468 ld.load_store.address = 1;
1469 ld.load_store.arg_2 = 0x1E;
1470 }
1471
1472 for (unsigned c = 2; c < 16; ++c)
1473 ld.swizzle[0][c] = 0;
1474 }
1475
1476 emit_mir_instruction(ctx, ld);
1477 break;
1478
1479 case nir_intrinsic_load_blend_const_color_rgba: {
1480 assert(ctx->is_blend);
1481 reg = nir_dest_index(&instr->dest);
1482
1483 /* Blend constants are embedded directly in the shader and
1484 * patched in, so we use some magic routing */
1485
1486 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1487 ins.has_constants = true;
1488 ins.has_blend_constant = true;
1489 emit_mir_instruction(ctx, ins);
1490 break;
1491 }
1492
1493 case nir_intrinsic_store_zs_output_pan: {
1494 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1495 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1496 MIDGARD_ZS_RT);
1497
1498 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1499
1500 if (!nir_intrinsic_component(instr))
1501 br->writeout_depth = true;
1502 if (nir_intrinsic_component(instr) ||
1503 instr->num_components)
1504 br->writeout_stencil = true;
1505 assert(br->writeout_depth | br->writeout_stencil);
1506 break;
1507 }
1508
1509 case nir_intrinsic_store_output:
1510 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1511
1512 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1513
1514 reg = nir_src_index(ctx, &instr->src[0]);
1515
1516 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1517 const nir_variable *var;
1518 enum midgard_rt_id rt;
1519
1520 var = search_var(&ctx->nir->outputs,
1521 nir_intrinsic_base(instr));
1522 assert(var);
1523 if (var->data.location == FRAG_RESULT_COLOR)
1524 rt = MIDGARD_COLOR_RT0;
1525 else if (var->data.location >= FRAG_RESULT_DATA0)
1526 rt = MIDGARD_COLOR_RT0 + var->data.location -
1527 FRAG_RESULT_DATA0;
1528 else
1529 assert(0);
1530
1531 emit_fragment_store(ctx, reg, rt);
1532 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1533 /* We should have been vectorized, though we don't
1534 * currently check that st_vary is emitted only once
1535 * per slot (this is relevant, since there's not a mask
1536 * parameter available on the store [set to 0 by the
1537 * blob]). We do respect the component by adjusting the
1538 * swizzle. If this is a constant source, we'll need to
1539 * emit that explicitly. */
1540
1541 emit_explicit_constant(ctx, reg, reg);
1542
1543 unsigned dst_component = nir_intrinsic_component(instr);
1544 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1545
1546 midgard_instruction st = m_st_vary_32(reg, offset);
1547 st.load_store.arg_1 = 0x9E;
1548 st.load_store.arg_2 = 0x1E;
1549
1550 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1551 case nir_type_uint:
1552 case nir_type_bool:
1553 st.load_store.op = midgard_op_st_vary_32u;
1554 break;
1555 case nir_type_int:
1556 st.load_store.op = midgard_op_st_vary_32i;
1557 break;
1558 case nir_type_float:
1559 st.load_store.op = midgard_op_st_vary_32;
1560 break;
1561 default:
1562 unreachable("Attempted to store unknown type");
1563 break;
1564 }
1565
1566 /* nir_intrinsic_component(store_intr) encodes the
1567 * destination component start. Source component offset
1568 * adjustment is taken care of in
1569 * install_registers_instr(), when offset_swizzle() is
1570 * called.
1571 */
1572 unsigned src_component = COMPONENT_X;
1573
1574 assert(nr_comp > 0);
1575 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1576 st.swizzle[0][i] = src_component;
1577 if (i >= dst_component && i < dst_component + nr_comp - 1)
1578 src_component++;
1579 }
1580
1581 emit_mir_instruction(ctx, st);
1582 } else {
1583 DBG("Unknown store\n");
1584 assert(0);
1585 }
1586
1587 break;
1588
1589 /* Special case of store_output for lowered blend shaders */
1590 case nir_intrinsic_store_raw_output_pan:
1591 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1592 reg = nir_src_index(ctx, &instr->src[0]);
1593
1594 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1595 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1596 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1597 * of:
1598 *
1599 * imov r0.xyzw, r0.xxxx
1600 */
1601
1602 unsigned expanded = make_compiler_temp(ctx);
1603
1604 midgard_instruction splatter = v_mov(reg, expanded);
1605
1606 for (unsigned c = 0; c < 16; ++c)
1607 splatter.swizzle[1][c] = 0;
1608
1609 emit_mir_instruction(ctx, splatter);
1610 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1611 } else
1612 emit_fragment_store(ctx, reg, ctx->blend_rt);
1613
1614 break;
1615
1616 case nir_intrinsic_store_global:
1617 case nir_intrinsic_store_shared:
1618 reg = nir_src_index(ctx, &instr->src[0]);
1619 emit_explicit_constant(ctx, reg, reg);
1620
1621 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1622 break;
1623
1624 case nir_intrinsic_load_ssbo_address:
1625 emit_sysval_read(ctx, &instr->instr, 1, 0);
1626 break;
1627
1628 case nir_intrinsic_get_buffer_size:
1629 emit_sysval_read(ctx, &instr->instr, 1, 8);
1630 break;
1631
1632 case nir_intrinsic_load_viewport_scale:
1633 case nir_intrinsic_load_viewport_offset:
1634 case nir_intrinsic_load_num_work_groups:
1635 case nir_intrinsic_load_sampler_lod_parameters_pan:
1636 emit_sysval_read(ctx, &instr->instr, 3, 0);
1637 break;
1638
1639 case nir_intrinsic_load_work_group_id:
1640 case nir_intrinsic_load_local_invocation_id:
1641 emit_compute_builtin(ctx, instr);
1642 break;
1643
1644 case nir_intrinsic_load_vertex_id:
1645 case nir_intrinsic_load_instance_id:
1646 emit_vertex_builtin(ctx, instr);
1647 break;
1648
1649 case nir_intrinsic_memory_barrier_buffer:
1650 case nir_intrinsic_memory_barrier_shared:
1651 break;
1652
1653 case nir_intrinsic_control_barrier:
1654 schedule_barrier(ctx);
1655 emit_control_barrier(ctx);
1656 schedule_barrier(ctx);
1657 break;
1658
1659 default:
1660 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1661 assert(0);
1662 break;
1663 }
1664 }
1665
1666 static unsigned
1667 midgard_tex_format(enum glsl_sampler_dim dim)
1668 {
1669 switch (dim) {
1670 case GLSL_SAMPLER_DIM_1D:
1671 case GLSL_SAMPLER_DIM_BUF:
1672 return MALI_TEX_1D;
1673
1674 case GLSL_SAMPLER_DIM_2D:
1675 case GLSL_SAMPLER_DIM_EXTERNAL:
1676 case GLSL_SAMPLER_DIM_RECT:
1677 return MALI_TEX_2D;
1678
1679 case GLSL_SAMPLER_DIM_3D:
1680 return MALI_TEX_3D;
1681
1682 case GLSL_SAMPLER_DIM_CUBE:
1683 return MALI_TEX_CUBE;
1684
1685 default:
1686 DBG("Unknown sampler dim type\n");
1687 assert(0);
1688 return 0;
1689 }
1690 }
1691
1692 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1693 * was successful */
1694
1695 static bool
1696 pan_attach_constant_bias(
1697 compiler_context *ctx,
1698 nir_src lod,
1699 midgard_texture_word *word)
1700 {
1701 /* To attach as constant, it has to *be* constant */
1702
1703 if (!nir_src_is_const(lod))
1704 return false;
1705
1706 float f = nir_src_as_float(lod);
1707
1708 /* Break into fixed-point */
1709 signed lod_int = f;
1710 float lod_frac = f - lod_int;
1711
1712 /* Carry over negative fractions */
1713 if (lod_frac < 0.0) {
1714 lod_int--;
1715 lod_frac += 1.0;
1716 }
1717
1718 /* Encode */
1719 word->bias = float_to_ubyte(lod_frac);
1720 word->bias_int = lod_int;
1721
1722 return true;
1723 }
1724
1725 static void
1726 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1727 unsigned midgard_texop)
1728 {
1729 /* TODO */
1730 //assert (!instr->sampler);
1731
1732 int texture_index = instr->texture_index;
1733 int sampler_index = texture_index;
1734
1735 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1736 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1737
1738 midgard_instruction ins = {
1739 .type = TAG_TEXTURE_4,
1740 .mask = 0xF,
1741 .dest = nir_dest_index(&instr->dest),
1742 .src = { ~0, ~0, ~0, ~0 },
1743 .dest_type = dest_type,
1744 .swizzle = SWIZZLE_IDENTITY_4,
1745 .texture = {
1746 .op = midgard_texop,
1747 .format = midgard_tex_format(instr->sampler_dim),
1748 .texture_handle = texture_index,
1749 .sampler_handle = sampler_index,
1750 .shadow = instr->is_shadow,
1751 }
1752 };
1753
1754 /* We may need a temporary for the coordinate */
1755
1756 bool needs_temp_coord =
1757 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1758 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1759 (instr->is_shadow);
1760
1761 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1762
1763 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1764 int index = nir_src_index(ctx, &instr->src[i].src);
1765 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1766 unsigned sz = nir_src_bit_size(instr->src[i].src);
1767 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1768
1769 switch (instr->src[i].src_type) {
1770 case nir_tex_src_coord: {
1771 emit_explicit_constant(ctx, index, index);
1772
1773 unsigned coord_mask = mask_of(instr->coord_components);
1774
1775 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1776
1777 if (flip_zw)
1778 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1779
1780 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1781 /* texelFetch is undefined on samplerCube */
1782 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1783
1784 /* For cubemaps, we use a special ld/st op to
1785 * select the face and copy the xy into the
1786 * texture register */
1787
1788 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1789 ld.src[1] = index;
1790 ld.src_types[1] = T;
1791 ld.mask = 0x3; /* xy */
1792 ld.load_store.arg_1 = 0x20;
1793 ld.swizzle[1][3] = COMPONENT_X;
1794 emit_mir_instruction(ctx, ld);
1795
1796 /* xyzw -> xyxx */
1797 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1798 ins.swizzle[1][3] = COMPONENT_X;
1799 } else if (needs_temp_coord) {
1800 /* mov coord_temp, coords */
1801 midgard_instruction mov = v_mov(index, coords);
1802 mov.mask = coord_mask;
1803
1804 if (flip_zw)
1805 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1806
1807 emit_mir_instruction(ctx, mov);
1808 } else {
1809 coords = index;
1810 }
1811
1812 ins.src[1] = coords;
1813 ins.src_types[1] = T;
1814
1815 /* Texelfetch coordinates uses all four elements
1816 * (xyz/index) regardless of texture dimensionality,
1817 * which means it's necessary to zero the unused
1818 * components to keep everything happy */
1819
1820 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1821 /* mov index.zw, #0, or generalized */
1822 midgard_instruction mov =
1823 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1824 mov.has_constants = true;
1825 mov.mask = coord_mask ^ 0xF;
1826 emit_mir_instruction(ctx, mov);
1827 }
1828
1829 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1830 /* Array component in w but NIR wants it in z,
1831 * but if we have a temp coord we already fixed
1832 * that up */
1833
1834 if (nr_components == 3) {
1835 ins.swizzle[1][2] = COMPONENT_Z;
1836 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1837 } else if (nr_components == 2) {
1838 ins.swizzle[1][2] =
1839 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1840 ins.swizzle[1][3] = COMPONENT_X;
1841 } else
1842 unreachable("Invalid texture 2D components");
1843 }
1844
1845 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1846 /* We zeroed */
1847 ins.swizzle[1][2] = COMPONENT_Z;
1848 ins.swizzle[1][3] = COMPONENT_W;
1849 }
1850
1851 break;
1852 }
1853
1854 case nir_tex_src_bias:
1855 case nir_tex_src_lod: {
1856 /* Try as a constant if we can */
1857
1858 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1859 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1860 break;
1861
1862 ins.texture.lod_register = true;
1863 ins.src[2] = index;
1864 ins.src_types[2] = T;
1865
1866 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1867 ins.swizzle[2][c] = COMPONENT_X;
1868
1869 emit_explicit_constant(ctx, index, index);
1870
1871 break;
1872 };
1873
1874 case nir_tex_src_offset: {
1875 ins.texture.offset_register = true;
1876 ins.src[3] = index;
1877 ins.src_types[3] = T;
1878
1879 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1880 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1881
1882 emit_explicit_constant(ctx, index, index);
1883 break;
1884 };
1885
1886 case nir_tex_src_comparator: {
1887 unsigned comp = COMPONENT_Z;
1888
1889 /* mov coord_temp.foo, coords */
1890 midgard_instruction mov = v_mov(index, coords);
1891 mov.mask = 1 << comp;
1892
1893 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1894 mov.swizzle[1][i] = COMPONENT_X;
1895
1896 emit_mir_instruction(ctx, mov);
1897 break;
1898 }
1899
1900 default: {
1901 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1902 assert(0);
1903 }
1904 }
1905 }
1906
1907 emit_mir_instruction(ctx, ins);
1908
1909 /* Used for .cont and .last hinting */
1910 ctx->texture_op_count++;
1911 }
1912
1913 static void
1914 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1915 {
1916 switch (instr->op) {
1917 case nir_texop_tex:
1918 case nir_texop_txb:
1919 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1920 break;
1921 case nir_texop_txl:
1922 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1923 break;
1924 case nir_texop_txf:
1925 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1926 break;
1927 case nir_texop_txs:
1928 emit_sysval_read(ctx, &instr->instr, 4, 0);
1929 break;
1930 default: {
1931 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1932 assert(0);
1933 }
1934 }
1935 }
1936
1937 static void
1938 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1939 {
1940 switch (instr->type) {
1941 case nir_jump_break: {
1942 /* Emit a branch out of the loop */
1943 struct midgard_instruction br = v_branch(false, false);
1944 br.branch.target_type = TARGET_BREAK;
1945 br.branch.target_break = ctx->current_loop_depth;
1946 emit_mir_instruction(ctx, br);
1947 break;
1948 }
1949
1950 default:
1951 DBG("Unknown jump type %d\n", instr->type);
1952 break;
1953 }
1954 }
1955
1956 static void
1957 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1958 {
1959 switch (instr->type) {
1960 case nir_instr_type_load_const:
1961 emit_load_const(ctx, nir_instr_as_load_const(instr));
1962 break;
1963
1964 case nir_instr_type_intrinsic:
1965 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1966 break;
1967
1968 case nir_instr_type_alu:
1969 emit_alu(ctx, nir_instr_as_alu(instr));
1970 break;
1971
1972 case nir_instr_type_tex:
1973 emit_tex(ctx, nir_instr_as_tex(instr));
1974 break;
1975
1976 case nir_instr_type_jump:
1977 emit_jump(ctx, nir_instr_as_jump(instr));
1978 break;
1979
1980 case nir_instr_type_ssa_undef:
1981 /* Spurious */
1982 break;
1983
1984 default:
1985 DBG("Unhandled instruction type\n");
1986 break;
1987 }
1988 }
1989
1990
1991 /* ALU instructions can inline or embed constants, which decreases register
1992 * pressure and saves space. */
1993
1994 #define CONDITIONAL_ATTACH(idx) { \
1995 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1996 \
1997 if (entry) { \
1998 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1999 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2000 } \
2001 }
2002
2003 static void
2004 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2005 {
2006 mir_foreach_instr_in_block(block, alu) {
2007 /* Other instructions cannot inline constants */
2008 if (alu->type != TAG_ALU_4) continue;
2009 if (alu->compact_branch) continue;
2010
2011 /* If there is already a constant here, we can do nothing */
2012 if (alu->has_constants) continue;
2013
2014 CONDITIONAL_ATTACH(0);
2015
2016 if (!alu->has_constants) {
2017 CONDITIONAL_ATTACH(1)
2018 } else if (!alu->inline_constant) {
2019 /* Corner case: _two_ vec4 constants, for instance with a
2020 * csel. For this case, we can only use a constant
2021 * register for one, we'll have to emit a move for the
2022 * other. */
2023
2024 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2025 unsigned scratch = make_compiler_temp(ctx);
2026
2027 if (entry) {
2028 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2029 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2030
2031 /* Set the source */
2032 alu->src[1] = scratch;
2033
2034 /* Inject us -before- the last instruction which set r31 */
2035 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2036 }
2037 }
2038 }
2039 }
2040
2041 /* Being a little silly with the names, but returns the op that is the bitwise
2042 * inverse of the op with the argument switched. I.e. (f and g are
2043 * contrapositives):
2044 *
2045 * f(a, b) = ~g(b, a)
2046 *
2047 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2048 *
2049 * f(a, b) = ~g(b, a)
2050 * ~f(a, b) = g(b, a)
2051 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2052 * f(a, b) = h(a, b)
2053 *
2054 * Thus we define this function in pairs.
2055 */
2056
2057 static inline midgard_alu_op
2058 mir_contrapositive(midgard_alu_op op)
2059 {
2060 switch (op) {
2061 case midgard_alu_op_flt:
2062 return midgard_alu_op_fle;
2063 case midgard_alu_op_fle:
2064 return midgard_alu_op_flt;
2065
2066 case midgard_alu_op_ilt:
2067 return midgard_alu_op_ile;
2068 case midgard_alu_op_ile:
2069 return midgard_alu_op_ilt;
2070
2071 default:
2072 unreachable("No known contrapositive");
2073 }
2074 }
2075
2076 /* Midgard supports two types of constants, embedded constants (128-bit) and
2077 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2078 * constants can be demoted to inline constants, for space savings and
2079 * sometimes a performance boost */
2080
2081 static void
2082 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2083 {
2084 mir_foreach_instr_in_block(block, ins) {
2085 if (!ins->has_constants) continue;
2086 if (ins->has_inline_constant) continue;
2087
2088 /* Blend constants must not be inlined by definition */
2089 if (ins->has_blend_constant) continue;
2090
2091 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2092 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2093 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2094
2095 if (!(is_16 || is_32))
2096 continue;
2097
2098 /* src1 cannot be an inline constant due to encoding
2099 * restrictions. So, if possible we try to flip the arguments
2100 * in that case */
2101
2102 int op = ins->alu.op;
2103
2104 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2105 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2106
2107 switch (op) {
2108 /* Conditionals can be inverted */
2109 case midgard_alu_op_flt:
2110 case midgard_alu_op_ilt:
2111 case midgard_alu_op_fle:
2112 case midgard_alu_op_ile:
2113 ins->alu.op = mir_contrapositive(ins->alu.op);
2114 ins->invert = true;
2115 flip = true;
2116 break;
2117
2118 case midgard_alu_op_fcsel:
2119 case midgard_alu_op_icsel:
2120 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2121 default:
2122 break;
2123 }
2124
2125 if (flip)
2126 mir_flip(ins);
2127 }
2128
2129 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2130 /* Extract the source information */
2131
2132 midgard_vector_alu_src *src;
2133 int q = ins->alu.src2;
2134 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2135 src = m;
2136
2137 /* Component is from the swizzle. Take a nonzero component */
2138 assert(ins->mask);
2139 unsigned first_comp = ffs(ins->mask) - 1;
2140 unsigned component = ins->swizzle[1][first_comp];
2141
2142 /* Scale constant appropriately, if we can legally */
2143 uint16_t scaled_constant = 0;
2144
2145 if (is_16) {
2146 scaled_constant = ins->constants.u16[component];
2147 } else if (midgard_is_integer_op(op)) {
2148 scaled_constant = ins->constants.u32[component];
2149
2150 /* Constant overflow after resize */
2151 if (scaled_constant != ins->constants.u32[component])
2152 continue;
2153 } else {
2154 float original = ins->constants.f32[component];
2155 scaled_constant = _mesa_float_to_half(original);
2156
2157 /* Check for loss of precision. If this is
2158 * mediump, we don't care, but for a highp
2159 * shader, we need to pay attention. NIR
2160 * doesn't yet tell us which mode we're in!
2161 * Practically this prevents most constants
2162 * from being inlined, sadly. */
2163
2164 float fp32 = _mesa_half_to_float(scaled_constant);
2165
2166 if (fp32 != original)
2167 continue;
2168 }
2169
2170 /* We don't know how to handle these with a constant */
2171
2172 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2173 DBG("Bailing inline constant...\n");
2174 continue;
2175 }
2176
2177 /* Make sure that the constant is not itself a vector
2178 * by checking if all accessed values are the same. */
2179
2180 const midgard_constants *cons = &ins->constants;
2181 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2182
2183 bool is_vector = false;
2184 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2185
2186 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2187 /* We only care if this component is actually used */
2188 if (!(mask & (1 << c)))
2189 continue;
2190
2191 uint32_t test = is_16 ?
2192 cons->u16[ins->swizzle[1][c]] :
2193 cons->u32[ins->swizzle[1][c]];
2194
2195 if (test != value) {
2196 is_vector = true;
2197 break;
2198 }
2199 }
2200
2201 if (is_vector)
2202 continue;
2203
2204 /* Get rid of the embedded constant */
2205 ins->has_constants = false;
2206 ins->src[1] = ~0;
2207 ins->has_inline_constant = true;
2208 ins->inline_constant = scaled_constant;
2209 }
2210 }
2211 }
2212
2213 /* Dead code elimination for branches at the end of a block - only one branch
2214 * per block is legal semantically */
2215
2216 static void
2217 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2218 {
2219 bool branched = false;
2220
2221 mir_foreach_instr_in_block_safe(block, ins) {
2222 if (!midgard_is_branch_unit(ins->unit)) continue;
2223
2224 if (branched)
2225 mir_remove_instruction(ins);
2226
2227 branched = true;
2228 }
2229 }
2230
2231 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2232 * the move can be propagated away entirely */
2233
2234 static bool
2235 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2236 {
2237 /* Nothing to do */
2238 if (comp == midgard_outmod_none)
2239 return true;
2240
2241 if (*outmod == midgard_outmod_none) {
2242 *outmod = comp;
2243 return true;
2244 }
2245
2246 /* TODO: Compose rules */
2247 return false;
2248 }
2249
2250 static bool
2251 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2252 {
2253 bool progress = false;
2254
2255 mir_foreach_instr_in_block_safe(block, ins) {
2256 if (ins->type != TAG_ALU_4) continue;
2257 if (ins->alu.op != midgard_alu_op_fmov) continue;
2258 if (ins->alu.outmod != midgard_outmod_pos) continue;
2259
2260 /* TODO: Registers? */
2261 unsigned src = ins->src[1];
2262 if (src & PAN_IS_REG) continue;
2263
2264 /* There might be a source modifier, too */
2265 if (mir_nontrivial_source2_mod(ins)) continue;
2266
2267 /* Backpropagate the modifier */
2268 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2269 if (v->type != TAG_ALU_4) continue;
2270 if (v->dest != src) continue;
2271
2272 /* Can we even take a float outmod? */
2273 if (midgard_is_integer_out_op(v->alu.op)) continue;
2274
2275 midgard_outmod_float temp = v->alu.outmod;
2276 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2277
2278 /* Throw in the towel.. */
2279 if (!progress) break;
2280
2281 /* Otherwise, transfer the modifier */
2282 v->alu.outmod = temp;
2283 ins->alu.outmod = midgard_outmod_none;
2284
2285 break;
2286 }
2287 }
2288
2289 return progress;
2290 }
2291
2292 static unsigned
2293 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2294 {
2295 /* Loop to ourselves */
2296 midgard_instruction *br = ctx->writeout_branch[rt];
2297 struct midgard_instruction ins = v_branch(false, false);
2298 ins.writeout = true;
2299 ins.writeout_depth = br->writeout_depth;
2300 ins.writeout_stencil = br->writeout_stencil;
2301 ins.branch.target_block = ctx->block_count - 1;
2302 ins.constants.u32[0] = br->constants.u32[0];
2303 emit_mir_instruction(ctx, ins);
2304
2305 ctx->current_block->epilogue = true;
2306 schedule_barrier(ctx);
2307 return ins.branch.target_block;
2308 }
2309
2310 static midgard_block *
2311 emit_block(compiler_context *ctx, nir_block *block)
2312 {
2313 midgard_block *this_block = ctx->after_block;
2314 ctx->after_block = NULL;
2315
2316 if (!this_block)
2317 this_block = create_empty_block(ctx);
2318
2319 list_addtail(&this_block->base.link, &ctx->blocks);
2320
2321 this_block->scheduled = false;
2322 ++ctx->block_count;
2323
2324 /* Set up current block */
2325 list_inithead(&this_block->base.instructions);
2326 ctx->current_block = this_block;
2327
2328 nir_foreach_instr(instr, block) {
2329 emit_instr(ctx, instr);
2330 ++ctx->instruction_count;
2331 }
2332
2333 return this_block;
2334 }
2335
2336 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2337
2338 static void
2339 emit_if(struct compiler_context *ctx, nir_if *nif)
2340 {
2341 midgard_block *before_block = ctx->current_block;
2342
2343 /* Speculatively emit the branch, but we can't fill it in until later */
2344 EMIT(branch, true, true);
2345 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2346 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2347
2348 /* Emit the two subblocks. */
2349 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2350 midgard_block *end_then_block = ctx->current_block;
2351
2352 /* Emit a jump from the end of the then block to the end of the else */
2353 EMIT(branch, false, false);
2354 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2355
2356 /* Emit second block, and check if it's empty */
2357
2358 int else_idx = ctx->block_count;
2359 int count_in = ctx->instruction_count;
2360 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2361 midgard_block *end_else_block = ctx->current_block;
2362 int after_else_idx = ctx->block_count;
2363
2364 /* Now that we have the subblocks emitted, fix up the branches */
2365
2366 assert(then_block);
2367 assert(else_block);
2368
2369 if (ctx->instruction_count == count_in) {
2370 /* The else block is empty, so don't emit an exit jump */
2371 mir_remove_instruction(then_exit);
2372 then_branch->branch.target_block = after_else_idx;
2373 } else {
2374 then_branch->branch.target_block = else_idx;
2375 then_exit->branch.target_block = after_else_idx;
2376 }
2377
2378 /* Wire up the successors */
2379
2380 ctx->after_block = create_empty_block(ctx);
2381
2382 pan_block_add_successor(&before_block->base, &then_block->base);
2383 pan_block_add_successor(&before_block->base, &else_block->base);
2384
2385 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2386 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2387 }
2388
2389 static void
2390 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2391 {
2392 /* Remember where we are */
2393 midgard_block *start_block = ctx->current_block;
2394
2395 /* Allocate a loop number, growing the current inner loop depth */
2396 int loop_idx = ++ctx->current_loop_depth;
2397
2398 /* Get index from before the body so we can loop back later */
2399 int start_idx = ctx->block_count;
2400
2401 /* Emit the body itself */
2402 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2403
2404 /* Branch back to loop back */
2405 struct midgard_instruction br_back = v_branch(false, false);
2406 br_back.branch.target_block = start_idx;
2407 emit_mir_instruction(ctx, br_back);
2408
2409 /* Mark down that branch in the graph. */
2410 pan_block_add_successor(&start_block->base, &loop_block->base);
2411 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2412
2413 /* Find the index of the block about to follow us (note: we don't add
2414 * one; blocks are 0-indexed so we get a fencepost problem) */
2415 int break_block_idx = ctx->block_count;
2416
2417 /* Fix up the break statements we emitted to point to the right place,
2418 * now that we can allocate a block number for them */
2419 ctx->after_block = create_empty_block(ctx);
2420
2421 mir_foreach_block_from(ctx, start_block, _block) {
2422 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2423 if (ins->type != TAG_ALU_4) continue;
2424 if (!ins->compact_branch) continue;
2425
2426 /* We found a branch -- check the type to see if we need to do anything */
2427 if (ins->branch.target_type != TARGET_BREAK) continue;
2428
2429 /* It's a break! Check if it's our break */
2430 if (ins->branch.target_break != loop_idx) continue;
2431
2432 /* Okay, cool, we're breaking out of this loop.
2433 * Rewrite from a break to a goto */
2434
2435 ins->branch.target_type = TARGET_GOTO;
2436 ins->branch.target_block = break_block_idx;
2437
2438 pan_block_add_successor(_block, &ctx->after_block->base);
2439 }
2440 }
2441
2442 /* Now that we've finished emitting the loop, free up the depth again
2443 * so we play nice with recursion amid nested loops */
2444 --ctx->current_loop_depth;
2445
2446 /* Dump loop stats */
2447 ++ctx->loop_count;
2448 }
2449
2450 static midgard_block *
2451 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2452 {
2453 midgard_block *start_block = NULL;
2454
2455 foreach_list_typed(nir_cf_node, node, node, list) {
2456 switch (node->type) {
2457 case nir_cf_node_block: {
2458 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2459
2460 if (!start_block)
2461 start_block = block;
2462
2463 break;
2464 }
2465
2466 case nir_cf_node_if:
2467 emit_if(ctx, nir_cf_node_as_if(node));
2468 break;
2469
2470 case nir_cf_node_loop:
2471 emit_loop(ctx, nir_cf_node_as_loop(node));
2472 break;
2473
2474 case nir_cf_node_function:
2475 assert(0);
2476 break;
2477 }
2478 }
2479
2480 return start_block;
2481 }
2482
2483 /* Due to lookahead, we need to report the first tag executed in the command
2484 * stream and in branch targets. An initial block might be empty, so iterate
2485 * until we find one that 'works' */
2486
2487 static unsigned
2488 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2489 {
2490 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2491
2492 mir_foreach_block_from(ctx, initial_block, _v) {
2493 midgard_block *v = (midgard_block *) _v;
2494 if (v->quadword_count) {
2495 midgard_bundle *initial_bundle =
2496 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2497
2498 return initial_bundle->tag;
2499 }
2500 }
2501
2502 /* Default to a tag 1 which will break from the shader, in case we jump
2503 * to the exit block (i.e. `return` in a compute shader) */
2504
2505 return 1;
2506 }
2507
2508 /* For each fragment writeout instruction, generate a writeout loop to
2509 * associate with it */
2510
2511 static void
2512 mir_add_writeout_loops(compiler_context *ctx)
2513 {
2514 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2515 midgard_instruction *br = ctx->writeout_branch[rt];
2516 if (!br) continue;
2517
2518 unsigned popped = br->branch.target_block;
2519 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2520 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2521
2522 /* If we have more RTs, we'll need to restore back after our
2523 * loop terminates */
2524
2525 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2526 midgard_instruction uncond = v_branch(false, false);
2527 uncond.branch.target_block = popped;
2528 emit_mir_instruction(ctx, uncond);
2529 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2530 schedule_barrier(ctx);
2531 } else {
2532 /* We're last, so we can terminate here */
2533 br->last_writeout = true;
2534 }
2535 }
2536 }
2537
2538 int
2539 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2540 {
2541 struct util_dynarray *compiled = &program->compiled;
2542
2543 midgard_debug = debug_get_option_midgard_debug();
2544
2545 /* TODO: Bound against what? */
2546 compiler_context *ctx = rzalloc(NULL, compiler_context);
2547
2548 ctx->nir = nir;
2549 ctx->stage = nir->info.stage;
2550 ctx->is_blend = is_blend;
2551 ctx->alpha_ref = program->alpha_ref;
2552 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2553 ctx->quirks = midgard_get_quirks(gpu_id);
2554
2555 /* Start off with a safe cutoff, allowing usage of all 16 work
2556 * registers. Later, we'll promote uniform reads to uniform registers
2557 * if we determine it is beneficial to do so */
2558 ctx->uniform_cutoff = 8;
2559
2560 /* Initialize at a global (not block) level hash tables */
2561
2562 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2563 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2564
2565 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2566 * (so we don't accidentally duplicate the epilogue since mesa/st has
2567 * messed with our I/O quite a bit already) */
2568
2569 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2570
2571 if (ctx->stage == MESA_SHADER_VERTEX) {
2572 NIR_PASS_V(nir, nir_lower_viewport_transform);
2573 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2574 }
2575
2576 NIR_PASS_V(nir, nir_lower_var_copies);
2577 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2578 NIR_PASS_V(nir, nir_split_var_copies);
2579 NIR_PASS_V(nir, nir_lower_var_copies);
2580 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2581 NIR_PASS_V(nir, nir_lower_var_copies);
2582 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2583
2584 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2585 NIR_PASS_V(nir, nir_lower_ssbo);
2586 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2587
2588 /* Optimisation passes */
2589
2590 optimise_nir(nir, ctx->quirks);
2591
2592 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2593 nir_print_shader(nir, stdout);
2594 }
2595
2596 /* Assign sysvals and counts, now that we're sure
2597 * (post-optimisation) */
2598
2599 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2600 program->sysval_count = ctx->sysvals.sysval_count;
2601 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2602
2603 nir_foreach_function(func, nir) {
2604 if (!func->impl)
2605 continue;
2606
2607 list_inithead(&ctx->blocks);
2608 ctx->block_count = 0;
2609 ctx->func = func;
2610
2611 emit_cf_list(ctx, &func->impl->body);
2612 break; /* TODO: Multi-function shaders */
2613 }
2614
2615 util_dynarray_init(compiled, NULL);
2616
2617 /* Per-block lowering before opts */
2618
2619 mir_foreach_block(ctx, _block) {
2620 midgard_block *block = (midgard_block *) _block;
2621 inline_alu_constants(ctx, block);
2622 midgard_opt_promote_fmov(ctx, block);
2623 embedded_to_inline_constant(ctx, block);
2624 }
2625 /* MIR-level optimizations */
2626
2627 bool progress = false;
2628
2629 do {
2630 progress = false;
2631
2632 mir_foreach_block(ctx, _block) {
2633 midgard_block *block = (midgard_block *) _block;
2634 progress |= midgard_opt_pos_propagate(ctx, block);
2635 progress |= midgard_opt_copy_prop(ctx, block);
2636 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2637 progress |= midgard_opt_combine_projection(ctx, block);
2638 progress |= midgard_opt_varying_projection(ctx, block);
2639 progress |= midgard_opt_not_propagate(ctx, block);
2640 progress |= midgard_opt_fuse_src_invert(ctx, block);
2641 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2642 progress |= midgard_opt_csel_invert(ctx, block);
2643 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2644 progress |= midgard_opt_invert_branch(ctx, block);
2645 }
2646 } while (progress);
2647
2648 mir_foreach_block(ctx, _block) {
2649 midgard_block *block = (midgard_block *) _block;
2650 midgard_lower_invert(ctx, block);
2651 midgard_lower_derivatives(ctx, block);
2652 }
2653
2654 /* Nested control-flow can result in dead branches at the end of the
2655 * block. This messes with our analysis and is just dead code, so cull
2656 * them */
2657 mir_foreach_block(ctx, _block) {
2658 midgard_block *block = (midgard_block *) _block;
2659 midgard_opt_cull_dead_branch(ctx, block);
2660 }
2661
2662 /* Ensure we were lowered */
2663 mir_foreach_instr_global(ctx, ins) {
2664 assert(!ins->invert);
2665 }
2666
2667 if (ctx->stage == MESA_SHADER_FRAGMENT)
2668 mir_add_writeout_loops(ctx);
2669
2670 /* Schedule! */
2671 midgard_schedule_program(ctx);
2672 mir_ra(ctx);
2673
2674 /* Now that all the bundles are scheduled and we can calculate block
2675 * sizes, emit actual branch instructions rather than placeholders */
2676
2677 int br_block_idx = 0;
2678
2679 mir_foreach_block(ctx, _block) {
2680 midgard_block *block = (midgard_block *) _block;
2681 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2682 for (int c = 0; c < bundle->instruction_count; ++c) {
2683 midgard_instruction *ins = bundle->instructions[c];
2684
2685 if (!midgard_is_branch_unit(ins->unit)) continue;
2686
2687 /* Parse some basic branch info */
2688 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2689 bool is_conditional = ins->branch.conditional;
2690 bool is_inverted = ins->branch.invert_conditional;
2691 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2692 bool is_writeout = ins->writeout;
2693
2694 /* Determine the block we're jumping to */
2695 int target_number = ins->branch.target_block;
2696
2697 /* Report the destination tag */
2698 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2699
2700 /* Count up the number of quadwords we're
2701 * jumping over = number of quadwords until
2702 * (br_block_idx, target_number) */
2703
2704 int quadword_offset = 0;
2705
2706 if (is_discard) {
2707 /* Ignored */
2708 } else if (target_number > br_block_idx) {
2709 /* Jump forward */
2710
2711 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2712 midgard_block *blk = mir_get_block(ctx, idx);
2713 assert(blk);
2714
2715 quadword_offset += blk->quadword_count;
2716 }
2717 } else {
2718 /* Jump backwards */
2719
2720 for (int idx = br_block_idx; idx >= target_number; --idx) {
2721 midgard_block *blk = mir_get_block(ctx, idx);
2722 assert(blk);
2723
2724 quadword_offset -= blk->quadword_count;
2725 }
2726 }
2727
2728 /* Unconditional extended branches (far jumps)
2729 * have issues, so we always use a conditional
2730 * branch, setting the condition to always for
2731 * unconditional. For compact unconditional
2732 * branches, cond isn't used so it doesn't
2733 * matter what we pick. */
2734
2735 midgard_condition cond =
2736 !is_conditional ? midgard_condition_always :
2737 is_inverted ? midgard_condition_false :
2738 midgard_condition_true;
2739
2740 midgard_jmp_writeout_op op =
2741 is_discard ? midgard_jmp_writeout_op_discard :
2742 is_writeout ? midgard_jmp_writeout_op_writeout :
2743 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2744 midgard_jmp_writeout_op_branch_cond;
2745
2746 if (!is_compact) {
2747 midgard_branch_extended branch =
2748 midgard_create_branch_extended(
2749 cond, op,
2750 dest_tag,
2751 quadword_offset);
2752
2753 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2754 } else if (is_conditional || is_discard) {
2755 midgard_branch_cond branch = {
2756 .op = op,
2757 .dest_tag = dest_tag,
2758 .offset = quadword_offset,
2759 .cond = cond
2760 };
2761
2762 assert(branch.offset == quadword_offset);
2763
2764 memcpy(&ins->br_compact, &branch, sizeof(branch));
2765 } else {
2766 assert(op == midgard_jmp_writeout_op_branch_uncond);
2767
2768 midgard_branch_uncond branch = {
2769 .op = op,
2770 .dest_tag = dest_tag,
2771 .offset = quadword_offset,
2772 .unknown = 1
2773 };
2774
2775 assert(branch.offset == quadword_offset);
2776
2777 memcpy(&ins->br_compact, &branch, sizeof(branch));
2778 }
2779 }
2780 }
2781
2782 ++br_block_idx;
2783 }
2784
2785 /* Emit flat binary from the instruction arrays. Iterate each block in
2786 * sequence. Save instruction boundaries such that lookahead tags can
2787 * be assigned easily */
2788
2789 /* Cache _all_ bundles in source order for lookahead across failed branches */
2790
2791 int bundle_count = 0;
2792 mir_foreach_block(ctx, _block) {
2793 midgard_block *block = (midgard_block *) _block;
2794 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2795 }
2796 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2797 int bundle_idx = 0;
2798 mir_foreach_block(ctx, _block) {
2799 midgard_block *block = (midgard_block *) _block;
2800 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2801 source_order_bundles[bundle_idx++] = bundle;
2802 }
2803 }
2804
2805 int current_bundle = 0;
2806
2807 /* Midgard prefetches instruction types, so during emission we
2808 * need to lookahead. Unless this is the last instruction, in
2809 * which we return 1. */
2810
2811 mir_foreach_block(ctx, _block) {
2812 midgard_block *block = (midgard_block *) _block;
2813 mir_foreach_bundle_in_block(block, bundle) {
2814 int lookahead = 1;
2815
2816 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2817 lookahead = source_order_bundles[current_bundle + 1]->tag;
2818
2819 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2820 ++current_bundle;
2821 }
2822
2823 /* TODO: Free deeper */
2824 //util_dynarray_fini(&block->instructions);
2825 }
2826
2827 free(source_order_bundles);
2828
2829 /* Report the very first tag executed */
2830 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2831
2832 /* Deal with off-by-one related to the fencepost problem */
2833 program->work_register_count = ctx->work_registers + 1;
2834 program->uniform_cutoff = ctx->uniform_cutoff;
2835
2836 program->blend_patch_offset = ctx->blend_constant_offset;
2837 program->tls_size = ctx->tls_size;
2838
2839 if (midgard_debug & MIDGARD_DBG_SHADERS)
2840 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2841
2842 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2843 unsigned nr_bundles = 0, nr_ins = 0;
2844
2845 /* Count instructions and bundles */
2846
2847 mir_foreach_block(ctx, _block) {
2848 midgard_block *block = (midgard_block *) _block;
2849 nr_bundles += util_dynarray_num_elements(
2850 &block->bundles, midgard_bundle);
2851
2852 mir_foreach_bundle_in_block(block, bun)
2853 nr_ins += bun->instruction_count;
2854 }
2855
2856 /* Calculate thread count. There are certain cutoffs by
2857 * register count for thread count */
2858
2859 unsigned nr_registers = program->work_register_count;
2860
2861 unsigned nr_threads =
2862 (nr_registers <= 4) ? 4 :
2863 (nr_registers <= 8) ? 2 :
2864 1;
2865
2866 /* Dump stats */
2867
2868 fprintf(stderr, "shader%d - %s shader: "
2869 "%u inst, %u bundles, %u quadwords, "
2870 "%u registers, %u threads, %u loops, "
2871 "%u:%u spills:fills\n",
2872 SHADER_DB_COUNT++,
2873 gl_shader_stage_name(ctx->stage),
2874 nr_ins, nr_bundles, ctx->quadword_count,
2875 nr_registers, nr_threads,
2876 ctx->loop_count,
2877 ctx->spills, ctx->fills);
2878 }
2879
2880 ralloc_free(ctx);
2881
2882 return 0;
2883 }