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panfrost: Treat texture dimension as first-class
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51 #include "panfrost-quirks.h"
52 #include "panfrost/util/pan_lower_framebuffer.h"
53
54 #include "disassemble.h"
55
56 static const struct debug_named_value debug_options[] = {
57 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
58 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
59 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
60 DEBUG_NAMED_VALUE_END
61 };
62
63 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
64
65 unsigned SHADER_DB_COUNT = 0;
66
67 int midgard_debug = 0;
68
69 #define DBG(fmt, ...) \
70 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
71 fprintf(stderr, "%s:%d: "fmt, \
72 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 static midgard_block *
74 create_empty_block(compiler_context *ctx)
75 {
76 midgard_block *blk = rzalloc(ctx, midgard_block);
77
78 blk->base.predecessors = _mesa_set_create(blk,
79 _mesa_hash_pointer,
80 _mesa_key_pointer_equal);
81
82 blk->base.name = ctx->block_source_count++;
83
84 return blk;
85 }
86
87 static void
88 schedule_barrier(compiler_context *ctx)
89 {
90 midgard_block *temp = ctx->after_block;
91 ctx->after_block = create_empty_block(ctx);
92 ctx->block_count++;
93 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
94 list_inithead(&ctx->after_block->base.instructions);
95 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
96 ctx->current_block = ctx->after_block;
97 ctx->after_block = temp;
98 }
99
100 /* Helpers to generate midgard_instruction's using macro magic, since every
101 * driver seems to do it that way */
102
103 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
104
105 #define M_LOAD_STORE(name, store, T) \
106 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
107 midgard_instruction i = { \
108 .type = TAG_LOAD_STORE_4, \
109 .mask = 0xF, \
110 .dest = ~0, \
111 .src = { ~0, ~0, ~0, ~0 }, \
112 .swizzle = SWIZZLE_IDENTITY_4, \
113 .op = midgard_op_##name, \
114 .load_store = { \
115 .address = address \
116 } \
117 }; \
118 \
119 if (store) { \
120 i.src[0] = ssa; \
121 i.src_types[0] = T; \
122 i.dest_type = T; \
123 } else { \
124 i.dest = ssa; \
125 i.dest_type = T; \
126 } \
127 return i; \
128 }
129
130 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
131 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
132
133 M_LOAD(ld_attr_32, nir_type_uint32);
134 M_LOAD(ld_vary_32, nir_type_uint32);
135 M_LOAD(ld_ubo_int4, nir_type_uint32);
136 M_LOAD(ld_int4, nir_type_uint32);
137 M_STORE(st_int4, nir_type_uint32);
138 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
139 M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
140 M_LOAD(ld_color_buffer_as_fp32, nir_type_float32);
141 M_STORE(st_vary_32, nir_type_uint32);
142 M_LOAD(ld_cubemap_coords, nir_type_uint32);
143 M_LOAD(ld_compute_id, nir_type_uint32);
144
145 static midgard_instruction
146 v_branch(bool conditional, bool invert)
147 {
148 midgard_instruction ins = {
149 .type = TAG_ALU_4,
150 .unit = ALU_ENAB_BRANCH,
151 .compact_branch = true,
152 .branch = {
153 .conditional = conditional,
154 .invert_conditional = invert
155 },
156 .dest = ~0,
157 .src = { ~0, ~0, ~0, ~0 },
158 };
159
160 return ins;
161 }
162
163 static void
164 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
165 {
166 ins->has_constants = true;
167 memcpy(&ins->constants, constants, 16);
168 }
169
170 static int
171 glsl_type_size(const struct glsl_type *type, bool bindless)
172 {
173 return glsl_count_attribute_slots(type, false);
174 }
175
176 /* Lower fdot2 to a vector multiplication followed by channel addition */
177 static void
178 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
179 {
180 if (alu->op != nir_op_fdot2)
181 return;
182
183 b->cursor = nir_before_instr(&alu->instr);
184
185 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
186 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
187
188 nir_ssa_def *product = nir_fmul(b, src0, src1);
189
190 nir_ssa_def *sum = nir_fadd(b,
191 nir_channel(b, product, 0),
192 nir_channel(b, product, 1));
193
194 /* Replace the fdot2 with this sum */
195 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
196 }
197
198 static bool
199 midgard_nir_lower_fdot2(nir_shader *shader)
200 {
201 bool progress = false;
202
203 nir_foreach_function(function, shader) {
204 if (!function->impl) continue;
205
206 nir_builder _b;
207 nir_builder *b = &_b;
208 nir_builder_init(b, function->impl);
209
210 nir_foreach_block(block, function->impl) {
211 nir_foreach_instr_safe(instr, block) {
212 if (instr->type != nir_instr_type_alu) continue;
213
214 nir_alu_instr *alu = nir_instr_as_alu(instr);
215 midgard_nir_lower_fdot2_body(b, alu);
216
217 progress |= true;
218 }
219 }
220
221 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
222
223 }
224
225 return progress;
226 }
227
228 static const nir_variable *
229 search_var(nir_shader *nir, nir_variable_mode mode, unsigned driver_loc)
230 {
231 nir_foreach_variable_with_modes(var, nir, mode) {
232 if (var->data.driver_location == driver_loc)
233 return var;
234 }
235
236 return NULL;
237 }
238
239 /* Midgard can write all of color, depth and stencil in a single writeout
240 * operation, so we merge depth/stencil stores with color stores.
241 * If there are no color stores, we add a write to the "depth RT".
242 */
243 static bool
244 midgard_nir_lower_zs_store(nir_shader *nir)
245 {
246 if (nir->info.stage != MESA_SHADER_FRAGMENT)
247 return false;
248
249 nir_variable *z_var = NULL, *s_var = NULL;
250
251 nir_foreach_shader_out_variable(var, nir) {
252 if (var->data.location == FRAG_RESULT_DEPTH)
253 z_var = var;
254 else if (var->data.location == FRAG_RESULT_STENCIL)
255 s_var = var;
256 }
257
258 if (!z_var && !s_var)
259 return false;
260
261 bool progress = false;
262
263 nir_foreach_function(function, nir) {
264 if (!function->impl) continue;
265
266 nir_intrinsic_instr *z_store = NULL, *s_store = NULL;
267
268 nir_foreach_block(block, function->impl) {
269 nir_foreach_instr_safe(instr, block) {
270 if (instr->type != nir_instr_type_intrinsic)
271 continue;
272
273 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
274 if (intr->intrinsic != nir_intrinsic_store_output)
275 continue;
276
277 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
278 assert(!z_store);
279 z_store = intr;
280 }
281
282 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
283 assert(!s_store);
284 s_store = intr;
285 }
286 }
287 }
288
289 if (!z_store && !s_store) continue;
290
291 bool replaced = false;
292
293 nir_foreach_block(block, function->impl) {
294 nir_foreach_instr_safe(instr, block) {
295 if (instr->type != nir_instr_type_intrinsic)
296 continue;
297
298 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
299 if (intr->intrinsic != nir_intrinsic_store_output)
300 continue;
301
302 const nir_variable *var = search_var(nir, nir_var_shader_out, nir_intrinsic_base(intr));
303 assert(var);
304
305 if (var->data.location != FRAG_RESULT_COLOR &&
306 var->data.location < FRAG_RESULT_DATA0)
307 continue;
308
309 if (var->data.index)
310 continue;
311
312 assert(nir_src_is_const(intr->src[1]) && "no indirect outputs");
313
314 nir_builder b;
315 nir_builder_init(&b, function->impl);
316
317 assert(!z_store || z_store->instr.block == instr->block);
318 assert(!s_store || s_store->instr.block == instr->block);
319 b.cursor = nir_after_block_before_jump(instr->block);
320
321 nir_intrinsic_instr *combined_store;
322 combined_store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_combined_output_pan);
323
324 combined_store->num_components = intr->src[0].ssa->num_components;
325
326 nir_intrinsic_set_base(combined_store, nir_intrinsic_base(intr));
327
328 unsigned writeout = PAN_WRITEOUT_C;
329 if (z_store)
330 writeout |= PAN_WRITEOUT_Z;
331 if (s_store)
332 writeout |= PAN_WRITEOUT_S;
333
334 nir_intrinsic_set_component(combined_store, writeout);
335
336 struct nir_ssa_def *zero = nir_imm_int(&b, 0);
337
338 struct nir_ssa_def *src[4] = {
339 intr->src[0].ssa,
340 intr->src[1].ssa,
341 z_store ? z_store->src[0].ssa : zero,
342 s_store ? s_store->src[0].ssa : zero,
343 };
344
345 for (int i = 0; i < 4; ++i)
346 combined_store->src[i] = nir_src_for_ssa(src[i]);
347
348 nir_builder_instr_insert(&b, &combined_store->instr);
349
350 nir_instr_remove(instr);
351
352 replaced = true;
353 }
354 }
355
356 /* Insert a store to the depth RT (0xff) if needed */
357 if (!replaced) {
358 nir_builder b;
359 nir_builder_init(&b, function->impl);
360
361 nir_block *block = NULL;
362 if (z_store && s_store)
363 assert(z_store->instr.block == s_store->instr.block);
364
365 if (z_store)
366 block = z_store->instr.block;
367 else
368 block = s_store->instr.block;
369
370 b.cursor = nir_after_block_before_jump(block);
371
372 nir_intrinsic_instr *combined_store;
373 combined_store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_combined_output_pan);
374
375 combined_store->num_components = 4;
376
377 unsigned base;
378 if (z_store)
379 base = nir_intrinsic_base(z_store);
380 else
381 base = nir_intrinsic_base(s_store);
382 nir_intrinsic_set_base(combined_store, base);
383
384 unsigned writeout = 0;
385 if (z_store)
386 writeout |= PAN_WRITEOUT_Z;
387 if (s_store)
388 writeout |= PAN_WRITEOUT_S;
389
390 nir_intrinsic_set_component(combined_store, writeout);
391
392 struct nir_ssa_def *zero = nir_imm_int(&b, 0);
393
394 struct nir_ssa_def *src[4] = {
395 nir_imm_vec4(&b, 0, 0, 0, 0),
396 zero,
397 z_store ? z_store->src[0].ssa : zero,
398 s_store ? s_store->src[0].ssa : zero,
399 };
400
401 for (int i = 0; i < 4; ++i)
402 combined_store->src[i] = nir_src_for_ssa(src[i]);
403
404 nir_builder_instr_insert(&b, &combined_store->instr);
405 }
406
407 if (z_store)
408 nir_instr_remove(&z_store->instr);
409
410 if (s_store)
411 nir_instr_remove(&s_store->instr);
412
413 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
414 progress = true;
415 }
416
417 return progress;
418 }
419
420 /* Real writeout stores, which break execution, need to be moved to after
421 * dual-source stores, which are just standard register writes. */
422 static bool
423 midgard_nir_reorder_writeout(nir_shader *nir)
424 {
425 bool progress = false;
426
427 nir_foreach_function(function, nir) {
428 if (!function->impl) continue;
429
430 nir_foreach_block(block, function->impl) {
431 nir_instr *last_writeout = NULL;
432
433 nir_foreach_instr_reverse_safe(instr, block) {
434 if (instr->type != nir_instr_type_intrinsic)
435 continue;
436
437 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
438 if (intr->intrinsic != nir_intrinsic_store_output)
439 continue;
440
441 const nir_variable *var = search_var(nir, nir_var_shader_out, nir_intrinsic_base(intr));
442
443 if (var->data.index) {
444 if (!last_writeout)
445 last_writeout = instr;
446 continue;
447 }
448
449 if (!last_writeout)
450 continue;
451
452 /* This is a real store, so move it to after dual-source stores */
453 exec_node_remove(&instr->node);
454 exec_node_insert_after(&last_writeout->node, &instr->node);
455
456 progress = true;
457 }
458 }
459 }
460
461 return progress;
462 }
463
464 /* Flushes undefined values to zero */
465
466 static void
467 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
468 {
469 bool progress;
470 unsigned lower_flrp =
471 (nir->options->lower_flrp16 ? 16 : 0) |
472 (nir->options->lower_flrp32 ? 32 : 0) |
473 (nir->options->lower_flrp64 ? 64 : 0);
474
475 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
476 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
477
478 nir_lower_tex_options lower_tex_options = {
479 .lower_txs_lod = true,
480 .lower_txp = ~0,
481 .lower_tex_without_implicit_lod =
482 (quirks & MIDGARD_EXPLICIT_LOD),
483
484 /* TODO: we have native gradient.. */
485 .lower_txd = true,
486 };
487
488 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
489
490 /* Must lower fdot2 after tex is lowered */
491 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
492
493 /* T720 is broken. */
494
495 if (quirks & MIDGARD_BROKEN_LOD)
496 NIR_PASS_V(nir, midgard_nir_lod_errata);
497
498 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
499
500 do {
501 progress = false;
502
503 NIR_PASS(progress, nir, nir_lower_var_copies);
504 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
505
506 NIR_PASS(progress, nir, nir_copy_prop);
507 NIR_PASS(progress, nir, nir_opt_remove_phis);
508 NIR_PASS(progress, nir, nir_opt_dce);
509 NIR_PASS(progress, nir, nir_opt_dead_cf);
510 NIR_PASS(progress, nir, nir_opt_cse);
511 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
512 NIR_PASS(progress, nir, nir_opt_algebraic);
513 NIR_PASS(progress, nir, nir_opt_constant_folding);
514
515 if (lower_flrp != 0) {
516 bool lower_flrp_progress = false;
517 NIR_PASS(lower_flrp_progress,
518 nir,
519 nir_lower_flrp,
520 lower_flrp,
521 false /* always_precise */,
522 nir->options->lower_ffma);
523 if (lower_flrp_progress) {
524 NIR_PASS(progress, nir,
525 nir_opt_constant_folding);
526 progress = true;
527 }
528
529 /* Nothing should rematerialize any flrps, so we only
530 * need to do this lowering once.
531 */
532 lower_flrp = 0;
533 }
534
535 NIR_PASS(progress, nir, nir_opt_undef);
536 NIR_PASS(progress, nir, nir_undef_to_zero);
537
538 NIR_PASS(progress, nir, nir_opt_loop_unroll,
539 nir_var_shader_in |
540 nir_var_shader_out |
541 nir_var_function_temp);
542
543 NIR_PASS(progress, nir, nir_opt_vectorize);
544 } while (progress);
545
546 /* Run after opts so it can hit more */
547 if (!is_blend)
548 NIR_PASS(progress, nir, nir_fuse_io_16);
549
550 /* Must be run at the end to prevent creation of fsin/fcos ops */
551 NIR_PASS(progress, nir, midgard_nir_scale_trig);
552
553 do {
554 progress = false;
555
556 NIR_PASS(progress, nir, nir_opt_dce);
557 NIR_PASS(progress, nir, nir_opt_algebraic);
558 NIR_PASS(progress, nir, nir_opt_constant_folding);
559 NIR_PASS(progress, nir, nir_copy_prop);
560 } while (progress);
561
562 NIR_PASS(progress, nir, nir_opt_algebraic_late);
563 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
564
565 /* We implement booleans as 32-bit 0/~0 */
566 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
567
568 /* Now that booleans are lowered, we can run out late opts */
569 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
570 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
571
572 NIR_PASS(progress, nir, nir_copy_prop);
573 NIR_PASS(progress, nir, nir_opt_dce);
574
575 /* Take us out of SSA */
576 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
577 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
578
579 /* We are a vector architecture; write combine where possible */
580 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
581 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
582
583 NIR_PASS(progress, nir, nir_opt_dce);
584 }
585
586 /* Do not actually emit a load; instead, cache the constant for inlining */
587
588 static void
589 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
590 {
591 nir_ssa_def def = instr->def;
592
593 midgard_constants *consts = rzalloc(NULL, midgard_constants);
594
595 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
596
597 #define RAW_CONST_COPY(bits) \
598 nir_const_value_to_array(consts->u##bits, instr->value, \
599 instr->def.num_components, u##bits)
600
601 switch (instr->def.bit_size) {
602 case 64:
603 RAW_CONST_COPY(64);
604 break;
605 case 32:
606 RAW_CONST_COPY(32);
607 break;
608 case 16:
609 RAW_CONST_COPY(16);
610 break;
611 case 8:
612 RAW_CONST_COPY(8);
613 break;
614 default:
615 unreachable("Invalid bit_size for load_const instruction\n");
616 }
617
618 /* Shifted for SSA, +1 for off-by-one */
619 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
620 }
621
622 /* Normally constants are embedded implicitly, but for I/O and such we have to
623 * explicitly emit a move with the constant source */
624
625 static void
626 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
627 {
628 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
629
630 if (constant_value) {
631 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
632 attach_constants(ctx, &ins, constant_value, node + 1);
633 emit_mir_instruction(ctx, ins);
634 }
635 }
636
637 static bool
638 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
639 {
640 unsigned comp = src->swizzle[0];
641
642 for (unsigned c = 1; c < nr_components; ++c) {
643 if (src->swizzle[c] != comp)
644 return true;
645 }
646
647 return false;
648 }
649
650 #define ALU_CASE(nir, _op) \
651 case nir_op_##nir: \
652 op = midgard_alu_op_##_op; \
653 assert(src_bitsize == dst_bitsize); \
654 break;
655
656 #define ALU_CASE_RTZ(nir, _op) \
657 case nir_op_##nir: \
658 op = midgard_alu_op_##_op; \
659 roundmode = MIDGARD_RTZ; \
660 break;
661
662 #define ALU_CHECK_CMP(sext) \
663 assert(src_bitsize == 16 || src_bitsize == 32); \
664 assert(dst_bitsize == 16 || dst_bitsize == 32); \
665
666 #define ALU_CASE_BCAST(nir, _op, count) \
667 case nir_op_##nir: \
668 op = midgard_alu_op_##_op; \
669 broadcast_swizzle = count; \
670 ALU_CHECK_CMP(true); \
671 break;
672
673 #define ALU_CASE_CMP(nir, _op, sext) \
674 case nir_op_##nir: \
675 op = midgard_alu_op_##_op; \
676 ALU_CHECK_CMP(sext); \
677 break;
678
679 /* Compare mir_lower_invert */
680 static bool
681 nir_accepts_inot(nir_op op, unsigned src)
682 {
683 switch (op) {
684 case nir_op_ior:
685 case nir_op_iand: /* TODO: b2f16 */
686 case nir_op_ixor:
687 return true;
688 case nir_op_b32csel:
689 /* Only the condition */
690 return (src == 0);
691 default:
692 return false;
693 }
694 }
695
696 static bool
697 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
698 {
699 if (pan_has_dest_mod(dest, op)) {
700 assert((*dest)->is_ssa);
701 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
702 return true;
703 }
704
705 return false;
706 }
707
708 /* Look for floating point mods. We have the mods fsat, fsat_signed,
709 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
710 *
711 * fsat_signed(fpos(x)) = fsat(x)
712 * fsat_signed(fsat(x)) = fsat(x)
713 * fpos(fsat_signed(x)) = fsat(x)
714 * fpos(fsat(x)) = fsat(x)
715 * fsat(fsat_signed(x)) = fsat(x)
716 * fsat(fpos(x)) = fsat(x)
717 *
718 * So by cases any composition of output modifiers is equivalent to
719 * fsat alone.
720 */
721 static unsigned
722 mir_determine_float_outmod(compiler_context *ctx, nir_dest **dest, unsigned prior_outmod)
723 {
724 bool fpos = mir_accept_dest_mod(ctx, dest, nir_op_fclamp_pos);
725 bool fsat = mir_accept_dest_mod(ctx, dest, nir_op_fsat);
726 bool ssat = mir_accept_dest_mod(ctx, dest, nir_op_fsat_signed);
727 bool prior = (prior_outmod != midgard_outmod_none);
728 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
729
730 return ((count > 1) || fsat) ? midgard_outmod_sat :
731 fpos ? midgard_outmod_pos :
732 ssat ? midgard_outmod_sat_signed :
733 prior_outmod;
734 }
735
736 static void
737 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
738 {
739 nir_alu_src src = instr->src[i];
740
741 if (!is_int) {
742 if (pan_has_source_mod(&src, nir_op_fneg))
743 *neg = !(*neg);
744
745 if (pan_has_source_mod(&src, nir_op_fabs))
746 *abs = true;
747 }
748
749 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
750 *not = true;
751
752 if (roundmode) {
753 if (pan_has_source_mod(&src, nir_op_fround_even))
754 *roundmode = MIDGARD_RTE;
755
756 if (pan_has_source_mod(&src, nir_op_ftrunc))
757 *roundmode = MIDGARD_RTZ;
758
759 if (pan_has_source_mod(&src, nir_op_ffloor))
760 *roundmode = MIDGARD_RTN;
761
762 if (pan_has_source_mod(&src, nir_op_fceil))
763 *roundmode = MIDGARD_RTP;
764 }
765
766 unsigned bits = nir_src_bit_size(src.src);
767
768 ins->src[to] = nir_src_index(NULL, &src.src);
769 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
770
771 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
772 ins->swizzle[to][c] = src.swizzle[
773 (!bcast_count || c < bcast_count) ? c :
774 (bcast_count - 1)];
775 }
776 }
777
778 /* Midgard features both fcsel and icsel, depending on whether you want int or
779 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
780 * we should emit an int or float csel depending on what modifiers could be
781 * placed. In the absense of modifiers, this is probably arbitrary. */
782
783 static bool
784 mir_is_bcsel_float(nir_alu_instr *instr)
785 {
786 nir_op intmods[] = {
787 nir_op_i2i8, nir_op_i2i16,
788 nir_op_i2i32, nir_op_i2i64
789 };
790
791 nir_op floatmods[] = {
792 nir_op_fabs, nir_op_fneg,
793 nir_op_f2f16, nir_op_f2f32,
794 nir_op_f2f64
795 };
796
797 nir_op floatdestmods[] = {
798 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
799 nir_op_f2f16, nir_op_f2f32
800 };
801
802 signed score = 0;
803
804 for (unsigned i = 1; i < 3; ++i) {
805 nir_alu_src s = instr->src[i];
806 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
807 if (pan_has_source_mod(&s, intmods[q]))
808 score--;
809 }
810 }
811
812 for (unsigned i = 1; i < 3; ++i) {
813 nir_alu_src s = instr->src[i];
814 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
815 if (pan_has_source_mod(&s, floatmods[q]))
816 score++;
817 }
818 }
819
820 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
821 nir_dest *dest = &instr->dest.dest;
822 if (pan_has_dest_mod(&dest, floatdestmods[q]))
823 score++;
824 }
825
826 return (score > 0);
827 }
828
829 static void
830 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
831 {
832 nir_dest *dest = &instr->dest.dest;
833
834 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
835 return;
836
837 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
838 * is handled elsewhere */
839
840 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
841 midgard_emit_derivatives(ctx, instr);
842 return;
843 }
844
845 bool is_ssa = dest->is_ssa;
846
847 unsigned nr_components = nir_dest_num_components(*dest);
848 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
849 unsigned op = 0;
850
851 /* Number of components valid to check for the instruction (the rest
852 * will be forced to the last), or 0 to use as-is. Relevant as
853 * ball-type instructions have a channel count in NIR but are all vec4
854 * in Midgard */
855
856 unsigned broadcast_swizzle = 0;
857
858 /* Should we swap arguments? */
859 bool flip_src12 = false;
860
861 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
862 unsigned dst_bitsize = nir_dest_bit_size(*dest);
863
864 enum midgard_roundmode roundmode = MIDGARD_RTE;
865
866 switch (instr->op) {
867 ALU_CASE(fadd, fadd);
868 ALU_CASE(fmul, fmul);
869 ALU_CASE(fmin, fmin);
870 ALU_CASE(fmax, fmax);
871 ALU_CASE(imin, imin);
872 ALU_CASE(imax, imax);
873 ALU_CASE(umin, umin);
874 ALU_CASE(umax, umax);
875 ALU_CASE(ffloor, ffloor);
876 ALU_CASE(fround_even, froundeven);
877 ALU_CASE(ftrunc, ftrunc);
878 ALU_CASE(fceil, fceil);
879 ALU_CASE(fdot3, fdot3);
880 ALU_CASE(fdot4, fdot4);
881 ALU_CASE(iadd, iadd);
882 ALU_CASE(isub, isub);
883 ALU_CASE(imul, imul);
884
885 /* Zero shoved as second-arg */
886 ALU_CASE(iabs, iabsdiff);
887
888 ALU_CASE(mov, imov);
889
890 ALU_CASE_CMP(feq32, feq, false);
891 ALU_CASE_CMP(fne32, fne, false);
892 ALU_CASE_CMP(flt32, flt, false);
893 ALU_CASE_CMP(ieq32, ieq, true);
894 ALU_CASE_CMP(ine32, ine, true);
895 ALU_CASE_CMP(ilt32, ilt, true);
896 ALU_CASE_CMP(ult32, ult, false);
897
898 /* We don't have a native b2f32 instruction. Instead, like many
899 * GPUs, we exploit booleans as 0/~0 for false/true, and
900 * correspondingly AND
901 * by 1.0 to do the type conversion. For the moment, prime us
902 * to emit:
903 *
904 * iand [whatever], #0
905 *
906 * At the end of emit_alu (as MIR), we'll fix-up the constant
907 */
908
909 ALU_CASE_CMP(b2f32, iand, true);
910 ALU_CASE_CMP(b2f16, iand, true);
911 ALU_CASE_CMP(b2i32, iand, true);
912
913 /* Likewise, we don't have a dedicated f2b32 instruction, but
914 * we can do a "not equal to 0.0" test. */
915
916 ALU_CASE_CMP(f2b32, fne, false);
917 ALU_CASE_CMP(i2b32, ine, true);
918
919 ALU_CASE(frcp, frcp);
920 ALU_CASE(frsq, frsqrt);
921 ALU_CASE(fsqrt, fsqrt);
922 ALU_CASE(fexp2, fexp2);
923 ALU_CASE(flog2, flog2);
924
925 ALU_CASE_RTZ(f2i64, f2i_rte);
926 ALU_CASE_RTZ(f2u64, f2u_rte);
927 ALU_CASE_RTZ(i2f64, i2f_rte);
928 ALU_CASE_RTZ(u2f64, u2f_rte);
929
930 ALU_CASE_RTZ(f2i32, f2i_rte);
931 ALU_CASE_RTZ(f2u32, f2u_rte);
932 ALU_CASE_RTZ(i2f32, i2f_rte);
933 ALU_CASE_RTZ(u2f32, u2f_rte);
934
935 ALU_CASE_RTZ(f2i8, f2i_rte);
936 ALU_CASE_RTZ(f2u8, f2u_rte);
937
938 ALU_CASE_RTZ(f2i16, f2i_rte);
939 ALU_CASE_RTZ(f2u16, f2u_rte);
940 ALU_CASE_RTZ(i2f16, i2f_rte);
941 ALU_CASE_RTZ(u2f16, u2f_rte);
942
943 ALU_CASE(fsin, fsin);
944 ALU_CASE(fcos, fcos);
945
946 /* We'll get 0 in the second arg, so:
947 * ~a = ~(a | 0) = nor(a, 0) */
948 ALU_CASE(inot, inor);
949 ALU_CASE(iand, iand);
950 ALU_CASE(ior, ior);
951 ALU_CASE(ixor, ixor);
952 ALU_CASE(ishl, ishl);
953 ALU_CASE(ishr, iasr);
954 ALU_CASE(ushr, ilsr);
955
956 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
957 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
958 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
959
960 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
961 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
962 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
963
964 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
965 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
966 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
967
968 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
969 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
970 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
971
972 /* Source mods will be shoved in later */
973 ALU_CASE(fabs, fmov);
974 ALU_CASE(fneg, fmov);
975 ALU_CASE(fsat, fmov);
976 ALU_CASE(fsat_signed, fmov);
977 ALU_CASE(fclamp_pos, fmov);
978
979 /* For size conversion, we use a move. Ideally though we would squash
980 * these ops together; maybe that has to happen after in NIR as part of
981 * propagation...? An earlier algebraic pass ensured we step down by
982 * only / exactly one size. If stepping down, we use a dest override to
983 * reduce the size; if stepping up, we use a larger-sized move with a
984 * half source and a sign/zero-extension modifier */
985
986 case nir_op_i2i8:
987 case nir_op_i2i16:
988 case nir_op_i2i32:
989 case nir_op_i2i64:
990 case nir_op_u2u8:
991 case nir_op_u2u16:
992 case nir_op_u2u32:
993 case nir_op_u2u64:
994 case nir_op_f2f16:
995 case nir_op_f2f32:
996 case nir_op_f2f64: {
997 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
998 instr->op == nir_op_f2f64)
999 op = midgard_alu_op_fmov;
1000 else
1001 op = midgard_alu_op_imov;
1002
1003 break;
1004 }
1005
1006 /* For greater-or-equal, we lower to less-or-equal and flip the
1007 * arguments */
1008
1009 case nir_op_fge:
1010 case nir_op_fge32:
1011 case nir_op_ige32:
1012 case nir_op_uge32: {
1013 op =
1014 instr->op == nir_op_fge ? midgard_alu_op_fle :
1015 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
1016 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
1017 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
1018 0;
1019
1020 flip_src12 = true;
1021 ALU_CHECK_CMP(false);
1022 break;
1023 }
1024
1025 case nir_op_b32csel: {
1026 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
1027 bool is_float = mir_is_bcsel_float(instr);
1028 op = is_float ?
1029 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
1030 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
1031
1032 break;
1033 }
1034
1035 case nir_op_unpack_32_2x16:
1036 case nir_op_unpack_32_4x8:
1037 case nir_op_pack_32_2x16:
1038 case nir_op_pack_32_4x8: {
1039 op = midgard_alu_op_imov;
1040 break;
1041 }
1042
1043 default:
1044 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
1045 assert(0);
1046 return;
1047 }
1048
1049 /* Promote imov to fmov if it might help inline a constant */
1050 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
1051 && nir_src_bit_size(instr->src[0].src) == 32
1052 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
1053 nir_src_num_components(instr->src[0].src))) {
1054 op = midgard_alu_op_fmov;
1055 }
1056
1057 /* Midgard can perform certain modifiers on output of an ALU op */
1058
1059 unsigned outmod = 0;
1060 bool is_int = midgard_is_integer_op(op);
1061
1062 if (midgard_is_integer_out_op(op)) {
1063 outmod = midgard_outmod_int_wrap;
1064 } else if (instr->op == nir_op_fsat) {
1065 outmod = midgard_outmod_sat;
1066 } else if (instr->op == nir_op_fsat_signed) {
1067 outmod = midgard_outmod_sat_signed;
1068 } else if (instr->op == nir_op_fclamp_pos) {
1069 outmod = midgard_outmod_pos;
1070 }
1071
1072 /* Fetch unit, quirks, etc information */
1073 unsigned opcode_props = alu_opcode_props[op].props;
1074 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
1075
1076 if (!midgard_is_integer_out_op(op)) {
1077 outmod = mir_determine_float_outmod(ctx, &dest, outmod);
1078 }
1079
1080 midgard_instruction ins = {
1081 .type = TAG_ALU_4,
1082 .dest = nir_dest_index(dest),
1083 .dest_type = nir_op_infos[instr->op].output_type
1084 | nir_dest_bit_size(*dest),
1085 .roundmode = roundmode,
1086 };
1087
1088 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
1089 &ins.roundmode : NULL;
1090
1091 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1092 ins.src[i] = ~0;
1093
1094 if (quirk_flipped_r24) {
1095 ins.src[0] = ~0;
1096 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
1097 } else {
1098 for (unsigned i = 0; i < nr_inputs; ++i) {
1099 unsigned to = i;
1100
1101 if (instr->op == nir_op_b32csel) {
1102 /* The condition is the first argument; move
1103 * the other arguments up one to be a binary
1104 * instruction for Midgard with the condition
1105 * last */
1106
1107 if (i == 0)
1108 to = 2;
1109 else if (flip_src12)
1110 to = 2 - i;
1111 else
1112 to = i - 1;
1113 } else if (flip_src12) {
1114 to = 1 - to;
1115 }
1116
1117 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
1118
1119 /* (!c) ? a : b = c ? b : a */
1120 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1121 ins.src_invert[2] = false;
1122 flip_src12 ^= true;
1123 }
1124 }
1125 }
1126
1127 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1128 /* Lowered to move */
1129 if (instr->op == nir_op_fneg)
1130 ins.src_neg[1] ^= true;
1131
1132 if (instr->op == nir_op_fabs)
1133 ins.src_abs[1] = true;
1134 }
1135
1136 ins.mask = mask_of(nr_components);
1137
1138 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1139 * components that don't exist. Note modifier => SSA => !reg => no
1140 * writemask, so we don't have to worry about writemasks here.*/
1141
1142 if (!is_ssa)
1143 ins.mask &= instr->dest.write_mask;
1144
1145 ins.op = op;
1146 ins.outmod = outmod;
1147
1148 /* Late fixup for emulated instructions */
1149
1150 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1151 /* Presently, our second argument is an inline #0 constant.
1152 * Switch over to an embedded 1.0 constant (that can't fit
1153 * inline, since we're 32-bit, not 16-bit like the inline
1154 * constants) */
1155
1156 ins.has_inline_constant = false;
1157 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1158 ins.src_types[1] = nir_type_float32;
1159 ins.has_constants = true;
1160
1161 if (instr->op == nir_op_b2f32)
1162 ins.constants.f32[0] = 1.0f;
1163 else
1164 ins.constants.i32[0] = 1;
1165
1166 for (unsigned c = 0; c < 16; ++c)
1167 ins.swizzle[1][c] = 0;
1168 } else if (instr->op == nir_op_b2f16) {
1169 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1170 ins.src_types[1] = nir_type_float16;
1171 ins.has_constants = true;
1172 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1173
1174 for (unsigned c = 0; c < 16; ++c)
1175 ins.swizzle[1][c] = 0;
1176 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1177 /* Lots of instructions need a 0 plonked in */
1178 ins.has_inline_constant = false;
1179 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1180 ins.src_types[1] = ins.src_types[0];
1181 ins.has_constants = true;
1182 ins.constants.u32[0] = 0;
1183
1184 for (unsigned c = 0; c < 16; ++c)
1185 ins.swizzle[1][c] = 0;
1186 } else if (instr->op == nir_op_pack_32_2x16) {
1187 ins.dest_type = nir_type_uint16;
1188 ins.mask = mask_of(nr_components * 2);
1189 ins.is_pack = true;
1190 } else if (instr->op == nir_op_pack_32_4x8) {
1191 ins.dest_type = nir_type_uint8;
1192 ins.mask = mask_of(nr_components * 4);
1193 ins.is_pack = true;
1194 } else if (instr->op == nir_op_unpack_32_2x16) {
1195 ins.dest_type = nir_type_uint32;
1196 ins.mask = mask_of(nr_components >> 1);
1197 ins.is_pack = true;
1198 } else if (instr->op == nir_op_unpack_32_4x8) {
1199 ins.dest_type = nir_type_uint32;
1200 ins.mask = mask_of(nr_components >> 2);
1201 ins.is_pack = true;
1202 }
1203
1204 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1205 /* To avoid duplicating the lookup tables (probably), true LUT
1206 * instructions can only operate as if they were scalars. Lower
1207 * them here by changing the component. */
1208
1209 unsigned orig_mask = ins.mask;
1210
1211 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1212 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1213
1214 midgard_instruction ins_split[MIR_VEC_COMPONENTS];
1215 unsigned ins_count = 0;
1216
1217 for (int i = 0; i < nr_components; ++i) {
1218 /* Mask the associated component, dropping the
1219 * instruction if needed */
1220
1221 ins.mask = 1 << i;
1222 ins.mask &= orig_mask;
1223
1224 for (unsigned j = 0; j < ins_count; ++j) {
1225 if (swizzle_back[i] == ins_split[j].swizzle[0][0]) {
1226 ins_split[j].mask |= ins.mask;
1227 ins.mask = 0;
1228 break;
1229 }
1230 }
1231
1232 if (!ins.mask)
1233 continue;
1234
1235 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1236 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1237
1238 ins_split[ins_count] = ins;
1239
1240 ++ins_count;
1241 }
1242
1243 for (unsigned i = 0; i < ins_count; ++i) {
1244 emit_mir_instruction(ctx, ins_split[i]);
1245 }
1246 } else {
1247 emit_mir_instruction(ctx, ins);
1248 }
1249 }
1250
1251 #undef ALU_CASE
1252
1253 static void
1254 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1255 {
1256 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1257 unsigned nir_mask = 0;
1258 unsigned dsize = 0;
1259
1260 if (is_read) {
1261 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1262 dsize = nir_dest_bit_size(intr->dest);
1263 } else {
1264 nir_mask = nir_intrinsic_write_mask(intr);
1265 dsize = 32;
1266 }
1267
1268 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1269 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1270 mir_set_bytemask(ins, bytemask);
1271 ins->dest_type = nir_type_uint | dsize;
1272 }
1273
1274 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1275 * optimized) versions of UBO #0 */
1276
1277 static midgard_instruction *
1278 emit_ubo_read(
1279 compiler_context *ctx,
1280 nir_instr *instr,
1281 unsigned dest,
1282 unsigned offset,
1283 nir_src *indirect_offset,
1284 unsigned indirect_shift,
1285 unsigned index)
1286 {
1287 /* TODO: half-floats */
1288
1289 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1290 ins.constants.u32[0] = offset;
1291
1292 if (instr->type == nir_instr_type_intrinsic)
1293 mir_set_intr_mask(instr, &ins, true);
1294
1295 if (indirect_offset) {
1296 ins.src[2] = nir_src_index(ctx, indirect_offset);
1297 ins.src_types[2] = nir_type_uint32;
1298 ins.load_store.arg_2 = (indirect_shift << 5);
1299
1300 /* X component for the whole swizzle to prevent register
1301 * pressure from ballooning from the extra components */
1302 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[2]); ++i)
1303 ins.swizzle[2][i] = 0;
1304 } else {
1305 ins.load_store.arg_2 = 0x1E;
1306 }
1307
1308 ins.load_store.arg_1 = index;
1309
1310 return emit_mir_instruction(ctx, ins);
1311 }
1312
1313 /* Globals are like UBOs if you squint. And shared memory is like globals if
1314 * you squint even harder */
1315
1316 static void
1317 emit_global(
1318 compiler_context *ctx,
1319 nir_instr *instr,
1320 bool is_read,
1321 unsigned srcdest,
1322 nir_src *offset,
1323 bool is_shared)
1324 {
1325 /* TODO: types */
1326
1327 midgard_instruction ins;
1328
1329 if (is_read)
1330 ins = m_ld_int4(srcdest, 0);
1331 else
1332 ins = m_st_int4(srcdest, 0);
1333
1334 mir_set_offset(ctx, &ins, offset, is_shared);
1335 mir_set_intr_mask(instr, &ins, is_read);
1336
1337 emit_mir_instruction(ctx, ins);
1338 }
1339
1340 static void
1341 emit_varying_read(
1342 compiler_context *ctx,
1343 unsigned dest, unsigned offset,
1344 unsigned nr_comp, unsigned component,
1345 nir_src *indirect_offset, nir_alu_type type, bool flat)
1346 {
1347 /* XXX: Half-floats? */
1348 /* TODO: swizzle, mask */
1349
1350 midgard_instruction ins = m_ld_vary_32(dest, offset);
1351 ins.mask = mask_of(nr_comp);
1352 ins.dest_type = type;
1353
1354 if (type == nir_type_float16) {
1355 /* Ensure we are aligned so we can pack it later */
1356 ins.mask = mask_of(ALIGN_POT(nr_comp, 2));
1357 }
1358
1359 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1360 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1361
1362 midgard_varying_parameter p = {
1363 .is_varying = 1,
1364 .interpolation = midgard_interp_default,
1365 .flat = flat,
1366 };
1367
1368 unsigned u;
1369 memcpy(&u, &p, sizeof(p));
1370 ins.load_store.varying_parameters = u;
1371
1372 if (indirect_offset) {
1373 ins.src[2] = nir_src_index(ctx, indirect_offset);
1374 ins.src_types[2] = nir_type_uint32;
1375 } else
1376 ins.load_store.arg_2 = 0x1E;
1377
1378 ins.load_store.arg_1 = 0x9E;
1379
1380 /* Use the type appropriate load */
1381 switch (type) {
1382 case nir_type_uint32:
1383 case nir_type_bool32:
1384 ins.op = midgard_op_ld_vary_32u;
1385 break;
1386 case nir_type_int32:
1387 ins.op = midgard_op_ld_vary_32i;
1388 break;
1389 case nir_type_float32:
1390 ins.op = midgard_op_ld_vary_32;
1391 break;
1392 case nir_type_float16:
1393 ins.op = midgard_op_ld_vary_16;
1394 break;
1395 default:
1396 unreachable("Attempted to load unknown type");
1397 break;
1398 }
1399
1400 emit_mir_instruction(ctx, ins);
1401 }
1402
1403 static void
1404 emit_attr_read(
1405 compiler_context *ctx,
1406 unsigned dest, unsigned offset,
1407 unsigned nr_comp, nir_alu_type t)
1408 {
1409 midgard_instruction ins = m_ld_attr_32(dest, offset);
1410 ins.load_store.arg_1 = 0x1E;
1411 ins.load_store.arg_2 = 0x1E;
1412 ins.mask = mask_of(nr_comp);
1413
1414 /* Use the type appropriate load */
1415 switch (t) {
1416 case nir_type_uint:
1417 case nir_type_bool:
1418 ins.op = midgard_op_ld_attr_32u;
1419 break;
1420 case nir_type_int:
1421 ins.op = midgard_op_ld_attr_32i;
1422 break;
1423 case nir_type_float:
1424 ins.op = midgard_op_ld_attr_32;
1425 break;
1426 default:
1427 unreachable("Attempted to load unknown type");
1428 break;
1429 }
1430
1431 emit_mir_instruction(ctx, ins);
1432 }
1433
1434 static void
1435 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1436 unsigned nr_components, unsigned offset)
1437 {
1438 nir_dest nir_dest;
1439
1440 /* Figure out which uniform this is */
1441 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1442 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1443
1444 unsigned dest = nir_dest_index(&nir_dest);
1445
1446 /* Sysvals are prefix uniforms */
1447 unsigned uniform = ((uintptr_t) val) - 1;
1448
1449 /* Emit the read itself -- this is never indirect */
1450 midgard_instruction *ins =
1451 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1452
1453 ins->mask = mask_of(nr_components);
1454 }
1455
1456 static unsigned
1457 compute_builtin_arg(nir_op op)
1458 {
1459 switch (op) {
1460 case nir_intrinsic_load_work_group_id:
1461 return 0x14;
1462 case nir_intrinsic_load_local_invocation_id:
1463 return 0x10;
1464 default:
1465 unreachable("Invalid compute paramater loaded");
1466 }
1467 }
1468
1469 static void
1470 emit_fragment_store(compiler_context *ctx, unsigned src, unsigned src_z, unsigned src_s, enum midgard_rt_id rt)
1471 {
1472 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1473
1474 midgard_instruction *br = ctx->writeout_branch[rt];
1475
1476 assert(!br);
1477
1478 emit_explicit_constant(ctx, src, src);
1479
1480 struct midgard_instruction ins =
1481 v_branch(false, false);
1482
1483 bool depth_only = (rt == MIDGARD_ZS_RT);
1484
1485 ins.writeout = depth_only ? 0 : PAN_WRITEOUT_C;
1486
1487 /* Add dependencies */
1488 ins.src[0] = src;
1489 ins.src_types[0] = nir_type_uint32;
1490 ins.constants.u32[0] = depth_only ? 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1491 for (int i = 0; i < 4; ++i)
1492 ins.swizzle[0][i] = i;
1493
1494 if (~src_z) {
1495 emit_explicit_constant(ctx, src_z, src_z);
1496 ins.src[2] = src_z;
1497 ins.src_types[2] = nir_type_uint32;
1498 ins.writeout |= PAN_WRITEOUT_Z;
1499 }
1500 if (~src_s) {
1501 emit_explicit_constant(ctx, src_s, src_s);
1502 ins.src[3] = src_s;
1503 ins.src_types[3] = nir_type_uint32;
1504 ins.writeout |= PAN_WRITEOUT_S;
1505 }
1506
1507 /* Emit the branch */
1508 br = emit_mir_instruction(ctx, ins);
1509 schedule_barrier(ctx);
1510 ctx->writeout_branch[rt] = br;
1511
1512 /* Push our current location = current block count - 1 = where we'll
1513 * jump to. Maybe a bit too clever for my own good */
1514
1515 br->branch.target_block = ctx->block_count - 1;
1516 }
1517
1518 static void
1519 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1520 {
1521 unsigned reg = nir_dest_index(&instr->dest);
1522 midgard_instruction ins = m_ld_compute_id(reg, 0);
1523 ins.mask = mask_of(3);
1524 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1525 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1526 emit_mir_instruction(ctx, ins);
1527 }
1528
1529 static unsigned
1530 vertex_builtin_arg(nir_op op)
1531 {
1532 switch (op) {
1533 case nir_intrinsic_load_vertex_id:
1534 return PAN_VERTEX_ID;
1535 case nir_intrinsic_load_instance_id:
1536 return PAN_INSTANCE_ID;
1537 default:
1538 unreachable("Invalid vertex builtin");
1539 }
1540 }
1541
1542 static void
1543 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1544 {
1545 unsigned reg = nir_dest_index(&instr->dest);
1546 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1547 }
1548
1549 static void
1550 emit_msaa_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1551 {
1552 unsigned reg = nir_dest_index(&instr->dest);
1553
1554 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1555 ld.op = midgard_op_ld_color_buffer_32u_old;
1556 ld.load_store.address = 97;
1557 ld.load_store.arg_2 = 0x1E;
1558
1559 for (int i = 0; i < 4; ++i)
1560 ld.swizzle[0][i] = COMPONENT_X;
1561
1562 emit_mir_instruction(ctx, ld);
1563 }
1564
1565 static void
1566 emit_control_barrier(compiler_context *ctx)
1567 {
1568 midgard_instruction ins = {
1569 .type = TAG_TEXTURE_4,
1570 .dest = ~0,
1571 .src = { ~0, ~0, ~0, ~0 },
1572 .op = TEXTURE_OP_BARRIER,
1573 .texture = {
1574 /* TODO: optimize */
1575 .out_of_order = MIDGARD_BARRIER_BUFFER |
1576 MIDGARD_BARRIER_SHARED ,
1577 }
1578 };
1579
1580 emit_mir_instruction(ctx, ins);
1581 }
1582
1583 static unsigned
1584 mir_get_branch_cond(nir_src *src, bool *invert)
1585 {
1586 /* Wrap it. No swizzle since it's a scalar */
1587
1588 nir_alu_src alu = {
1589 .src = *src
1590 };
1591
1592 *invert = pan_has_source_mod(&alu, nir_op_inot);
1593 return nir_src_index(NULL, &alu.src);
1594 }
1595
1596 static uint8_t
1597 output_load_rt_addr(compiler_context *ctx, nir_intrinsic_instr *instr)
1598 {
1599 if (ctx->is_blend)
1600 return ctx->blend_rt;
1601
1602 const nir_variable *var;
1603 var = search_var(ctx->nir, nir_var_shader_out, nir_intrinsic_base(instr));
1604 assert(var);
1605
1606 unsigned loc = var->data.location;
1607
1608 if (loc == FRAG_RESULT_COLOR)
1609 loc = FRAG_RESULT_DATA0;
1610
1611 if (loc >= FRAG_RESULT_DATA0)
1612 return loc - FRAG_RESULT_DATA0;
1613
1614 if (loc == FRAG_RESULT_DEPTH)
1615 return 0x1F;
1616 if (loc == FRAG_RESULT_STENCIL)
1617 return 0x1E;
1618
1619 unreachable("Invalid RT to load from");
1620 }
1621
1622 static void
1623 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1624 {
1625 unsigned offset = 0, reg;
1626
1627 switch (instr->intrinsic) {
1628 case nir_intrinsic_discard_if:
1629 case nir_intrinsic_discard: {
1630 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1631 struct midgard_instruction discard = v_branch(conditional, false);
1632 discard.branch.target_type = TARGET_DISCARD;
1633
1634 if (conditional) {
1635 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1636 &discard.branch.invert_conditional);
1637 discard.src_types[0] = nir_type_uint32;
1638 }
1639
1640 emit_mir_instruction(ctx, discard);
1641 schedule_barrier(ctx);
1642
1643 break;
1644 }
1645
1646 case nir_intrinsic_load_uniform:
1647 case nir_intrinsic_load_ubo:
1648 case nir_intrinsic_load_global:
1649 case nir_intrinsic_load_shared:
1650 case nir_intrinsic_load_input:
1651 case nir_intrinsic_load_interpolated_input: {
1652 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1653 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1654 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1655 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1656 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1657 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1658
1659 /* Get the base type of the intrinsic */
1660 /* TODO: Infer type? Does it matter? */
1661 nir_alu_type t =
1662 (is_ubo || is_global || is_shared) ? nir_type_uint :
1663 (is_interp) ? nir_type_float :
1664 nir_intrinsic_type(instr);
1665
1666 t = nir_alu_type_get_base_type(t);
1667
1668 if (!(is_ubo || is_global)) {
1669 offset = nir_intrinsic_base(instr);
1670 }
1671
1672 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1673
1674 nir_src *src_offset = nir_get_io_offset_src(instr);
1675
1676 bool direct = nir_src_is_const(*src_offset);
1677 nir_src *indirect_offset = direct ? NULL : src_offset;
1678
1679 if (direct)
1680 offset += nir_src_as_uint(*src_offset);
1681
1682 /* We may need to apply a fractional offset */
1683 int component = (is_flat || is_interp) ?
1684 nir_intrinsic_component(instr) : 0;
1685 reg = nir_dest_index(&instr->dest);
1686
1687 if (is_uniform && !ctx->is_blend) {
1688 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1689 } else if (is_ubo) {
1690 nir_src index = instr->src[0];
1691
1692 /* TODO: Is indirect block number possible? */
1693 assert(nir_src_is_const(index));
1694
1695 uint32_t uindex = nir_src_as_uint(index) + 1;
1696 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1697 } else if (is_global || is_shared) {
1698 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1699 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1700 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1701 } else if (ctx->is_blend) {
1702 /* ctx->blend_input will be precoloured to r0/r2, where
1703 * the input is preloaded */
1704
1705 unsigned *input = offset ? &ctx->blend_src1 : &ctx->blend_input;
1706
1707 if (*input == ~0)
1708 *input = reg;
1709 else
1710 emit_mir_instruction(ctx, v_mov(*input, reg));
1711 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1712 emit_attr_read(ctx, reg, offset, nr_comp, t);
1713 } else {
1714 DBG("Unknown load\n");
1715 assert(0);
1716 }
1717
1718 break;
1719 }
1720
1721 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1722 case nir_intrinsic_load_barycentric_pixel:
1723 case nir_intrinsic_load_barycentric_centroid:
1724 break;
1725
1726 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1727
1728 case nir_intrinsic_load_raw_output_pan: {
1729 reg = nir_dest_index(&instr->dest);
1730
1731 /* T720 and below use different blend opcodes with slightly
1732 * different semantics than T760 and up */
1733
1734 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1735
1736 ld.load_store.arg_2 = output_load_rt_addr(ctx, instr);
1737
1738 if (nir_src_is_const(instr->src[0])) {
1739 ld.load_store.arg_1 = nir_src_as_uint(instr->src[0]);
1740 } else {
1741 ld.load_store.varying_parameters = 2;
1742 ld.src[1] = nir_src_index(ctx, &instr->src[0]);
1743 ld.src_types[1] = nir_type_int32;
1744 }
1745
1746 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1747 ld.op = midgard_op_ld_color_buffer_32u_old;
1748 ld.load_store.address = 16;
1749 ld.load_store.arg_2 = 0x1E;
1750 }
1751
1752 emit_mir_instruction(ctx, ld);
1753 break;
1754 }
1755
1756 case nir_intrinsic_load_output: {
1757 reg = nir_dest_index(&instr->dest);
1758
1759 unsigned bits = nir_dest_bit_size(instr->dest);
1760
1761 midgard_instruction ld;
1762 if (bits == 16)
1763 ld = m_ld_color_buffer_as_fp16(reg, 0);
1764 else
1765 ld = m_ld_color_buffer_as_fp32(reg, 0);
1766
1767 ld.load_store.arg_2 = output_load_rt_addr(ctx, instr);
1768
1769 for (unsigned c = 4; c < 16; ++c)
1770 ld.swizzle[0][c] = 0;
1771
1772 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1773 if (bits == 16)
1774 ld.op = midgard_op_ld_color_buffer_as_fp16_old;
1775 else
1776 ld.op = midgard_op_ld_color_buffer_as_fp32_old;
1777 ld.load_store.address = 1;
1778 ld.load_store.arg_2 = 0x1E;
1779 }
1780
1781 emit_mir_instruction(ctx, ld);
1782 break;
1783 }
1784
1785 case nir_intrinsic_load_blend_const_color_rgba: {
1786 assert(ctx->is_blend);
1787 reg = nir_dest_index(&instr->dest);
1788
1789 /* Blend constants are embedded directly in the shader and
1790 * patched in, so we use some magic routing */
1791
1792 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1793 ins.has_constants = true;
1794 ins.has_blend_constant = true;
1795 emit_mir_instruction(ctx, ins);
1796 break;
1797 }
1798
1799 case nir_intrinsic_store_output:
1800 case nir_intrinsic_store_combined_output_pan:
1801 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1802
1803 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1804
1805 reg = nir_src_index(ctx, &instr->src[0]);
1806
1807 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1808 bool combined = instr->intrinsic ==
1809 nir_intrinsic_store_combined_output_pan;
1810
1811 const nir_variable *var;
1812 var = search_var(ctx->nir, nir_var_shader_out,
1813 nir_intrinsic_base(instr));
1814 assert(var);
1815
1816 /* Dual-source blend writeout is done by leaving the
1817 * value in r2 for the blend shader to use. */
1818 if (var->data.index) {
1819 if (instr->src[0].is_ssa) {
1820 emit_explicit_constant(ctx, reg, reg);
1821
1822 unsigned out = make_compiler_temp(ctx);
1823
1824 midgard_instruction ins = v_mov(reg, out);
1825 emit_mir_instruction(ctx, ins);
1826
1827 ctx->blend_src1 = out;
1828 } else {
1829 ctx->blend_src1 = reg;
1830 }
1831
1832 break;
1833 }
1834
1835 enum midgard_rt_id rt;
1836 if (var->data.location == FRAG_RESULT_COLOR)
1837 rt = MIDGARD_COLOR_RT0;
1838 else if (var->data.location >= FRAG_RESULT_DATA0)
1839 rt = MIDGARD_COLOR_RT0 + var->data.location -
1840 FRAG_RESULT_DATA0;
1841 else if (combined)
1842 rt = MIDGARD_ZS_RT;
1843 else
1844 assert(0);
1845
1846 unsigned reg_z = ~0, reg_s = ~0;
1847 if (combined) {
1848 unsigned writeout = nir_intrinsic_component(instr);
1849 if (writeout & PAN_WRITEOUT_Z)
1850 reg_z = nir_src_index(ctx, &instr->src[2]);
1851 if (writeout & PAN_WRITEOUT_S)
1852 reg_s = nir_src_index(ctx, &instr->src[3]);
1853 }
1854
1855 emit_fragment_store(ctx, reg, reg_z, reg_s, rt);
1856 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1857 assert(instr->intrinsic == nir_intrinsic_store_output);
1858
1859 /* We should have been vectorized, though we don't
1860 * currently check that st_vary is emitted only once
1861 * per slot (this is relevant, since there's not a mask
1862 * parameter available on the store [set to 0 by the
1863 * blob]). We do respect the component by adjusting the
1864 * swizzle. If this is a constant source, we'll need to
1865 * emit that explicitly. */
1866
1867 emit_explicit_constant(ctx, reg, reg);
1868
1869 unsigned dst_component = nir_intrinsic_component(instr);
1870 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1871
1872 midgard_instruction st = m_st_vary_32(reg, offset);
1873 st.load_store.arg_1 = 0x9E;
1874 st.load_store.arg_2 = 0x1E;
1875
1876 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1877 case nir_type_uint:
1878 case nir_type_bool:
1879 st.op = midgard_op_st_vary_32u;
1880 break;
1881 case nir_type_int:
1882 st.op = midgard_op_st_vary_32i;
1883 break;
1884 case nir_type_float:
1885 st.op = midgard_op_st_vary_32;
1886 break;
1887 default:
1888 unreachable("Attempted to store unknown type");
1889 break;
1890 }
1891
1892 /* nir_intrinsic_component(store_intr) encodes the
1893 * destination component start. Source component offset
1894 * adjustment is taken care of in
1895 * install_registers_instr(), when offset_swizzle() is
1896 * called.
1897 */
1898 unsigned src_component = COMPONENT_X;
1899
1900 assert(nr_comp > 0);
1901 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1902 st.swizzle[0][i] = src_component;
1903 if (i >= dst_component && i < dst_component + nr_comp - 1)
1904 src_component++;
1905 }
1906
1907 emit_mir_instruction(ctx, st);
1908 } else {
1909 DBG("Unknown store\n");
1910 assert(0);
1911 }
1912
1913 break;
1914
1915 /* Special case of store_output for lowered blend shaders */
1916 case nir_intrinsic_store_raw_output_pan:
1917 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1918 reg = nir_src_index(ctx, &instr->src[0]);
1919 emit_fragment_store(ctx, reg, ~0, ~0, ctx->blend_rt);
1920 break;
1921
1922 case nir_intrinsic_store_global:
1923 case nir_intrinsic_store_shared:
1924 reg = nir_src_index(ctx, &instr->src[0]);
1925 emit_explicit_constant(ctx, reg, reg);
1926
1927 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1928 break;
1929
1930 case nir_intrinsic_load_ssbo_address:
1931 emit_sysval_read(ctx, &instr->instr, 1, 0);
1932 break;
1933
1934 case nir_intrinsic_get_buffer_size:
1935 emit_sysval_read(ctx, &instr->instr, 1, 8);
1936 break;
1937
1938 case nir_intrinsic_load_viewport_scale:
1939 case nir_intrinsic_load_viewport_offset:
1940 case nir_intrinsic_load_num_work_groups:
1941 case nir_intrinsic_load_sampler_lod_parameters_pan:
1942 emit_sysval_read(ctx, &instr->instr, 3, 0);
1943 break;
1944
1945 case nir_intrinsic_load_work_group_id:
1946 case nir_intrinsic_load_local_invocation_id:
1947 emit_compute_builtin(ctx, instr);
1948 break;
1949
1950 case nir_intrinsic_load_vertex_id:
1951 case nir_intrinsic_load_instance_id:
1952 emit_vertex_builtin(ctx, instr);
1953 break;
1954
1955 case nir_intrinsic_load_sample_id:
1956 emit_msaa_builtin(ctx, instr);
1957 break;
1958
1959 case nir_intrinsic_memory_barrier_buffer:
1960 case nir_intrinsic_memory_barrier_shared:
1961 break;
1962
1963 case nir_intrinsic_control_barrier:
1964 schedule_barrier(ctx);
1965 emit_control_barrier(ctx);
1966 schedule_barrier(ctx);
1967 break;
1968
1969 default:
1970 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1971 assert(0);
1972 break;
1973 }
1974 }
1975
1976 /* Returns dimension with 0 special casing cubemaps */
1977 static unsigned
1978 midgard_tex_format(enum glsl_sampler_dim dim)
1979 {
1980 switch (dim) {
1981 case GLSL_SAMPLER_DIM_1D:
1982 case GLSL_SAMPLER_DIM_BUF:
1983 return 1;
1984
1985 case GLSL_SAMPLER_DIM_2D:
1986 case GLSL_SAMPLER_DIM_MS:
1987 case GLSL_SAMPLER_DIM_EXTERNAL:
1988 case GLSL_SAMPLER_DIM_RECT:
1989 return 2;
1990
1991 case GLSL_SAMPLER_DIM_3D:
1992 return 3;
1993
1994 case GLSL_SAMPLER_DIM_CUBE:
1995 return 0;
1996
1997 default:
1998 DBG("Unknown sampler dim type\n");
1999 assert(0);
2000 return 0;
2001 }
2002 }
2003
2004 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
2005 * was successful */
2006
2007 static bool
2008 pan_attach_constant_bias(
2009 compiler_context *ctx,
2010 nir_src lod,
2011 midgard_texture_word *word)
2012 {
2013 /* To attach as constant, it has to *be* constant */
2014
2015 if (!nir_src_is_const(lod))
2016 return false;
2017
2018 float f = nir_src_as_float(lod);
2019
2020 /* Break into fixed-point */
2021 signed lod_int = f;
2022 float lod_frac = f - lod_int;
2023
2024 /* Carry over negative fractions */
2025 if (lod_frac < 0.0) {
2026 lod_int--;
2027 lod_frac += 1.0;
2028 }
2029
2030 /* Encode */
2031 word->bias = float_to_ubyte(lod_frac);
2032 word->bias_int = lod_int;
2033
2034 return true;
2035 }
2036
2037 static void
2038 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
2039 unsigned midgard_texop)
2040 {
2041 /* TODO */
2042 //assert (!instr->sampler);
2043
2044 nir_dest *dest = &instr->dest;
2045
2046 int texture_index = instr->texture_index;
2047 int sampler_index = texture_index;
2048
2049 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
2050 nir_alu_type dest_type = dest_base | nir_dest_bit_size(*dest);
2051
2052 /* texture instructions support float outmods */
2053 unsigned outmod = midgard_outmod_none;
2054 if (dest_base == nir_type_float) {
2055 outmod = mir_determine_float_outmod(ctx, &dest, 0);
2056 }
2057
2058 midgard_instruction ins = {
2059 .type = TAG_TEXTURE_4,
2060 .mask = 0xF,
2061 .dest = nir_dest_index(dest),
2062 .src = { ~0, ~0, ~0, ~0 },
2063 .dest_type = dest_type,
2064 .swizzle = SWIZZLE_IDENTITY_4,
2065 .outmod = outmod,
2066 .op = midgard_texop,
2067 .texture = {
2068 .format = midgard_tex_format(instr->sampler_dim),
2069 .texture_handle = texture_index,
2070 .sampler_handle = sampler_index,
2071 .shadow = instr->is_shadow,
2072 }
2073 };
2074
2075 if (instr->is_shadow && !instr->is_new_style_shadow)
2076 for (int i = 0; i < 4; ++i)
2077 ins.swizzle[0][i] = COMPONENT_X;
2078
2079 /* We may need a temporary for the coordinate */
2080
2081 bool needs_temp_coord =
2082 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
2083 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
2084 (instr->is_shadow);
2085
2086 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
2087
2088 for (unsigned i = 0; i < instr->num_srcs; ++i) {
2089 int index = nir_src_index(ctx, &instr->src[i].src);
2090 unsigned nr_components = nir_src_num_components(instr->src[i].src);
2091 unsigned sz = nir_src_bit_size(instr->src[i].src);
2092 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
2093
2094 switch (instr->src[i].src_type) {
2095 case nir_tex_src_coord: {
2096 emit_explicit_constant(ctx, index, index);
2097
2098 unsigned coord_mask = mask_of(instr->coord_components);
2099
2100 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
2101
2102 if (flip_zw)
2103 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
2104
2105 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2106 /* texelFetch is undefined on samplerCube */
2107 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
2108
2109 /* For cubemaps, we use a special ld/st op to
2110 * select the face and copy the xy into the
2111 * texture register */
2112
2113 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
2114 ld.src[1] = index;
2115 ld.src_types[1] = T;
2116 ld.mask = 0x3; /* xy */
2117 ld.load_store.arg_1 = 0x20;
2118 ld.swizzle[1][3] = COMPONENT_X;
2119 emit_mir_instruction(ctx, ld);
2120
2121 /* xyzw -> xyxx */
2122 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
2123 ins.swizzle[1][3] = COMPONENT_X;
2124 } else if (needs_temp_coord) {
2125 /* mov coord_temp, coords */
2126 midgard_instruction mov = v_mov(index, coords);
2127 mov.mask = coord_mask;
2128
2129 if (flip_zw)
2130 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
2131
2132 emit_mir_instruction(ctx, mov);
2133 } else {
2134 coords = index;
2135 }
2136
2137 ins.src[1] = coords;
2138 ins.src_types[1] = T;
2139
2140 /* Texelfetch coordinates uses all four elements
2141 * (xyz/index) regardless of texture dimensionality,
2142 * which means it's necessary to zero the unused
2143 * components to keep everything happy */
2144
2145 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2146 /* mov index.zw, #0, or generalized */
2147 midgard_instruction mov =
2148 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
2149 mov.has_constants = true;
2150 mov.mask = coord_mask ^ 0xF;
2151 emit_mir_instruction(ctx, mov);
2152 }
2153
2154 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
2155 /* Array component in w but NIR wants it in z,
2156 * but if we have a temp coord we already fixed
2157 * that up */
2158
2159 if (nr_components == 3) {
2160 ins.swizzle[1][2] = COMPONENT_Z;
2161 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
2162 } else if (nr_components == 2) {
2163 ins.swizzle[1][2] =
2164 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
2165 ins.swizzle[1][3] = COMPONENT_X;
2166 } else
2167 unreachable("Invalid texture 2D components");
2168 }
2169
2170 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2171 /* We zeroed */
2172 ins.swizzle[1][2] = COMPONENT_Z;
2173 ins.swizzle[1][3] = COMPONENT_W;
2174 }
2175
2176 break;
2177 }
2178
2179 case nir_tex_src_bias:
2180 case nir_tex_src_lod: {
2181 /* Try as a constant if we can */
2182
2183 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2184 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2185 break;
2186
2187 ins.texture.lod_register = true;
2188 ins.src[2] = index;
2189 ins.src_types[2] = T;
2190
2191 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2192 ins.swizzle[2][c] = COMPONENT_X;
2193
2194 emit_explicit_constant(ctx, index, index);
2195
2196 break;
2197 };
2198
2199 case nir_tex_src_offset: {
2200 ins.texture.offset_register = true;
2201 ins.src[3] = index;
2202 ins.src_types[3] = T;
2203
2204 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2205 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2206
2207 emit_explicit_constant(ctx, index, index);
2208 break;
2209 };
2210
2211 case nir_tex_src_comparator:
2212 case nir_tex_src_ms_index: {
2213 unsigned comp = COMPONENT_Z;
2214
2215 /* mov coord_temp.foo, coords */
2216 midgard_instruction mov = v_mov(index, coords);
2217 mov.mask = 1 << comp;
2218
2219 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2220 mov.swizzle[1][i] = COMPONENT_X;
2221
2222 emit_mir_instruction(ctx, mov);
2223 break;
2224 }
2225
2226 default: {
2227 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2228 assert(0);
2229 }
2230 }
2231 }
2232
2233 emit_mir_instruction(ctx, ins);
2234 }
2235
2236 static void
2237 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2238 {
2239 switch (instr->op) {
2240 case nir_texop_tex:
2241 case nir_texop_txb:
2242 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2243 break;
2244 case nir_texop_txl:
2245 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2246 break;
2247 case nir_texop_txf:
2248 case nir_texop_txf_ms:
2249 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2250 break;
2251 case nir_texop_txs:
2252 emit_sysval_read(ctx, &instr->instr, 4, 0);
2253 break;
2254 default: {
2255 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2256 assert(0);
2257 }
2258 }
2259 }
2260
2261 static void
2262 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2263 {
2264 switch (instr->type) {
2265 case nir_jump_break: {
2266 /* Emit a branch out of the loop */
2267 struct midgard_instruction br = v_branch(false, false);
2268 br.branch.target_type = TARGET_BREAK;
2269 br.branch.target_break = ctx->current_loop_depth;
2270 emit_mir_instruction(ctx, br);
2271 break;
2272 }
2273
2274 default:
2275 DBG("Unknown jump type %d\n", instr->type);
2276 break;
2277 }
2278 }
2279
2280 static void
2281 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2282 {
2283 switch (instr->type) {
2284 case nir_instr_type_load_const:
2285 emit_load_const(ctx, nir_instr_as_load_const(instr));
2286 break;
2287
2288 case nir_instr_type_intrinsic:
2289 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2290 break;
2291
2292 case nir_instr_type_alu:
2293 emit_alu(ctx, nir_instr_as_alu(instr));
2294 break;
2295
2296 case nir_instr_type_tex:
2297 emit_tex(ctx, nir_instr_as_tex(instr));
2298 break;
2299
2300 case nir_instr_type_jump:
2301 emit_jump(ctx, nir_instr_as_jump(instr));
2302 break;
2303
2304 case nir_instr_type_ssa_undef:
2305 /* Spurious */
2306 break;
2307
2308 default:
2309 DBG("Unhandled instruction type\n");
2310 break;
2311 }
2312 }
2313
2314
2315 /* ALU instructions can inline or embed constants, which decreases register
2316 * pressure and saves space. */
2317
2318 #define CONDITIONAL_ATTACH(idx) { \
2319 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2320 \
2321 if (entry) { \
2322 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2323 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2324 } \
2325 }
2326
2327 static void
2328 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2329 {
2330 mir_foreach_instr_in_block(block, alu) {
2331 /* Other instructions cannot inline constants */
2332 if (alu->type != TAG_ALU_4) continue;
2333 if (alu->compact_branch) continue;
2334
2335 /* If there is already a constant here, we can do nothing */
2336 if (alu->has_constants) continue;
2337
2338 CONDITIONAL_ATTACH(0);
2339
2340 if (!alu->has_constants) {
2341 CONDITIONAL_ATTACH(1)
2342 } else if (!alu->inline_constant) {
2343 /* Corner case: _two_ vec4 constants, for instance with a
2344 * csel. For this case, we can only use a constant
2345 * register for one, we'll have to emit a move for the
2346 * other. */
2347
2348 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2349 unsigned scratch = make_compiler_temp(ctx);
2350
2351 if (entry) {
2352 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2353 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2354
2355 /* Set the source */
2356 alu->src[1] = scratch;
2357
2358 /* Inject us -before- the last instruction which set r31 */
2359 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2360 }
2361 }
2362 }
2363 }
2364
2365 unsigned
2366 max_bitsize_for_alu(midgard_instruction *ins)
2367 {
2368 unsigned max_bitsize = 0;
2369 for (int i = 0; i < MIR_SRC_COUNT; i++) {
2370 if (ins->src[i] == ~0) continue;
2371 unsigned src_bitsize = nir_alu_type_get_type_size(ins->src_types[i]);
2372 max_bitsize = MAX2(src_bitsize, max_bitsize);
2373 }
2374 unsigned dst_bitsize = nir_alu_type_get_type_size(ins->dest_type);
2375 max_bitsize = MAX2(dst_bitsize, max_bitsize);
2376
2377 /* We don't have fp16 LUTs, so we'll want to emit code like:
2378 *
2379 * vlut.fsinr hr0, hr0
2380 *
2381 * where both input and output are 16-bit but the operation is carried
2382 * out in 32-bit
2383 */
2384
2385 switch (ins->op) {
2386 case midgard_alu_op_fsqrt:
2387 case midgard_alu_op_frcp:
2388 case midgard_alu_op_frsqrt:
2389 case midgard_alu_op_fsin:
2390 case midgard_alu_op_fcos:
2391 case midgard_alu_op_fexp2:
2392 case midgard_alu_op_flog2:
2393 max_bitsize = MAX2(max_bitsize, 32);
2394 break;
2395
2396 default:
2397 break;
2398 }
2399
2400 return max_bitsize;
2401 }
2402
2403 midgard_reg_mode
2404 reg_mode_for_bitsize(unsigned bitsize)
2405 {
2406 switch (bitsize) {
2407 /* use 16 pipe for 8 since we don't support vec16 yet */
2408 case 8:
2409 case 16:
2410 return midgard_reg_mode_16;
2411 case 32:
2412 return midgard_reg_mode_32;
2413 case 64:
2414 return midgard_reg_mode_64;
2415 default:
2416 unreachable("invalid bit size");
2417 }
2418 }
2419
2420 /* Midgard supports two types of constants, embedded constants (128-bit) and
2421 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2422 * constants can be demoted to inline constants, for space savings and
2423 * sometimes a performance boost */
2424
2425 static void
2426 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2427 {
2428 mir_foreach_instr_in_block(block, ins) {
2429 if (!ins->has_constants) continue;
2430 if (ins->has_inline_constant) continue;
2431
2432 /* Blend constants must not be inlined by definition */
2433 if (ins->has_blend_constant) continue;
2434
2435 unsigned max_bitsize = max_bitsize_for_alu(ins);
2436
2437 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2438 bool is_16 = max_bitsize == 16;
2439 bool is_32 = max_bitsize == 32;
2440
2441 if (!(is_16 || is_32))
2442 continue;
2443
2444 /* src1 cannot be an inline constant due to encoding
2445 * restrictions. So, if possible we try to flip the arguments
2446 * in that case */
2447
2448 int op = ins->op;
2449
2450 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2451 alu_opcode_props[op].props & OP_COMMUTES) {
2452 mir_flip(ins);
2453 }
2454
2455 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2456 /* Component is from the swizzle. Take a nonzero component */
2457 assert(ins->mask);
2458 unsigned first_comp = ffs(ins->mask) - 1;
2459 unsigned component = ins->swizzle[1][first_comp];
2460
2461 /* Scale constant appropriately, if we can legally */
2462 int16_t scaled_constant = 0;
2463
2464 if (is_16) {
2465 scaled_constant = ins->constants.u16[component];
2466 } else if (midgard_is_integer_op(op)) {
2467 scaled_constant = ins->constants.u32[component];
2468
2469 /* Constant overflow after resize */
2470 if (scaled_constant != ins->constants.u32[component])
2471 continue;
2472 } else {
2473 float original = ins->constants.f32[component];
2474 scaled_constant = _mesa_float_to_half(original);
2475
2476 /* Check for loss of precision. If this is
2477 * mediump, we don't care, but for a highp
2478 * shader, we need to pay attention. NIR
2479 * doesn't yet tell us which mode we're in!
2480 * Practically this prevents most constants
2481 * from being inlined, sadly. */
2482
2483 float fp32 = _mesa_half_to_float(scaled_constant);
2484
2485 if (fp32 != original)
2486 continue;
2487 }
2488
2489 /* Should've been const folded */
2490 if (ins->src_abs[1] || ins->src_neg[1])
2491 continue;
2492
2493 /* Make sure that the constant is not itself a vector
2494 * by checking if all accessed values are the same. */
2495
2496 const midgard_constants *cons = &ins->constants;
2497 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2498
2499 bool is_vector = false;
2500 unsigned mask = effective_writemask(ins->op, ins->mask);
2501
2502 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2503 /* We only care if this component is actually used */
2504 if (!(mask & (1 << c)))
2505 continue;
2506
2507 uint32_t test = is_16 ?
2508 cons->u16[ins->swizzle[1][c]] :
2509 cons->u32[ins->swizzle[1][c]];
2510
2511 if (test != value) {
2512 is_vector = true;
2513 break;
2514 }
2515 }
2516
2517 if (is_vector)
2518 continue;
2519
2520 /* Get rid of the embedded constant */
2521 ins->has_constants = false;
2522 ins->src[1] = ~0;
2523 ins->has_inline_constant = true;
2524 ins->inline_constant = scaled_constant;
2525 }
2526 }
2527 }
2528
2529 /* Dead code elimination for branches at the end of a block - only one branch
2530 * per block is legal semantically */
2531
2532 static void
2533 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2534 {
2535 bool branched = false;
2536
2537 mir_foreach_instr_in_block_safe(block, ins) {
2538 if (!midgard_is_branch_unit(ins->unit)) continue;
2539
2540 if (branched)
2541 mir_remove_instruction(ins);
2542
2543 branched = true;
2544 }
2545 }
2546
2547 /* We want to force the invert on AND/OR to the second slot to legalize into
2548 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2549 *
2550 * ~a & #b = ~a & ~(#~b)
2551 * ~a & b = b & ~a
2552 */
2553
2554 static void
2555 midgard_legalize_invert(compiler_context *ctx, midgard_block *block)
2556 {
2557 mir_foreach_instr_in_block(block, ins) {
2558 if (ins->type != TAG_ALU_4) continue;
2559
2560 if (ins->op != midgard_alu_op_iand &&
2561 ins->op != midgard_alu_op_ior) continue;
2562
2563 if (ins->src_invert[1] || !ins->src_invert[0]) continue;
2564
2565 if (ins->has_inline_constant) {
2566 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2567 * inverts on */
2568 ins->inline_constant = ~ins->inline_constant;
2569 ins->src_invert[1] = true;
2570 } else {
2571 /* Flip to the right invert order. Note
2572 * has_inline_constant false by assumption on the
2573 * branch, so flipping makes sense. */
2574 mir_flip(ins);
2575 }
2576 }
2577 }
2578
2579 static unsigned
2580 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2581 {
2582 /* Loop to ourselves */
2583 midgard_instruction *br = ctx->writeout_branch[rt];
2584 struct midgard_instruction ins = v_branch(false, false);
2585 ins.writeout = br->writeout;
2586 ins.branch.target_block = ctx->block_count - 1;
2587 ins.constants.u32[0] = br->constants.u32[0];
2588 memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types));
2589 emit_mir_instruction(ctx, ins);
2590
2591 ctx->current_block->epilogue = true;
2592 schedule_barrier(ctx);
2593 return ins.branch.target_block;
2594 }
2595
2596 static midgard_block *
2597 emit_block_init(compiler_context *ctx)
2598 {
2599 midgard_block *this_block = ctx->after_block;
2600 ctx->after_block = NULL;
2601
2602 if (!this_block)
2603 this_block = create_empty_block(ctx);
2604
2605 list_addtail(&this_block->base.link, &ctx->blocks);
2606
2607 this_block->scheduled = false;
2608 ++ctx->block_count;
2609
2610 /* Set up current block */
2611 list_inithead(&this_block->base.instructions);
2612 ctx->current_block = this_block;
2613
2614 return this_block;
2615 }
2616
2617 static midgard_block *
2618 emit_block(compiler_context *ctx, nir_block *block)
2619 {
2620 midgard_block *this_block = emit_block_init(ctx);
2621
2622 nir_foreach_instr(instr, block) {
2623 emit_instr(ctx, instr);
2624 ++ctx->instruction_count;
2625 }
2626
2627 return this_block;
2628 }
2629
2630 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2631
2632 static void
2633 emit_if(struct compiler_context *ctx, nir_if *nif)
2634 {
2635 midgard_block *before_block = ctx->current_block;
2636
2637 /* Speculatively emit the branch, but we can't fill it in until later */
2638 bool inv = false;
2639 EMIT(branch, true, true);
2640 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2641 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2642 then_branch->src_types[0] = nir_type_uint32;
2643 then_branch->branch.invert_conditional = !inv;
2644
2645 /* Emit the two subblocks. */
2646 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2647 midgard_block *end_then_block = ctx->current_block;
2648
2649 /* Emit a jump from the end of the then block to the end of the else */
2650 EMIT(branch, false, false);
2651 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2652
2653 /* Emit second block, and check if it's empty */
2654
2655 int else_idx = ctx->block_count;
2656 int count_in = ctx->instruction_count;
2657 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2658 midgard_block *end_else_block = ctx->current_block;
2659 int after_else_idx = ctx->block_count;
2660
2661 /* Now that we have the subblocks emitted, fix up the branches */
2662
2663 assert(then_block);
2664 assert(else_block);
2665
2666 if (ctx->instruction_count == count_in) {
2667 /* The else block is empty, so don't emit an exit jump */
2668 mir_remove_instruction(then_exit);
2669 then_branch->branch.target_block = after_else_idx;
2670 } else {
2671 then_branch->branch.target_block = else_idx;
2672 then_exit->branch.target_block = after_else_idx;
2673 }
2674
2675 /* Wire up the successors */
2676
2677 ctx->after_block = create_empty_block(ctx);
2678
2679 pan_block_add_successor(&before_block->base, &then_block->base);
2680 pan_block_add_successor(&before_block->base, &else_block->base);
2681
2682 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2683 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2684 }
2685
2686 static void
2687 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2688 {
2689 /* Remember where we are */
2690 midgard_block *start_block = ctx->current_block;
2691
2692 /* Allocate a loop number, growing the current inner loop depth */
2693 int loop_idx = ++ctx->current_loop_depth;
2694
2695 /* Get index from before the body so we can loop back later */
2696 int start_idx = ctx->block_count;
2697
2698 /* Emit the body itself */
2699 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2700
2701 /* Branch back to loop back */
2702 struct midgard_instruction br_back = v_branch(false, false);
2703 br_back.branch.target_block = start_idx;
2704 emit_mir_instruction(ctx, br_back);
2705
2706 /* Mark down that branch in the graph. */
2707 pan_block_add_successor(&start_block->base, &loop_block->base);
2708 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2709
2710 /* Find the index of the block about to follow us (note: we don't add
2711 * one; blocks are 0-indexed so we get a fencepost problem) */
2712 int break_block_idx = ctx->block_count;
2713
2714 /* Fix up the break statements we emitted to point to the right place,
2715 * now that we can allocate a block number for them */
2716 ctx->after_block = create_empty_block(ctx);
2717
2718 mir_foreach_block_from(ctx, start_block, _block) {
2719 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2720 if (ins->type != TAG_ALU_4) continue;
2721 if (!ins->compact_branch) continue;
2722
2723 /* We found a branch -- check the type to see if we need to do anything */
2724 if (ins->branch.target_type != TARGET_BREAK) continue;
2725
2726 /* It's a break! Check if it's our break */
2727 if (ins->branch.target_break != loop_idx) continue;
2728
2729 /* Okay, cool, we're breaking out of this loop.
2730 * Rewrite from a break to a goto */
2731
2732 ins->branch.target_type = TARGET_GOTO;
2733 ins->branch.target_block = break_block_idx;
2734
2735 pan_block_add_successor(_block, &ctx->after_block->base);
2736 }
2737 }
2738
2739 /* Now that we've finished emitting the loop, free up the depth again
2740 * so we play nice with recursion amid nested loops */
2741 --ctx->current_loop_depth;
2742
2743 /* Dump loop stats */
2744 ++ctx->loop_count;
2745 }
2746
2747 static midgard_block *
2748 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2749 {
2750 midgard_block *start_block = NULL;
2751
2752 foreach_list_typed(nir_cf_node, node, node, list) {
2753 switch (node->type) {
2754 case nir_cf_node_block: {
2755 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2756
2757 if (!start_block)
2758 start_block = block;
2759
2760 break;
2761 }
2762
2763 case nir_cf_node_if:
2764 emit_if(ctx, nir_cf_node_as_if(node));
2765 break;
2766
2767 case nir_cf_node_loop:
2768 emit_loop(ctx, nir_cf_node_as_loop(node));
2769 break;
2770
2771 case nir_cf_node_function:
2772 assert(0);
2773 break;
2774 }
2775 }
2776
2777 return start_block;
2778 }
2779
2780 /* Due to lookahead, we need to report the first tag executed in the command
2781 * stream and in branch targets. An initial block might be empty, so iterate
2782 * until we find one that 'works' */
2783
2784 unsigned
2785 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2786 {
2787 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2788
2789 mir_foreach_block_from(ctx, initial_block, _v) {
2790 midgard_block *v = (midgard_block *) _v;
2791 if (v->quadword_count) {
2792 midgard_bundle *initial_bundle =
2793 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2794
2795 return initial_bundle->tag;
2796 }
2797 }
2798
2799 /* Default to a tag 1 which will break from the shader, in case we jump
2800 * to the exit block (i.e. `return` in a compute shader) */
2801
2802 return 1;
2803 }
2804
2805 /* For each fragment writeout instruction, generate a writeout loop to
2806 * associate with it */
2807
2808 static void
2809 mir_add_writeout_loops(compiler_context *ctx)
2810 {
2811 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2812 midgard_instruction *br = ctx->writeout_branch[rt];
2813 if (!br) continue;
2814
2815 unsigned popped = br->branch.target_block;
2816 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2817 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2818 br->branch.target_type = TARGET_GOTO;
2819
2820 /* If we have more RTs, we'll need to restore back after our
2821 * loop terminates */
2822
2823 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2824 midgard_instruction uncond = v_branch(false, false);
2825 uncond.branch.target_block = popped;
2826 uncond.branch.target_type = TARGET_GOTO;
2827 emit_mir_instruction(ctx, uncond);
2828 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2829 schedule_barrier(ctx);
2830 } else {
2831 /* We're last, so we can terminate here */
2832 br->last_writeout = true;
2833 }
2834 }
2835 }
2836
2837 int
2838 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb, bool silent)
2839 {
2840 struct util_dynarray *compiled = &program->compiled;
2841
2842 midgard_debug = debug_get_option_midgard_debug();
2843
2844 /* TODO: Bound against what? */
2845 compiler_context *ctx = rzalloc(NULL, compiler_context);
2846
2847 ctx->nir = nir;
2848 ctx->stage = nir->info.stage;
2849 ctx->is_blend = is_blend;
2850 ctx->alpha_ref = program->alpha_ref;
2851 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2852 ctx->blend_input = ~0;
2853 ctx->blend_src1 = ~0;
2854 ctx->quirks = midgard_get_quirks(gpu_id);
2855
2856 /* Start off with a safe cutoff, allowing usage of all 16 work
2857 * registers. Later, we'll promote uniform reads to uniform registers
2858 * if we determine it is beneficial to do so */
2859 ctx->uniform_cutoff = 8;
2860
2861 /* Initialize at a global (not block) level hash tables */
2862
2863 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2864 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2865
2866 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2867 * (so we don't accidentally duplicate the epilogue since mesa/st has
2868 * messed with our I/O quite a bit already) */
2869
2870 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2871
2872 if (ctx->stage == MESA_SHADER_VERTEX) {
2873 NIR_PASS_V(nir, nir_lower_viewport_transform);
2874 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2875 }
2876
2877 NIR_PASS_V(nir, nir_lower_var_copies);
2878 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2879 NIR_PASS_V(nir, nir_split_var_copies);
2880 NIR_PASS_V(nir, nir_lower_var_copies);
2881 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2882 NIR_PASS_V(nir, nir_lower_var_copies);
2883 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2884
2885 unsigned pan_quirks = panfrost_get_quirks(gpu_id);
2886 NIR_PASS_V(nir, pan_lower_framebuffer,
2887 program->rt_formats, is_blend, pan_quirks);
2888
2889 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
2890 glsl_type_size, 0);
2891 NIR_PASS_V(nir, nir_lower_ssbo);
2892 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2893
2894 /* Optimisation passes */
2895
2896 optimise_nir(nir, ctx->quirks, is_blend);
2897
2898 NIR_PASS_V(nir, midgard_nir_reorder_writeout);
2899
2900 if ((midgard_debug & MIDGARD_DBG_SHADERS) && !silent) {
2901 nir_print_shader(nir, stdout);
2902 }
2903
2904 /* Assign sysvals and counts, now that we're sure
2905 * (post-optimisation) */
2906
2907 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2908 program->sysval_count = ctx->sysvals.sysval_count;
2909 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2910
2911 nir_foreach_function(func, nir) {
2912 if (!func->impl)
2913 continue;
2914
2915 list_inithead(&ctx->blocks);
2916 ctx->block_count = 0;
2917 ctx->func = func;
2918 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2919
2920 if (nir->info.outputs_read && !is_blend) {
2921 emit_block_init(ctx);
2922
2923 struct midgard_instruction wait = v_branch(false, false);
2924 wait.branch.target_type = TARGET_TILEBUF_WAIT;
2925
2926 emit_mir_instruction(ctx, wait);
2927
2928 ++ctx->instruction_count;
2929 }
2930
2931 emit_cf_list(ctx, &func->impl->body);
2932 free(ctx->already_emitted);
2933 break; /* TODO: Multi-function shaders */
2934 }
2935
2936 util_dynarray_init(compiled, NULL);
2937
2938 /* Per-block lowering before opts */
2939
2940 mir_foreach_block(ctx, _block) {
2941 midgard_block *block = (midgard_block *) _block;
2942 inline_alu_constants(ctx, block);
2943 embedded_to_inline_constant(ctx, block);
2944 }
2945 /* MIR-level optimizations */
2946
2947 bool progress = false;
2948
2949 do {
2950 progress = false;
2951 progress |= midgard_opt_dead_code_eliminate(ctx);
2952
2953 mir_foreach_block(ctx, _block) {
2954 midgard_block *block = (midgard_block *) _block;
2955 progress |= midgard_opt_copy_prop(ctx, block);
2956 progress |= midgard_opt_combine_projection(ctx, block);
2957 progress |= midgard_opt_varying_projection(ctx, block);
2958 }
2959 } while (progress);
2960
2961 mir_foreach_block(ctx, _block) {
2962 midgard_block *block = (midgard_block *) _block;
2963 midgard_lower_derivatives(ctx, block);
2964 midgard_legalize_invert(ctx, block);
2965 midgard_cull_dead_branch(ctx, block);
2966 }
2967
2968 if (ctx->stage == MESA_SHADER_FRAGMENT)
2969 mir_add_writeout_loops(ctx);
2970
2971 /* Analyze now that the code is known but before scheduling creates
2972 * pipeline registers which are harder to track */
2973 mir_analyze_helper_terminate(ctx);
2974 mir_analyze_helper_requirements(ctx);
2975
2976 /* Schedule! */
2977 midgard_schedule_program(ctx);
2978 mir_ra(ctx);
2979
2980 /* Emit flat binary from the instruction arrays. Iterate each block in
2981 * sequence. Save instruction boundaries such that lookahead tags can
2982 * be assigned easily */
2983
2984 /* Cache _all_ bundles in source order for lookahead across failed branches */
2985
2986 int bundle_count = 0;
2987 mir_foreach_block(ctx, _block) {
2988 midgard_block *block = (midgard_block *) _block;
2989 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2990 }
2991 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2992 int bundle_idx = 0;
2993 mir_foreach_block(ctx, _block) {
2994 midgard_block *block = (midgard_block *) _block;
2995 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2996 source_order_bundles[bundle_idx++] = bundle;
2997 }
2998 }
2999
3000 int current_bundle = 0;
3001
3002 /* Midgard prefetches instruction types, so during emission we
3003 * need to lookahead. Unless this is the last instruction, in
3004 * which we return 1. */
3005
3006 mir_foreach_block(ctx, _block) {
3007 midgard_block *block = (midgard_block *) _block;
3008 mir_foreach_bundle_in_block(block, bundle) {
3009 int lookahead = 1;
3010
3011 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
3012 lookahead = source_order_bundles[current_bundle + 1]->tag;
3013
3014 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
3015 ++current_bundle;
3016 }
3017
3018 /* TODO: Free deeper */
3019 //util_dynarray_fini(&block->instructions);
3020 }
3021
3022 free(source_order_bundles);
3023
3024 /* Report the very first tag executed */
3025 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
3026
3027 /* Deal with off-by-one related to the fencepost problem */
3028 program->work_register_count = ctx->work_registers + 1;
3029 program->uniform_cutoff = ctx->uniform_cutoff;
3030
3031 program->blend_patch_offset = ctx->blend_constant_offset;
3032 program->tls_size = ctx->tls_size;
3033
3034 if ((midgard_debug & MIDGARD_DBG_SHADERS) && !silent)
3035 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
3036
3037 if ((midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) && !silent) {
3038 unsigned nr_bundles = 0, nr_ins = 0;
3039
3040 /* Count instructions and bundles */
3041
3042 mir_foreach_block(ctx, _block) {
3043 midgard_block *block = (midgard_block *) _block;
3044 nr_bundles += util_dynarray_num_elements(
3045 &block->bundles, midgard_bundle);
3046
3047 mir_foreach_bundle_in_block(block, bun)
3048 nr_ins += bun->instruction_count;
3049 }
3050
3051 /* Calculate thread count. There are certain cutoffs by
3052 * register count for thread count */
3053
3054 unsigned nr_registers = program->work_register_count;
3055
3056 unsigned nr_threads =
3057 (nr_registers <= 4) ? 4 :
3058 (nr_registers <= 8) ? 2 :
3059 1;
3060
3061 /* Dump stats */
3062
3063 fprintf(stderr, "shader%d - %s shader: "
3064 "%u inst, %u bundles, %u quadwords, "
3065 "%u registers, %u threads, %u loops, "
3066 "%u:%u spills:fills\n",
3067 SHADER_DB_COUNT++,
3068 ctx->is_blend ? "PAN_SHADER_BLEND" :
3069 gl_shader_stage_name(ctx->stage),
3070 nr_ins, nr_bundles, ctx->quadword_count,
3071 nr_registers, nr_threads,
3072 ctx->loop_count,
3073 ctx->spills, ctx->fills);
3074 }
3075
3076 ralloc_free(ctx);
3077
3078 return 0;
3079 }