2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
51 #include "midgard_quirks.h"
53 #include "disassemble.h"
55 static const struct debug_named_value debug_options
[] = {
56 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
64 unsigned SHADER_DB_COUNT
= 0;
66 int midgard_debug
= 0;
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72 static midgard_block
*
73 create_empty_block(compiler_context
*ctx
)
75 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
77 blk
->predecessors
= _mesa_set_create(blk
,
79 _mesa_key_pointer_equal
);
81 blk
->source_id
= ctx
->block_source_count
++;
87 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
93 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
94 if (block
->successors
[i
] == successor
)
98 block
->successors
[block
->nr_successors
++] = successor
;
99 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
101 /* Note the predecessor in the other direction */
102 _mesa_set_add(successor
->predecessors
, block
);
106 schedule_barrier(compiler_context
*ctx
)
108 midgard_block
*temp
= ctx
->after_block
;
109 ctx
->after_block
= create_empty_block(ctx
);
111 list_addtail(&ctx
->after_block
->link
, &ctx
->blocks
);
112 list_inithead(&ctx
->after_block
->instructions
);
113 midgard_block_add_successor(ctx
->current_block
, ctx
->after_block
);
114 ctx
->current_block
= ctx
->after_block
;
115 ctx
->after_block
= temp
;
118 /* Helpers to generate midgard_instruction's using macro magic, since every
119 * driver seems to do it that way */
121 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
123 #define M_LOAD_STORE(name, store) \
124 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
125 midgard_instruction i = { \
126 .type = TAG_LOAD_STORE_4, \
129 .src = { ~0, ~0, ~0, ~0 }, \
130 .swizzle = SWIZZLE_IDENTITY_4, \
132 .op = midgard_op_##name, \
145 #define M_LOAD(name) M_LOAD_STORE(name, false)
146 #define M_STORE(name) M_LOAD_STORE(name, true)
148 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
149 * the corresponding Midgard source */
151 static midgard_vector_alu_src
152 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
153 bool half
, bool sext
)
155 /* Figure out how many components there are so we can adjust.
156 * Specifically we want to broadcast the last channel so things like
160 if (broadcast_count
&& src
) {
161 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
163 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
164 src
->swizzle
[c
] = last_component
;
168 midgard_vector_alu_src alu_src
= {
175 alu_src
.mod
= midgard_int_normal
;
177 /* Sign/zero-extend if needed */
181 midgard_int_sign_extend
182 : midgard_int_zero_extend
;
185 /* These should have been lowered away */
187 assert(!(src
->abs
|| src
->negate
));
190 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
196 /* load/store instructions have both 32-bit and 16-bit variants, depending on
197 * whether we are using vectors composed of highp or mediump. At the moment, we
198 * don't support half-floats -- this requires changes in other parts of the
199 * compiler -- therefore the 16-bit versions are commented out. */
201 //M_LOAD(ld_attr_16);
203 //M_LOAD(ld_vary_16);
208 M_LOAD(ld_color_buffer_32u
);
209 //M_STORE(st_vary_16);
211 M_LOAD(ld_cubemap_coords
);
212 M_LOAD(ld_compute_id
);
214 static midgard_instruction
215 v_branch(bool conditional
, bool invert
)
217 midgard_instruction ins
= {
219 .unit
= ALU_ENAB_BRANCH
,
220 .compact_branch
= true,
222 .conditional
= conditional
,
223 .invert_conditional
= invert
226 .src
= { ~0, ~0, ~0, ~0 },
232 static midgard_branch_extended
233 midgard_create_branch_extended( midgard_condition cond
,
234 midgard_jmp_writeout_op op
,
236 signed quadword_offset
)
238 /* The condition code is actually a LUT describing a function to
239 * combine multiple condition codes. However, we only support a single
240 * condition code at the moment, so we just duplicate over a bunch of
243 uint16_t duplicated_cond
=
253 midgard_branch_extended branch
= {
255 .dest_tag
= dest_tag
,
256 .offset
= quadword_offset
,
257 .cond
= duplicated_cond
264 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
266 ins
->has_constants
= true;
267 memcpy(&ins
->constants
, constants
, 16);
271 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
273 return glsl_count_attribute_slots(type
, false);
276 /* Lower fdot2 to a vector multiplication followed by channel addition */
278 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
280 if (alu
->op
!= nir_op_fdot2
)
283 b
->cursor
= nir_before_instr(&alu
->instr
);
285 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
286 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
288 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
290 nir_ssa_def
*sum
= nir_fadd(b
,
291 nir_channel(b
, product
, 0),
292 nir_channel(b
, product
, 1));
294 /* Replace the fdot2 with this sum */
295 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
299 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
301 /* This is way too meta */
302 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
303 unsigned idx_idx
= is_store
? 1 : 0;
305 nir_src index
= instr
->src
[idx_idx
];
306 assert(nir_src_is_const(index
));
307 uint32_t uindex
= nir_src_as_uint(index
);
309 return PAN_SYSVAL(SSBO
, uindex
);
313 midgard_sysval_for_sampler(nir_intrinsic_instr
*instr
)
315 /* TODO: indirect samplers !!! */
316 nir_src index
= instr
->src
[0];
317 assert(nir_src_is_const(index
));
318 uint32_t uindex
= nir_src_as_uint(index
);
320 return PAN_SYSVAL(SAMPLER
, uindex
);
324 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
326 switch (instr
->intrinsic
) {
327 case nir_intrinsic_load_viewport_scale
:
328 return PAN_SYSVAL_VIEWPORT_SCALE
;
329 case nir_intrinsic_load_viewport_offset
:
330 return PAN_SYSVAL_VIEWPORT_OFFSET
;
331 case nir_intrinsic_load_num_work_groups
:
332 return PAN_SYSVAL_NUM_WORK_GROUPS
;
333 case nir_intrinsic_load_ssbo
:
334 case nir_intrinsic_store_ssbo
:
335 return midgard_sysval_for_ssbo(instr
);
336 case nir_intrinsic_load_sampler_lod_parameters_pan
:
337 return midgard_sysval_for_sampler(instr
);
343 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
346 nir_intrinsic_instr
*intr
;
347 nir_dest
*dst
= NULL
;
351 bool is_store
= false;
353 switch (instr
->type
) {
354 case nir_instr_type_intrinsic
:
355 intr
= nir_instr_as_intrinsic(instr
);
356 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
358 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
360 case nir_instr_type_tex
:
361 tex
= nir_instr_as_tex(instr
);
362 if (tex
->op
!= nir_texop_txs
)
365 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
366 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
367 nir_tex_instr_dest_size(tex
) -
368 (tex
->is_array
? 1 : 0),
376 if (dest
&& dst
&& !is_store
)
377 *dest
= nir_dest_index(ctx
, dst
);
383 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
387 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
391 /* We have a sysval load; check if it's already been assigned */
393 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
396 /* It hasn't -- so assign it now! */
398 unsigned id
= ctx
->sysval_count
++;
399 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
400 ctx
->sysvals
[id
] = sysval
;
404 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
406 ctx
->sysval_count
= 0;
408 nir_foreach_function(function
, shader
) {
409 if (!function
->impl
) continue;
411 nir_foreach_block(block
, function
->impl
) {
412 nir_foreach_instr_safe(instr
, block
) {
413 midgard_nir_assign_sysval_body(ctx
, instr
);
420 midgard_nir_lower_fdot2(nir_shader
*shader
)
422 bool progress
= false;
424 nir_foreach_function(function
, shader
) {
425 if (!function
->impl
) continue;
428 nir_builder
*b
= &_b
;
429 nir_builder_init(b
, function
->impl
);
431 nir_foreach_block(block
, function
->impl
) {
432 nir_foreach_instr_safe(instr
, block
) {
433 if (instr
->type
!= nir_instr_type_alu
) continue;
435 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
436 midgard_nir_lower_fdot2_body(b
, alu
);
442 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
449 /* Flushes undefined values to zero */
452 optimise_nir(nir_shader
*nir
, unsigned quirks
)
455 unsigned lower_flrp
=
456 (nir
->options
->lower_flrp16
? 16 : 0) |
457 (nir
->options
->lower_flrp32
? 32 : 0) |
458 (nir
->options
->lower_flrp64
? 64 : 0);
460 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
461 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
463 nir_lower_tex_options lower_tex_options
= {
464 .lower_txs_lod
= true,
466 .lower_tex_without_implicit_lod
=
467 (quirks
& MIDGARD_EXPLICIT_LOD
),
469 /* TODO: we have native gradient.. */
473 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
475 /* Must lower fdot2 after tex is lowered */
476 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
478 /* T720 is broken. */
480 if (quirks
& MIDGARD_BROKEN_LOD
)
481 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
486 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
487 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
489 NIR_PASS(progress
, nir
, nir_copy_prop
);
490 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
491 NIR_PASS(progress
, nir
, nir_opt_dce
);
492 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
493 NIR_PASS(progress
, nir
, nir_opt_cse
);
494 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
495 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
496 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
498 if (lower_flrp
!= 0) {
499 bool lower_flrp_progress
= false;
500 NIR_PASS(lower_flrp_progress
,
504 false /* always_precise */,
505 nir
->options
->lower_ffma
);
506 if (lower_flrp_progress
) {
507 NIR_PASS(progress
, nir
,
508 nir_opt_constant_folding
);
512 /* Nothing should rematerialize any flrps, so we only
513 * need to do this lowering once.
518 NIR_PASS(progress
, nir
, nir_opt_undef
);
519 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
521 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
524 nir_var_function_temp
);
526 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
529 /* Must be run at the end to prevent creation of fsin/fcos ops */
530 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
535 NIR_PASS(progress
, nir
, nir_opt_dce
);
536 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
537 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
538 NIR_PASS(progress
, nir
, nir_copy_prop
);
541 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
543 /* We implement booleans as 32-bit 0/~0 */
544 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
546 /* Now that booleans are lowered, we can run out late opts */
547 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
549 /* Lower mods for float ops only. Integer ops don't support modifiers
550 * (saturate doesn't make sense on integers, neg/abs require dedicated
553 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
554 NIR_PASS(progress
, nir
, nir_copy_prop
);
555 NIR_PASS(progress
, nir
, nir_opt_dce
);
557 /* Take us out of SSA */
558 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
559 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
561 /* We are a vector architecture; write combine where possible */
562 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
563 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
565 NIR_PASS(progress
, nir
, nir_opt_dce
);
568 /* Do not actually emit a load; instead, cache the constant for inlining */
571 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
573 nir_ssa_def def
= instr
->def
;
575 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
577 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
579 #define RAW_CONST_COPY(bits) \
580 nir_const_value_to_array(consts->u##bits, instr->value, \
581 instr->def.num_components, u##bits)
583 switch (instr
->def
.bit_size
) {
597 unreachable("Invalid bit_size for load_const instruction\n");
600 /* Shifted for SSA, +1 for off-by-one */
601 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
604 /* Normally constants are embedded implicitly, but for I/O and such we have to
605 * explicitly emit a move with the constant source */
608 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
610 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
612 if (constant_value
) {
613 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
614 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
615 emit_mir_instruction(ctx
, ins
);
620 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
622 unsigned comp
= src
->swizzle
[0];
624 for (unsigned c
= 1; c
< nr_components
; ++c
) {
625 if (src
->swizzle
[c
] != comp
)
632 #define ALU_CASE(nir, _op) \
634 op = midgard_alu_op_##_op; \
635 assert(src_bitsize == dst_bitsize); \
638 #define ALU_CASE_BCAST(nir, _op, count) \
640 op = midgard_alu_op_##_op; \
641 broadcast_swizzle = count; \
642 assert(src_bitsize == dst_bitsize); \
645 nir_is_fzero_constant(nir_src src
)
647 if (!nir_src_is_const(src
))
650 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
651 if (nir_src_comp_as_float(src
, c
) != 0.0)
658 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
659 * special treatment override this anyway. */
661 static midgard_reg_mode
662 reg_mode_for_nir(nir_alu_instr
*instr
)
664 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
666 switch (src_bitsize
) {
668 return midgard_reg_mode_8
;
670 return midgard_reg_mode_16
;
672 return midgard_reg_mode_32
;
674 return midgard_reg_mode_64
;
676 unreachable("Invalid bit size");
681 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
683 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
684 * is handled elsewhere */
686 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
687 midgard_emit_derivatives(ctx
, instr
);
691 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
693 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
694 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
695 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
697 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
698 * supported. A few do not and are commented for now. Also, there are a
699 * number of NIR ops which Midgard does not support and need to be
700 * lowered, also TODO. This switch block emits the opcode and calling
701 * convention of the Midgard instruction; actual packing is done in
706 /* Number of components valid to check for the instruction (the rest
707 * will be forced to the last), or 0 to use as-is. Relevant as
708 * ball-type instructions have a channel count in NIR but are all vec4
711 unsigned broadcast_swizzle
= 0;
713 /* What register mode should we operate in? */
714 midgard_reg_mode reg_mode
=
715 reg_mode_for_nir(instr
);
717 /* Do we need a destination override? Used for inline
720 midgard_dest_override dest_override
=
721 midgard_dest_override_none
;
723 /* Should we use a smaller respective source and sign-extend? */
725 bool half_1
= false, sext_1
= false;
726 bool half_2
= false, sext_2
= false;
728 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
729 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
732 ALU_CASE(fadd
, fadd
);
733 ALU_CASE(fmul
, fmul
);
734 ALU_CASE(fmin
, fmin
);
735 ALU_CASE(fmax
, fmax
);
736 ALU_CASE(imin
, imin
);
737 ALU_CASE(imax
, imax
);
738 ALU_CASE(umin
, umin
);
739 ALU_CASE(umax
, umax
);
740 ALU_CASE(ffloor
, ffloor
);
741 ALU_CASE(fround_even
, froundeven
);
742 ALU_CASE(ftrunc
, ftrunc
);
743 ALU_CASE(fceil
, fceil
);
744 ALU_CASE(fdot3
, fdot3
);
745 ALU_CASE(fdot4
, fdot4
);
746 ALU_CASE(iadd
, iadd
);
747 ALU_CASE(isub
, isub
);
748 ALU_CASE(imul
, imul
);
750 /* Zero shoved as second-arg */
751 ALU_CASE(iabs
, iabsdiff
);
755 ALU_CASE(feq32
, feq
);
756 ALU_CASE(fne32
, fne
);
757 ALU_CASE(flt32
, flt
);
758 ALU_CASE(ieq32
, ieq
);
759 ALU_CASE(ine32
, ine
);
760 ALU_CASE(ilt32
, ilt
);
761 ALU_CASE(ult32
, ult
);
763 /* We don't have a native b2f32 instruction. Instead, like many
764 * GPUs, we exploit booleans as 0/~0 for false/true, and
765 * correspondingly AND
766 * by 1.0 to do the type conversion. For the moment, prime us
769 * iand [whatever], #0
771 * At the end of emit_alu (as MIR), we'll fix-up the constant
774 ALU_CASE(b2f32
, iand
);
775 ALU_CASE(b2i32
, iand
);
777 /* Likewise, we don't have a dedicated f2b32 instruction, but
778 * we can do a "not equal to 0.0" test. */
780 ALU_CASE(f2b32
, fne
);
781 ALU_CASE(i2b32
, ine
);
783 ALU_CASE(frcp
, frcp
);
784 ALU_CASE(frsq
, frsqrt
);
785 ALU_CASE(fsqrt
, fsqrt
);
786 ALU_CASE(fexp2
, fexp2
);
787 ALU_CASE(flog2
, flog2
);
789 ALU_CASE(f2i64
, f2i_rtz
);
790 ALU_CASE(f2u64
, f2u_rtz
);
791 ALU_CASE(i2f64
, i2f_rtz
);
792 ALU_CASE(u2f64
, u2f_rtz
);
794 ALU_CASE(f2i32
, f2i_rtz
);
795 ALU_CASE(f2u32
, f2u_rtz
);
796 ALU_CASE(i2f32
, i2f_rtz
);
797 ALU_CASE(u2f32
, u2f_rtz
);
799 ALU_CASE(f2i16
, f2i_rtz
);
800 ALU_CASE(f2u16
, f2u_rtz
);
801 ALU_CASE(i2f16
, i2f_rtz
);
802 ALU_CASE(u2f16
, u2f_rtz
);
804 ALU_CASE(fsin
, fsin
);
805 ALU_CASE(fcos
, fcos
);
807 /* We'll set invert */
808 ALU_CASE(inot
, imov
);
809 ALU_CASE(iand
, iand
);
811 ALU_CASE(ixor
, ixor
);
812 ALU_CASE(ishl
, ishl
);
813 ALU_CASE(ishr
, iasr
);
814 ALU_CASE(ushr
, ilsr
);
816 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
817 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
818 ALU_CASE(b32all_fequal4
, fball_eq
);
820 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
821 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
822 ALU_CASE(b32any_fnequal4
, fbany_neq
);
824 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
825 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
826 ALU_CASE(b32all_iequal4
, iball_eq
);
828 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
829 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
830 ALU_CASE(b32any_inequal4
, ibany_neq
);
832 /* Source mods will be shoved in later */
833 ALU_CASE(fabs
, fmov
);
834 ALU_CASE(fneg
, fmov
);
835 ALU_CASE(fsat
, fmov
);
837 /* For size conversion, we use a move. Ideally though we would squash
838 * these ops together; maybe that has to happen after in NIR as part of
839 * propagation...? An earlier algebraic pass ensured we step down by
840 * only / exactly one size. If stepping down, we use a dest override to
841 * reduce the size; if stepping up, we use a larger-sized move with a
842 * half source and a sign/zero-extension modifier */
848 /* If we end up upscale, we'll need a sign-extend on the
849 * operand (the second argument) */
860 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
861 instr
->op
== nir_op_f2f64
)
862 op
= midgard_alu_op_fmov
;
864 op
= midgard_alu_op_imov
;
866 if (dst_bitsize
== (src_bitsize
* 2)) {
870 /* Use a greater register mode */
872 } else if (src_bitsize
== (dst_bitsize
* 2)) {
873 /* Converting down */
874 dest_override
= midgard_dest_override_lower
;
880 /* For greater-or-equal, we lower to less-or-equal and flip the
888 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
889 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
890 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
891 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
894 /* Swap via temporary */
895 nir_alu_src temp
= instr
->src
[1];
896 instr
->src
[1] = instr
->src
[0];
897 instr
->src
[0] = temp
;
902 case nir_op_b32csel
: {
903 /* Midgard features both fcsel and icsel, depending on
904 * the type of the arguments/output. However, as long
905 * as we're careful we can _always_ use icsel and
906 * _never_ need fcsel, since the latter does additional
907 * floating-point-specific processing whereas the
908 * former just moves bits on the wire. It's not obvious
909 * why these are separate opcodes, save for the ability
910 * to do things like sat/pos/abs/neg for free */
912 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
913 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
915 /* The condition is the first argument; move the other
916 * arguments up one to be a binary instruction for
917 * Midgard with the condition last */
919 nir_alu_src temp
= instr
->src
[2];
921 instr
->src
[2] = instr
->src
[0];
922 instr
->src
[0] = instr
->src
[1];
923 instr
->src
[1] = temp
;
929 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
934 /* Midgard can perform certain modifiers on output of an ALU op */
937 if (midgard_is_integer_out_op(op
)) {
938 outmod
= midgard_outmod_int_wrap
;
940 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
941 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
944 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
946 if (instr
->op
== nir_op_fmax
) {
947 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
948 op
= midgard_alu_op_fmov
;
950 outmod
= midgard_outmod_pos
;
951 instr
->src
[0] = instr
->src
[1];
952 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
953 op
= midgard_alu_op_fmov
;
955 outmod
= midgard_outmod_pos
;
959 /* Fetch unit, quirks, etc information */
960 unsigned opcode_props
= alu_opcode_props
[op
].props
;
961 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
963 /* src0 will always exist afaik, but src1 will not for 1-argument
964 * instructions. The latter can only be fetched if the instruction
965 * needs it, or else we may segfault. */
967 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
968 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
969 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
970 assert(nr_inputs
<= 3);
972 /* Rather than use the instruction generation helpers, we do it
973 * ourselves here to avoid the mess */
975 midgard_instruction ins
= {
978 quirk_flipped_r24
? ~0 : src0
,
979 quirk_flipped_r24
? src0
: src1
,
986 nir_alu_src
*nirmods
[3] = { NULL
};
988 if (nr_inputs
>= 2) {
989 nirmods
[0] = &instr
->src
[0];
990 nirmods
[1] = &instr
->src
[1];
991 } else if (nr_inputs
== 1) {
992 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
998 nirmods
[2] = &instr
->src
[2];
1000 /* These were lowered to a move, so apply the corresponding mod */
1002 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1003 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1005 if (instr
->op
== nir_op_fneg
)
1006 s
->negate
= !s
->negate
;
1008 if (instr
->op
== nir_op_fabs
)
1012 bool is_int
= midgard_is_integer_op(op
);
1014 ins
.mask
= mask_of(nr_components
);
1016 midgard_vector_alu alu
= {
1018 .reg_mode
= reg_mode
,
1019 .dest_override
= dest_override
,
1022 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1023 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1026 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1029 ins
.mask
&= instr
->dest
.write_mask
;
1031 for (unsigned m
= 0; m
< 3; ++m
) {
1035 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
1036 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
1038 /* Replicate. TODO: remove when vec16 lands */
1039 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
1040 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
1043 if (nr_inputs
== 3) {
1044 /* Conditions can't have mods */
1045 assert(!nirmods
[2]->abs
);
1046 assert(!nirmods
[2]->negate
);
1051 /* Late fixup for emulated instructions */
1053 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1054 /* Presently, our second argument is an inline #0 constant.
1055 * Switch over to an embedded 1.0 constant (that can't fit
1056 * inline, since we're 32-bit, not 16-bit like the inline
1059 ins
.has_inline_constant
= false;
1060 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1061 ins
.has_constants
= true;
1063 if (instr
->op
== nir_op_b2f32
)
1064 ins
.constants
.f32
[0] = 1.0f
;
1066 ins
.constants
.i32
[0] = 1;
1068 for (unsigned c
= 0; c
< 16; ++c
)
1069 ins
.swizzle
[1][c
] = 0;
1070 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1071 /* Lots of instructions need a 0 plonked in */
1072 ins
.has_inline_constant
= false;
1073 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1074 ins
.has_constants
= true;
1075 ins
.constants
.u32
[0] = 0;
1077 for (unsigned c
= 0; c
< 16; ++c
)
1078 ins
.swizzle
[1][c
] = 0;
1079 } else if (instr
->op
== nir_op_inot
) {
1083 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1084 /* To avoid duplicating the lookup tables (probably), true LUT
1085 * instructions can only operate as if they were scalars. Lower
1086 * them here by changing the component. */
1088 unsigned orig_mask
= ins
.mask
;
1090 for (int i
= 0; i
< nr_components
; ++i
) {
1091 /* Mask the associated component, dropping the
1092 * instruction if needed */
1095 ins
.mask
&= orig_mask
;
1100 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1101 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1103 emit_mir_instruction(ctx
, ins
);
1106 emit_mir_instruction(ctx
, ins
);
1113 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1115 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1116 unsigned nir_mask
= 0;
1120 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1121 dsize
= nir_dest_bit_size(intr
->dest
);
1123 nir_mask
= nir_intrinsic_write_mask(intr
);
1127 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1128 unsigned bytemask
= mir_to_bytemask(mir_mode_for_destsize(dsize
), nir_mask
);
1129 mir_set_bytemask(ins
, bytemask
);
1132 ins
->load_64
= true;
1135 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1136 * optimized) versions of UBO #0 */
1138 static midgard_instruction
*
1140 compiler_context
*ctx
,
1144 nir_src
*indirect_offset
,
1145 unsigned indirect_shift
,
1148 /* TODO: half-floats */
1150 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1151 ins
.constants
.u32
[0] = offset
;
1153 if (instr
->type
== nir_instr_type_intrinsic
)
1154 mir_set_intr_mask(instr
, &ins
, true);
1156 if (indirect_offset
) {
1157 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1158 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1160 ins
.load_store
.arg_2
= 0x1E;
1163 ins
.load_store
.arg_1
= index
;
1165 return emit_mir_instruction(ctx
, ins
);
1168 /* SSBO reads are like UBO reads if you squint */
1172 compiler_context
*ctx
,
1177 nir_src
*indirect_offset
,
1182 midgard_instruction ins
;
1185 ins
= m_ld_int4(srcdest
, offset
);
1187 ins
= m_st_int4(srcdest
, offset
);
1189 /* SSBO reads use a generic memory read interface, so we need the
1190 * address of the SSBO as the first argument. This is a sysval. */
1192 unsigned addr
= make_compiler_temp(ctx
);
1193 emit_sysval_read(ctx
, instr
, addr
, 2);
1195 /* The source array:
1197 * src[0] = store ? value : unused
1201 * We would like arg_1 = the address and
1202 * arg_2 = the offset.
1207 /* TODO: What is this? It looks superficially like a shift << 5, but
1208 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1209 * indirect offset. */
1211 if (indirect_offset
) {
1212 ins
.load_store
.arg_1
|= 0xE0;
1213 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1215 ins
.load_store
.arg_2
= 0x7E;
1218 /* TODO: Bounds check */
1220 /* Finally, we emit the direct offset */
1222 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1223 ins
.load_store
.address
= (offset
>> 9);
1224 mir_set_intr_mask(instr
, &ins
, is_read
);
1226 emit_mir_instruction(ctx
, ins
);
1231 compiler_context
*ctx
,
1232 unsigned dest
, unsigned offset
,
1233 unsigned nr_comp
, unsigned component
,
1234 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1236 /* XXX: Half-floats? */
1237 /* TODO: swizzle, mask */
1239 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1240 ins
.mask
= mask_of(nr_comp
);
1242 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1243 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1245 midgard_varying_parameter p
= {
1247 .interpolation
= midgard_interp_default
,
1252 memcpy(&u
, &p
, sizeof(p
));
1253 ins
.load_store
.varying_parameters
= u
;
1255 if (indirect_offset
)
1256 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1258 ins
.load_store
.arg_2
= 0x1E;
1260 ins
.load_store
.arg_1
= 0x9E;
1262 /* Use the type appropriate load */
1266 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1269 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1271 case nir_type_float
:
1272 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1275 unreachable("Attempted to load unknown type");
1279 emit_mir_instruction(ctx
, ins
);
1284 compiler_context
*ctx
,
1285 unsigned dest
, unsigned offset
,
1286 unsigned nr_comp
, nir_alu_type t
)
1288 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1289 ins
.load_store
.arg_1
= 0x1E;
1290 ins
.load_store
.arg_2
= 0x1E;
1291 ins
.mask
= mask_of(nr_comp
);
1293 /* Use the type appropriate load */
1297 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1300 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1302 case nir_type_float
:
1303 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1306 unreachable("Attempted to load unknown type");
1310 emit_mir_instruction(ctx
, ins
);
1314 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1315 unsigned nr_components
)
1319 /* Figure out which uniform this is */
1320 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1321 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1323 if (dest_override
>= 0)
1324 dest
= dest_override
;
1326 /* Sysvals are prefix uniforms */
1327 unsigned uniform
= ((uintptr_t) val
) - 1;
1329 /* Emit the read itself -- this is never indirect */
1330 midgard_instruction
*ins
=
1331 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0, 0);
1333 ins
->mask
= mask_of(nr_components
);
1337 compute_builtin_arg(nir_op op
)
1340 case nir_intrinsic_load_work_group_id
:
1342 case nir_intrinsic_load_local_invocation_id
:
1345 unreachable("Invalid compute paramater loaded");
1350 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1352 emit_explicit_constant(ctx
, src
, src
);
1354 struct midgard_instruction ins
=
1355 v_branch(false, false);
1357 ins
.writeout
= true;
1359 /* Add dependencies */
1361 ins
.constants
.u32
[0] = rt
* 0x100;
1363 /* Emit the branch */
1364 midgard_instruction
*br
= emit_mir_instruction(ctx
, ins
);
1365 schedule_barrier(ctx
);
1367 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1368 assert(!ctx
->writeout_branch
[rt
]);
1369 ctx
->writeout_branch
[rt
] = br
;
1371 /* Push our current location = current block count - 1 = where we'll
1372 * jump to. Maybe a bit too clever for my own good */
1374 br
->branch
.target_block
= ctx
->block_count
- 1;
1378 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1380 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1381 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1382 ins
.mask
= mask_of(3);
1383 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1384 emit_mir_instruction(ctx
, ins
);
1388 vertex_builtin_arg(nir_op op
)
1391 case nir_intrinsic_load_vertex_id
:
1392 return PAN_VERTEX_ID
;
1393 case nir_intrinsic_load_instance_id
:
1394 return PAN_INSTANCE_ID
;
1396 unreachable("Invalid vertex builtin");
1401 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1403 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1404 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1408 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1410 unsigned offset
= 0, reg
;
1412 switch (instr
->intrinsic
) {
1413 case nir_intrinsic_discard_if
:
1414 case nir_intrinsic_discard
: {
1415 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1416 struct midgard_instruction discard
= v_branch(conditional
, false);
1417 discard
.branch
.target_type
= TARGET_DISCARD
;
1420 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1422 emit_mir_instruction(ctx
, discard
);
1423 schedule_barrier(ctx
);
1428 case nir_intrinsic_load_uniform
:
1429 case nir_intrinsic_load_ubo
:
1430 case nir_intrinsic_load_ssbo
:
1431 case nir_intrinsic_load_input
:
1432 case nir_intrinsic_load_interpolated_input
: {
1433 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1434 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1435 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1436 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1437 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1439 /* Get the base type of the intrinsic */
1440 /* TODO: Infer type? Does it matter? */
1442 (is_ubo
|| is_ssbo
) ? nir_type_uint
:
1443 (is_interp
) ? nir_type_float
:
1444 nir_intrinsic_type(instr
);
1446 t
= nir_alu_type_get_base_type(t
);
1448 if (!(is_ubo
|| is_ssbo
)) {
1449 offset
= nir_intrinsic_base(instr
);
1452 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1454 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1456 bool direct
= nir_src_is_const(*src_offset
);
1457 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1460 offset
+= nir_src_as_uint(*src_offset
);
1462 /* We may need to apply a fractional offset */
1463 int component
= (is_flat
|| is_interp
) ?
1464 nir_intrinsic_component(instr
) : 0;
1465 reg
= nir_dest_index(ctx
, &instr
->dest
);
1467 if (is_uniform
&& !ctx
->is_blend
) {
1468 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1469 } else if (is_ubo
) {
1470 nir_src index
= instr
->src
[0];
1472 /* TODO: Is indirect block number possible? */
1473 assert(nir_src_is_const(index
));
1475 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1476 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1477 } else if (is_ssbo
) {
1478 nir_src index
= instr
->src
[0];
1479 assert(nir_src_is_const(index
));
1480 uint32_t uindex
= nir_src_as_uint(index
);
1482 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1483 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1484 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
, is_flat
);
1485 } else if (ctx
->is_blend
) {
1486 /* For blend shaders, load the input color, which is
1487 * preloaded to r0 */
1489 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1490 emit_mir_instruction(ctx
, move
);
1491 schedule_barrier(ctx
);
1492 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1493 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1495 DBG("Unknown load\n");
1502 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1503 case nir_intrinsic_load_barycentric_pixel
:
1504 case nir_intrinsic_load_barycentric_centroid
:
1507 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1509 case nir_intrinsic_load_raw_output_pan
:
1510 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1511 reg
= nir_dest_index(ctx
, &instr
->dest
);
1512 assert(ctx
->is_blend
);
1514 /* T720 and below use different blend opcodes with slightly
1515 * different semantics than T760 and up */
1517 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1518 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1520 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1521 ld
.load_store
.op
= old_blend
?
1522 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1523 midgard_op_ld_color_buffer_u8_as_fp16
;
1526 ld
.load_store
.address
= 1;
1527 ld
.load_store
.arg_2
= 0x1E;
1530 for (unsigned c
= 2; c
< 16; ++c
)
1531 ld
.swizzle
[0][c
] = 0;
1534 emit_mir_instruction(ctx
, ld
);
1537 case nir_intrinsic_load_blend_const_color_rgba
: {
1538 assert(ctx
->is_blend
);
1539 reg
= nir_dest_index(ctx
, &instr
->dest
);
1541 /* Blend constants are embedded directly in the shader and
1542 * patched in, so we use some magic routing */
1544 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1545 ins
.has_constants
= true;
1546 ins
.has_blend_constant
= true;
1547 emit_mir_instruction(ctx
, ins
);
1551 case nir_intrinsic_store_output
:
1552 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1554 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1556 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1558 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1559 emit_fragment_store(ctx
, reg
, offset
);
1560 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1561 /* We should have been vectorized, though we don't
1562 * currently check that st_vary is emitted only once
1563 * per slot (this is relevant, since there's not a mask
1564 * parameter available on the store [set to 0 by the
1565 * blob]). We do respect the component by adjusting the
1566 * swizzle. If this is a constant source, we'll need to
1567 * emit that explicitly. */
1569 emit_explicit_constant(ctx
, reg
, reg
);
1571 unsigned dst_component
= nir_intrinsic_component(instr
);
1572 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1574 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1575 st
.load_store
.arg_1
= 0x9E;
1576 st
.load_store
.arg_2
= 0x1E;
1578 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1581 st
.load_store
.op
= midgard_op_st_vary_32u
;
1584 st
.load_store
.op
= midgard_op_st_vary_32i
;
1586 case nir_type_float
:
1587 st
.load_store
.op
= midgard_op_st_vary_32
;
1590 unreachable("Attempted to store unknown type");
1594 /* nir_intrinsic_component(store_intr) encodes the
1595 * destination component start. Source component offset
1596 * adjustment is taken care of in
1597 * install_registers_instr(), when offset_swizzle() is
1600 unsigned src_component
= COMPONENT_X
;
1602 assert(nr_comp
> 0);
1603 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1604 st
.swizzle
[0][i
] = src_component
;
1605 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1609 emit_mir_instruction(ctx
, st
);
1611 DBG("Unknown store\n");
1617 /* Special case of store_output for lowered blend shaders */
1618 case nir_intrinsic_store_raw_output_pan
:
1619 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1620 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1622 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1623 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1624 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1627 * imov r0.xyzw, r0.xxxx
1630 unsigned expanded
= make_compiler_temp(ctx
);
1632 midgard_instruction splatter
= v_mov(reg
, expanded
);
1634 for (unsigned c
= 0; c
< 16; ++c
)
1635 splatter
.swizzle
[1][c
] = 0;
1637 emit_mir_instruction(ctx
, splatter
);
1638 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1640 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1644 case nir_intrinsic_store_ssbo
:
1645 assert(nir_src_is_const(instr
->src
[1]));
1647 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1648 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1649 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1650 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1652 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1654 emit_explicit_constant(ctx
, reg
, reg
);
1655 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1658 case nir_intrinsic_load_viewport_scale
:
1659 case nir_intrinsic_load_viewport_offset
:
1660 case nir_intrinsic_load_num_work_groups
:
1661 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1662 emit_sysval_read(ctx
, &instr
->instr
, ~0, 3);
1665 case nir_intrinsic_load_work_group_id
:
1666 case nir_intrinsic_load_local_invocation_id
:
1667 emit_compute_builtin(ctx
, instr
);
1670 case nir_intrinsic_load_vertex_id
:
1671 case nir_intrinsic_load_instance_id
:
1672 emit_vertex_builtin(ctx
, instr
);
1676 printf ("Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1683 midgard_tex_format(enum glsl_sampler_dim dim
)
1686 case GLSL_SAMPLER_DIM_1D
:
1687 case GLSL_SAMPLER_DIM_BUF
:
1690 case GLSL_SAMPLER_DIM_2D
:
1691 case GLSL_SAMPLER_DIM_EXTERNAL
:
1692 case GLSL_SAMPLER_DIM_RECT
:
1695 case GLSL_SAMPLER_DIM_3D
:
1698 case GLSL_SAMPLER_DIM_CUBE
:
1699 return MALI_TEX_CUBE
;
1702 DBG("Unknown sampler dim type\n");
1708 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1712 pan_attach_constant_bias(
1713 compiler_context
*ctx
,
1715 midgard_texture_word
*word
)
1717 /* To attach as constant, it has to *be* constant */
1719 if (!nir_src_is_const(lod
))
1722 float f
= nir_src_as_float(lod
);
1724 /* Break into fixed-point */
1726 float lod_frac
= f
- lod_int
;
1728 /* Carry over negative fractions */
1729 if (lod_frac
< 0.0) {
1735 word
->bias
= float_to_ubyte(lod_frac
);
1736 word
->bias_int
= lod_int
;
1741 static enum mali_sampler_type
1742 midgard_sampler_type(nir_alu_type t
) {
1743 switch (nir_alu_type_get_base_type(t
))
1745 case nir_type_float
:
1746 return MALI_SAMPLER_FLOAT
;
1748 return MALI_SAMPLER_SIGNED
;
1750 return MALI_SAMPLER_UNSIGNED
;
1752 unreachable("Unknown sampler type");
1757 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1758 unsigned midgard_texop
)
1761 //assert (!instr->sampler);
1762 //assert (!instr->texture_array_size);
1764 int texture_index
= instr
->texture_index
;
1765 int sampler_index
= texture_index
;
1767 /* No helper to build texture words -- we do it all here */
1768 midgard_instruction ins
= {
1769 .type
= TAG_TEXTURE_4
,
1771 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1772 .src
= { ~0, ~0, ~0, ~0 },
1773 .swizzle
= SWIZZLE_IDENTITY_4
,
1775 .op
= midgard_texop
,
1776 .format
= midgard_tex_format(instr
->sampler_dim
),
1777 .texture_handle
= texture_index
,
1778 .sampler_handle
= sampler_index
,
1784 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1785 .shadow
= instr
->is_shadow
,
1789 /* We may need a temporary for the coordinate */
1791 bool needs_temp_coord
=
1792 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1793 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
1796 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1798 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1799 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1800 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1802 switch (instr
->src
[i
].src_type
) {
1803 case nir_tex_src_coord
: {
1804 emit_explicit_constant(ctx
, index
, index
);
1806 unsigned coord_mask
= mask_of(instr
->coord_components
);
1808 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
1811 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
1813 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1814 /* texelFetch is undefined on samplerCube */
1815 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1817 /* For cubemaps, we use a special ld/st op to
1818 * select the face and copy the xy into the
1819 * texture register */
1821 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
1823 ld
.mask
= 0x3; /* xy */
1824 ld
.load_store
.arg_1
= 0x20;
1825 ld
.swizzle
[1][3] = COMPONENT_X
;
1826 emit_mir_instruction(ctx
, ld
);
1829 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1830 ins
.swizzle
[1][3] = COMPONENT_X
;
1831 } else if (needs_temp_coord
) {
1832 /* mov coord_temp, coords */
1833 midgard_instruction mov
= v_mov(index
, coords
);
1834 mov
.mask
= coord_mask
;
1837 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
1839 emit_mir_instruction(ctx
, mov
);
1844 ins
.src
[1] = coords
;
1846 /* Texelfetch coordinates uses all four elements
1847 * (xyz/index) regardless of texture dimensionality,
1848 * which means it's necessary to zero the unused
1849 * components to keep everything happy */
1851 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1852 /* mov index.zw, #0, or generalized */
1853 midgard_instruction mov
=
1854 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1855 mov
.has_constants
= true;
1856 mov
.mask
= coord_mask
^ 0xF;
1857 emit_mir_instruction(ctx
, mov
);
1860 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1861 /* Array component in w but NIR wants it in z,
1862 * but if we have a temp coord we already fixed
1865 if (nr_components
== 3) {
1866 ins
.swizzle
[1][2] = COMPONENT_Z
;
1867 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
1868 } else if (nr_components
== 2) {
1870 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1871 ins
.swizzle
[1][3] = COMPONENT_X
;
1873 unreachable("Invalid texture 2D components");
1876 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1878 ins
.swizzle
[1][2] = COMPONENT_Z
;
1879 ins
.swizzle
[1][3] = COMPONENT_W
;
1885 case nir_tex_src_bias
:
1886 case nir_tex_src_lod
: {
1887 /* Try as a constant if we can */
1889 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1890 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1893 ins
.texture
.lod_register
= true;
1896 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1897 ins
.swizzle
[2][c
] = COMPONENT_X
;
1899 emit_explicit_constant(ctx
, index
, index
);
1904 case nir_tex_src_offset
: {
1905 ins
.texture
.offset_register
= true;
1908 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1909 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
1911 emit_explicit_constant(ctx
, index
, index
);
1915 case nir_tex_src_comparator
: {
1916 unsigned comp
= COMPONENT_Z
;
1918 /* mov coord_temp.foo, coords */
1919 midgard_instruction mov
= v_mov(index
, coords
);
1920 mov
.mask
= 1 << comp
;
1922 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
1923 mov
.swizzle
[1][i
] = COMPONENT_X
;
1925 emit_mir_instruction(ctx
, mov
);
1930 printf ("Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
1936 emit_mir_instruction(ctx
, ins
);
1938 /* Used for .cont and .last hinting */
1939 ctx
->texture_op_count
++;
1943 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1945 switch (instr
->op
) {
1948 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1951 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1954 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1957 emit_sysval_read(ctx
, &instr
->instr
, ~0, 4);
1960 printf ("Unhandled texture op: %d\n", instr
->op
);
1967 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1969 switch (instr
->type
) {
1970 case nir_jump_break
: {
1971 /* Emit a branch out of the loop */
1972 struct midgard_instruction br
= v_branch(false, false);
1973 br
.branch
.target_type
= TARGET_BREAK
;
1974 br
.branch
.target_break
= ctx
->current_loop_depth
;
1975 emit_mir_instruction(ctx
, br
);
1980 DBG("Unknown jump type %d\n", instr
->type
);
1986 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1988 switch (instr
->type
) {
1989 case nir_instr_type_load_const
:
1990 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1993 case nir_instr_type_intrinsic
:
1994 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1997 case nir_instr_type_alu
:
1998 emit_alu(ctx
, nir_instr_as_alu(instr
));
2001 case nir_instr_type_tex
:
2002 emit_tex(ctx
, nir_instr_as_tex(instr
));
2005 case nir_instr_type_jump
:
2006 emit_jump(ctx
, nir_instr_as_jump(instr
));
2009 case nir_instr_type_ssa_undef
:
2014 DBG("Unhandled instruction type\n");
2020 /* ALU instructions can inline or embed constants, which decreases register
2021 * pressure and saves space. */
2023 #define CONDITIONAL_ATTACH(idx) { \
2024 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2027 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2028 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2033 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2035 mir_foreach_instr_in_block(block
, alu
) {
2036 /* Other instructions cannot inline constants */
2037 if (alu
->type
!= TAG_ALU_4
) continue;
2038 if (alu
->compact_branch
) continue;
2040 /* If there is already a constant here, we can do nothing */
2041 if (alu
->has_constants
) continue;
2043 CONDITIONAL_ATTACH(0);
2045 if (!alu
->has_constants
) {
2046 CONDITIONAL_ATTACH(1)
2047 } else if (!alu
->inline_constant
) {
2048 /* Corner case: _two_ vec4 constants, for instance with a
2049 * csel. For this case, we can only use a constant
2050 * register for one, we'll have to emit a move for the
2051 * other. Note, if both arguments are constants, then
2052 * necessarily neither argument depends on the value of
2053 * any particular register. As the destination register
2054 * will be wiped, that means we can spill the constant
2055 * to the destination register.
2058 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2059 unsigned scratch
= alu
->dest
;
2062 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2063 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2065 /* Set the source */
2066 alu
->src
[1] = scratch
;
2068 /* Inject us -before- the last instruction which set r31 */
2069 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2075 /* Being a little silly with the names, but returns the op that is the bitwise
2076 * inverse of the op with the argument switched. I.e. (f and g are
2079 * f(a, b) = ~g(b, a)
2081 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2083 * f(a, b) = ~g(b, a)
2084 * ~f(a, b) = g(b, a)
2085 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2088 * Thus we define this function in pairs.
2091 static inline midgard_alu_op
2092 mir_contrapositive(midgard_alu_op op
)
2095 case midgard_alu_op_flt
:
2096 return midgard_alu_op_fle
;
2097 case midgard_alu_op_fle
:
2098 return midgard_alu_op_flt
;
2100 case midgard_alu_op_ilt
:
2101 return midgard_alu_op_ile
;
2102 case midgard_alu_op_ile
:
2103 return midgard_alu_op_ilt
;
2106 unreachable("No known contrapositive");
2110 /* Midgard supports two types of constants, embedded constants (128-bit) and
2111 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2112 * constants can be demoted to inline constants, for space savings and
2113 * sometimes a performance boost */
2116 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2118 mir_foreach_instr_in_block(block
, ins
) {
2119 if (!ins
->has_constants
) continue;
2120 if (ins
->has_inline_constant
) continue;
2122 /* Blend constants must not be inlined by definition */
2123 if (ins
->has_blend_constant
) continue;
2125 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2126 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2127 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2129 if (!(is_16
|| is_32
))
2132 /* src1 cannot be an inline constant due to encoding
2133 * restrictions. So, if possible we try to flip the arguments
2136 int op
= ins
->alu
.op
;
2138 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2139 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2142 /* Conditionals can be inverted */
2143 case midgard_alu_op_flt
:
2144 case midgard_alu_op_ilt
:
2145 case midgard_alu_op_fle
:
2146 case midgard_alu_op_ile
:
2147 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2152 case midgard_alu_op_fcsel
:
2153 case midgard_alu_op_icsel
:
2154 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2163 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2164 /* Extract the source information */
2166 midgard_vector_alu_src
*src
;
2167 int q
= ins
->alu
.src2
;
2168 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2171 /* Component is from the swizzle. Take a nonzero component */
2173 unsigned first_comp
= ffs(ins
->mask
) - 1;
2174 unsigned component
= ins
->swizzle
[1][first_comp
];
2176 /* Scale constant appropriately, if we can legally */
2177 uint16_t scaled_constant
= 0;
2180 scaled_constant
= ins
->constants
.u16
[component
];
2181 } else if (midgard_is_integer_op(op
)) {
2182 scaled_constant
= ins
->constants
.u32
[component
];
2184 /* Constant overflow after resize */
2185 if (scaled_constant
!= ins
->constants
.u32
[component
])
2188 float original
= ins
->constants
.f32
[component
];
2189 scaled_constant
= _mesa_float_to_half(original
);
2191 /* Check for loss of precision. If this is
2192 * mediump, we don't care, but for a highp
2193 * shader, we need to pay attention. NIR
2194 * doesn't yet tell us which mode we're in!
2195 * Practically this prevents most constants
2196 * from being inlined, sadly. */
2198 float fp32
= _mesa_half_to_float(scaled_constant
);
2200 if (fp32
!= original
)
2204 /* We don't know how to handle these with a constant */
2206 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2207 DBG("Bailing inline constant...\n");
2211 /* Make sure that the constant is not itself a vector
2212 * by checking if all accessed values are the same. */
2214 const midgard_constants
*cons
= &ins
->constants
;
2215 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2217 bool is_vector
= false;
2218 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2220 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2221 /* We only care if this component is actually used */
2222 if (!(mask
& (1 << c
)))
2225 uint32_t test
= is_16
?
2226 cons
->u16
[ins
->swizzle
[1][c
]] :
2227 cons
->u32
[ins
->swizzle
[1][c
]];
2229 if (test
!= value
) {
2238 /* Get rid of the embedded constant */
2239 ins
->has_constants
= false;
2241 ins
->has_inline_constant
= true;
2242 ins
->inline_constant
= scaled_constant
;
2247 /* Dead code elimination for branches at the end of a block - only one branch
2248 * per block is legal semantically */
2251 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2253 bool branched
= false;
2255 mir_foreach_instr_in_block_safe(block
, ins
) {
2256 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2259 mir_remove_instruction(ins
);
2265 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2266 * the move can be propagated away entirely */
2269 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2272 if (comp
== midgard_outmod_none
)
2275 if (*outmod
== midgard_outmod_none
) {
2280 /* TODO: Compose rules */
2285 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2287 bool progress
= false;
2289 mir_foreach_instr_in_block_safe(block
, ins
) {
2290 if (ins
->type
!= TAG_ALU_4
) continue;
2291 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2292 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2294 /* TODO: Registers? */
2295 unsigned src
= ins
->src
[1];
2296 if (src
& IS_REG
) continue;
2298 /* There might be a source modifier, too */
2299 if (mir_nontrivial_source2_mod(ins
)) continue;
2301 /* Backpropagate the modifier */
2302 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2303 if (v
->type
!= TAG_ALU_4
) continue;
2304 if (v
->dest
!= src
) continue;
2306 /* Can we even take a float outmod? */
2307 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2309 midgard_outmod_float temp
= v
->alu
.outmod
;
2310 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2312 /* Throw in the towel.. */
2313 if (!progress
) break;
2315 /* Otherwise, transfer the modifier */
2316 v
->alu
.outmod
= temp
;
2317 ins
->alu
.outmod
= midgard_outmod_none
;
2327 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2329 /* Loop to ourselves */
2331 struct midgard_instruction ins
= v_branch(false, false);
2332 ins
.writeout
= true;
2333 ins
.branch
.target_block
= ctx
->block_count
- 1;
2334 ins
.constants
.u32
[0] = rt
* 0x100;
2335 emit_mir_instruction(ctx
, ins
);
2337 ctx
->current_block
->epilogue
= true;
2338 schedule_barrier(ctx
);
2339 return ins
.branch
.target_block
;
2342 static midgard_block
*
2343 emit_block(compiler_context
*ctx
, nir_block
*block
)
2345 midgard_block
*this_block
= ctx
->after_block
;
2346 ctx
->after_block
= NULL
;
2349 this_block
= create_empty_block(ctx
);
2351 list_addtail(&this_block
->link
, &ctx
->blocks
);
2353 this_block
->is_scheduled
= false;
2356 /* Set up current block */
2357 list_inithead(&this_block
->instructions
);
2358 ctx
->current_block
= this_block
;
2360 nir_foreach_instr(instr
, block
) {
2361 emit_instr(ctx
, instr
);
2362 ++ctx
->instruction_count
;
2368 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2371 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2373 midgard_block
*before_block
= ctx
->current_block
;
2375 /* Speculatively emit the branch, but we can't fill it in until later */
2376 EMIT(branch
, true, true);
2377 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2378 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2380 /* Emit the two subblocks. */
2381 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2382 midgard_block
*end_then_block
= ctx
->current_block
;
2384 /* Emit a jump from the end of the then block to the end of the else */
2385 EMIT(branch
, false, false);
2386 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2388 /* Emit second block, and check if it's empty */
2390 int else_idx
= ctx
->block_count
;
2391 int count_in
= ctx
->instruction_count
;
2392 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2393 midgard_block
*end_else_block
= ctx
->current_block
;
2394 int after_else_idx
= ctx
->block_count
;
2396 /* Now that we have the subblocks emitted, fix up the branches */
2401 if (ctx
->instruction_count
== count_in
) {
2402 /* The else block is empty, so don't emit an exit jump */
2403 mir_remove_instruction(then_exit
);
2404 then_branch
->branch
.target_block
= after_else_idx
;
2406 then_branch
->branch
.target_block
= else_idx
;
2407 then_exit
->branch
.target_block
= after_else_idx
;
2410 /* Wire up the successors */
2412 ctx
->after_block
= create_empty_block(ctx
);
2414 midgard_block_add_successor(before_block
, then_block
);
2415 midgard_block_add_successor(before_block
, else_block
);
2417 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2418 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2422 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2424 /* Remember where we are */
2425 midgard_block
*start_block
= ctx
->current_block
;
2427 /* Allocate a loop number, growing the current inner loop depth */
2428 int loop_idx
= ++ctx
->current_loop_depth
;
2430 /* Get index from before the body so we can loop back later */
2431 int start_idx
= ctx
->block_count
;
2433 /* Emit the body itself */
2434 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2436 /* Branch back to loop back */
2437 struct midgard_instruction br_back
= v_branch(false, false);
2438 br_back
.branch
.target_block
= start_idx
;
2439 emit_mir_instruction(ctx
, br_back
);
2441 /* Mark down that branch in the graph. */
2442 midgard_block_add_successor(start_block
, loop_block
);
2443 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2445 /* Find the index of the block about to follow us (note: we don't add
2446 * one; blocks are 0-indexed so we get a fencepost problem) */
2447 int break_block_idx
= ctx
->block_count
;
2449 /* Fix up the break statements we emitted to point to the right place,
2450 * now that we can allocate a block number for them */
2451 ctx
->after_block
= create_empty_block(ctx
);
2453 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2454 mir_foreach_instr_in_block(block
, ins
) {
2455 if (ins
->type
!= TAG_ALU_4
) continue;
2456 if (!ins
->compact_branch
) continue;
2458 /* We found a branch -- check the type to see if we need to do anything */
2459 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2461 /* It's a break! Check if it's our break */
2462 if (ins
->branch
.target_break
!= loop_idx
) continue;
2464 /* Okay, cool, we're breaking out of this loop.
2465 * Rewrite from a break to a goto */
2467 ins
->branch
.target_type
= TARGET_GOTO
;
2468 ins
->branch
.target_block
= break_block_idx
;
2470 midgard_block_add_successor(block
, ctx
->after_block
);
2474 /* Now that we've finished emitting the loop, free up the depth again
2475 * so we play nice with recursion amid nested loops */
2476 --ctx
->current_loop_depth
;
2478 /* Dump loop stats */
2482 static midgard_block
*
2483 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2485 midgard_block
*start_block
= NULL
;
2487 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2488 switch (node
->type
) {
2489 case nir_cf_node_block
: {
2490 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2493 start_block
= block
;
2498 case nir_cf_node_if
:
2499 emit_if(ctx
, nir_cf_node_as_if(node
));
2502 case nir_cf_node_loop
:
2503 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2506 case nir_cf_node_function
:
2515 /* Due to lookahead, we need to report the first tag executed in the command
2516 * stream and in branch targets. An initial block might be empty, so iterate
2517 * until we find one that 'works' */
2520 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2522 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2524 unsigned first_tag
= 0;
2526 mir_foreach_block_from(ctx
, initial_block
, v
) {
2527 if (v
->quadword_count
) {
2528 midgard_bundle
*initial_bundle
=
2529 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2531 first_tag
= initial_bundle
->tag
;
2540 pan_format_from_nir_base(nir_alu_type base
)
2544 return MALI_FORMAT_SINT
;
2547 return MALI_FORMAT_UINT
;
2548 case nir_type_float
:
2549 return MALI_CHANNEL_FLOAT
;
2551 unreachable("Invalid base");
2556 pan_format_from_nir_size(nir_alu_type base
, unsigned size
)
2558 if (base
== nir_type_float
) {
2560 case 16: return MALI_FORMAT_SINT
;
2561 case 32: return MALI_FORMAT_UNORM
;
2563 unreachable("Invalid float size for format");
2568 case 8: return MALI_CHANNEL_8
;
2569 case 16: return MALI_CHANNEL_16
;
2570 case 32: return MALI_CHANNEL_32
;
2572 unreachable("Invalid int size for format");
2577 static enum mali_format
2578 pan_format_from_glsl(const struct glsl_type
*type
)
2580 enum glsl_base_type glsl_base
= glsl_get_base_type(glsl_without_array(type
));
2581 nir_alu_type t
= nir_get_nir_type_for_glsl_base_type(glsl_base
);
2583 unsigned base
= nir_alu_type_get_base_type(t
);
2584 unsigned size
= nir_alu_type_get_type_size(t
);
2586 return pan_format_from_nir_base(base
) |
2587 pan_format_from_nir_size(base
, size
) |
2588 MALI_NR_CHANNELS(4);
2591 /* For each fragment writeout instruction, generate a writeout loop to
2592 * associate with it */
2595 mir_add_writeout_loops(compiler_context
*ctx
)
2597 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2598 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2601 unsigned popped
= br
->branch
.target_block
;
2602 midgard_block_add_successor(mir_get_block(ctx
, popped
- 1), ctx
->current_block
);
2603 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2605 /* If we have more RTs, we'll need to restore back after our
2606 * loop terminates */
2608 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2609 midgard_instruction uncond
= v_branch(false, false);
2610 uncond
.branch
.target_block
= popped
;
2611 emit_mir_instruction(ctx
, uncond
);
2612 midgard_block_add_successor(ctx
->current_block
, mir_get_block(ctx
, popped
));
2613 schedule_barrier(ctx
);
2615 /* We're last, so we can terminate here */
2616 br
->last_writeout
= true;
2622 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2624 struct util_dynarray
*compiled
= &program
->compiled
;
2626 midgard_debug
= debug_get_option_midgard_debug();
2628 /* TODO: Bound against what? */
2629 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2632 ctx
->stage
= nir
->info
.stage
;
2633 ctx
->is_blend
= is_blend
;
2634 ctx
->alpha_ref
= program
->alpha_ref
;
2635 ctx
->blend_rt
= blend_rt
;
2636 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2638 /* Start off with a safe cutoff, allowing usage of all 16 work
2639 * registers. Later, we'll promote uniform reads to uniform registers
2640 * if we determine it is beneficial to do so */
2641 ctx
->uniform_cutoff
= 8;
2643 /* Initialize at a global (not block) level hash tables */
2645 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2646 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2647 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2649 /* Record the varying mapping for the command stream's bookkeeping */
2651 struct exec_list
*varyings
=
2652 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2654 unsigned max_varying
= 0;
2655 nir_foreach_variable(var
, varyings
) {
2656 unsigned loc
= var
->data
.driver_location
;
2657 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2659 for (int c
= 0; c
< sz
; ++c
) {
2660 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2661 program
->varying_type
[loc
+ c
] = pan_format_from_glsl(var
->type
);
2662 max_varying
= MAX2(max_varying
, loc
+ c
);
2666 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2667 * (so we don't accidentally duplicate the epilogue since mesa/st has
2668 * messed with our I/O quite a bit already) */
2670 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2672 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2673 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2674 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2677 NIR_PASS_V(nir
, nir_lower_var_copies
);
2678 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2679 NIR_PASS_V(nir
, nir_split_var_copies
);
2680 NIR_PASS_V(nir
, nir_lower_var_copies
);
2681 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2682 NIR_PASS_V(nir
, nir_lower_var_copies
);
2683 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2685 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2687 /* Optimisation passes */
2689 optimise_nir(nir
, ctx
->quirks
);
2691 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2692 nir_print_shader(nir
, stdout
);
2695 /* Assign sysvals and counts, now that we're sure
2696 * (post-optimisation) */
2698 midgard_nir_assign_sysvals(ctx
, nir
);
2700 program
->uniform_count
= nir
->num_uniforms
;
2701 program
->sysval_count
= ctx
->sysval_count
;
2702 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2704 nir_foreach_function(func
, nir
) {
2708 list_inithead(&ctx
->blocks
);
2709 ctx
->block_count
= 0;
2712 emit_cf_list(ctx
, &func
->impl
->body
);
2713 break; /* TODO: Multi-function shaders */
2716 util_dynarray_init(compiled
, NULL
);
2718 /* Per-block lowering before opts */
2720 mir_foreach_block(ctx
, block
) {
2721 inline_alu_constants(ctx
, block
);
2722 midgard_opt_promote_fmov(ctx
, block
);
2723 embedded_to_inline_constant(ctx
, block
);
2725 /* MIR-level optimizations */
2727 bool progress
= false;
2732 mir_foreach_block(ctx
, block
) {
2733 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2734 progress
|= midgard_opt_copy_prop(ctx
, block
);
2735 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2736 progress
|= midgard_opt_combine_projection(ctx
, block
);
2737 progress
|= midgard_opt_varying_projection(ctx
, block
);
2738 progress
|= midgard_opt_not_propagate(ctx
, block
);
2739 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2740 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2741 progress
|= midgard_opt_csel_invert(ctx
, block
);
2742 progress
|= midgard_opt_drop_cmp_invert(ctx
, block
);
2743 progress
|= midgard_opt_invert_branch(ctx
, block
);
2747 mir_foreach_block(ctx
, block
) {
2748 midgard_lower_invert(ctx
, block
);
2749 midgard_lower_derivatives(ctx
, block
);
2752 /* Nested control-flow can result in dead branches at the end of the
2753 * block. This messes with our analysis and is just dead code, so cull
2755 mir_foreach_block(ctx
, block
) {
2756 midgard_opt_cull_dead_branch(ctx
, block
);
2759 /* Ensure we were lowered */
2760 mir_foreach_instr_global(ctx
, ins
) {
2761 assert(!ins
->invert
);
2764 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2765 mir_add_writeout_loops(ctx
);
2768 midgard_schedule_program(ctx
);
2771 /* Now that all the bundles are scheduled and we can calculate block
2772 * sizes, emit actual branch instructions rather than placeholders */
2774 int br_block_idx
= 0;
2776 mir_foreach_block(ctx
, block
) {
2777 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2778 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2779 midgard_instruction
*ins
= bundle
->instructions
[c
];
2781 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2783 /* Parse some basic branch info */
2784 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2785 bool is_conditional
= ins
->branch
.conditional
;
2786 bool is_inverted
= ins
->branch
.invert_conditional
;
2787 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2788 bool is_writeout
= ins
->writeout
;
2790 /* Determine the block we're jumping to */
2791 int target_number
= ins
->branch
.target_block
;
2793 /* Report the destination tag */
2794 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2796 /* Count up the number of quadwords we're
2797 * jumping over = number of quadwords until
2798 * (br_block_idx, target_number) */
2800 int quadword_offset
= 0;
2804 } else if (target_number
> br_block_idx
) {
2807 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2808 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2811 quadword_offset
+= blk
->quadword_count
;
2814 /* Jump backwards */
2816 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2817 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2820 quadword_offset
-= blk
->quadword_count
;
2824 /* Unconditional extended branches (far jumps)
2825 * have issues, so we always use a conditional
2826 * branch, setting the condition to always for
2827 * unconditional. For compact unconditional
2828 * branches, cond isn't used so it doesn't
2829 * matter what we pick. */
2831 midgard_condition cond
=
2832 !is_conditional
? midgard_condition_always
:
2833 is_inverted
? midgard_condition_false
:
2834 midgard_condition_true
;
2836 midgard_jmp_writeout_op op
=
2837 is_discard
? midgard_jmp_writeout_op_discard
:
2838 is_writeout
? midgard_jmp_writeout_op_writeout
:
2839 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2840 midgard_jmp_writeout_op_branch_cond
;
2843 midgard_branch_extended branch
=
2844 midgard_create_branch_extended(
2849 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2850 } else if (is_conditional
|| is_discard
) {
2851 midgard_branch_cond branch
= {
2853 .dest_tag
= dest_tag
,
2854 .offset
= quadword_offset
,
2858 assert(branch
.offset
== quadword_offset
);
2860 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2862 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2864 midgard_branch_uncond branch
= {
2866 .dest_tag
= dest_tag
,
2867 .offset
= quadword_offset
,
2871 assert(branch
.offset
== quadword_offset
);
2873 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2881 /* Emit flat binary from the instruction arrays. Iterate each block in
2882 * sequence. Save instruction boundaries such that lookahead tags can
2883 * be assigned easily */
2885 /* Cache _all_ bundles in source order for lookahead across failed branches */
2887 int bundle_count
= 0;
2888 mir_foreach_block(ctx
, block
) {
2889 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2891 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2893 mir_foreach_block(ctx
, block
) {
2894 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2895 source_order_bundles
[bundle_idx
++] = bundle
;
2899 int current_bundle
= 0;
2901 /* Midgard prefetches instruction types, so during emission we
2902 * need to lookahead. Unless this is the last instruction, in
2903 * which we return 1. */
2905 mir_foreach_block(ctx
, block
) {
2906 mir_foreach_bundle_in_block(block
, bundle
) {
2909 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
2910 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
2912 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2916 /* TODO: Free deeper */
2917 //util_dynarray_fini(&block->instructions);
2920 free(source_order_bundles
);
2922 /* Report the very first tag executed */
2923 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2925 /* Deal with off-by-one related to the fencepost problem */
2926 program
->work_register_count
= ctx
->work_registers
+ 1;
2927 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2929 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2930 program
->tls_size
= ctx
->tls_size
;
2932 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2933 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2935 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2936 unsigned nr_bundles
= 0, nr_ins
= 0;
2938 /* Count instructions and bundles */
2940 mir_foreach_block(ctx
, block
) {
2941 nr_bundles
+= util_dynarray_num_elements(
2942 &block
->bundles
, midgard_bundle
);
2944 mir_foreach_bundle_in_block(block
, bun
)
2945 nr_ins
+= bun
->instruction_count
;
2948 /* Calculate thread count. There are certain cutoffs by
2949 * register count for thread count */
2951 unsigned nr_registers
= program
->work_register_count
;
2953 unsigned nr_threads
=
2954 (nr_registers
<= 4) ? 4 :
2955 (nr_registers
<= 8) ? 2 :
2960 fprintf(stderr
, "shader%d - %s shader: "
2961 "%u inst, %u bundles, %u quadwords, "
2962 "%u registers, %u threads, %u loops, "
2963 "%u:%u spills:fills\n",
2965 gl_shader_stage_name(ctx
->stage
),
2966 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2967 nr_registers
, nr_threads
,
2969 ctx
->spills
, ctx
->fills
);