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pan/mdg: Remove writeout case from bytemask_of_read_components
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
138 M_STORE(st_vary_32, nir_type_uint32);
139 M_LOAD(ld_cubemap_coords, nir_type_uint32);
140 M_LOAD(ld_compute_id, nir_type_uint32);
141
142 static midgard_instruction
143 v_branch(bool conditional, bool invert)
144 {
145 midgard_instruction ins = {
146 .type = TAG_ALU_4,
147 .unit = ALU_ENAB_BRANCH,
148 .compact_branch = true,
149 .branch = {
150 .conditional = conditional,
151 .invert_conditional = invert
152 },
153 .dest = ~0,
154 .src = { ~0, ~0, ~0, ~0 },
155 };
156
157 return ins;
158 }
159
160 static midgard_branch_extended
161 midgard_create_branch_extended( midgard_condition cond,
162 midgard_jmp_writeout_op op,
163 unsigned dest_tag,
164 signed quadword_offset)
165 {
166 /* The condition code is actually a LUT describing a function to
167 * combine multiple condition codes. However, we only support a single
168 * condition code at the moment, so we just duplicate over a bunch of
169 * times. */
170
171 uint16_t duplicated_cond =
172 (cond << 14) |
173 (cond << 12) |
174 (cond << 10) |
175 (cond << 8) |
176 (cond << 6) |
177 (cond << 4) |
178 (cond << 2) |
179 (cond << 0);
180
181 midgard_branch_extended branch = {
182 .op = op,
183 .dest_tag = dest_tag,
184 .offset = quadword_offset,
185 .cond = duplicated_cond
186 };
187
188 return branch;
189 }
190
191 static void
192 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
193 {
194 ins->has_constants = true;
195 memcpy(&ins->constants, constants, 16);
196 }
197
198 static int
199 glsl_type_size(const struct glsl_type *type, bool bindless)
200 {
201 return glsl_count_attribute_slots(type, false);
202 }
203
204 /* Lower fdot2 to a vector multiplication followed by channel addition */
205 static void
206 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
207 {
208 if (alu->op != nir_op_fdot2)
209 return;
210
211 b->cursor = nir_before_instr(&alu->instr);
212
213 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
214 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
215
216 nir_ssa_def *product = nir_fmul(b, src0, src1);
217
218 nir_ssa_def *sum = nir_fadd(b,
219 nir_channel(b, product, 0),
220 nir_channel(b, product, 1));
221
222 /* Replace the fdot2 with this sum */
223 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
224 }
225
226 static bool
227 midgard_nir_lower_fdot2(nir_shader *shader)
228 {
229 bool progress = false;
230
231 nir_foreach_function(function, shader) {
232 if (!function->impl) continue;
233
234 nir_builder _b;
235 nir_builder *b = &_b;
236 nir_builder_init(b, function->impl);
237
238 nir_foreach_block(block, function->impl) {
239 nir_foreach_instr_safe(instr, block) {
240 if (instr->type != nir_instr_type_alu) continue;
241
242 nir_alu_instr *alu = nir_instr_as_alu(instr);
243 midgard_nir_lower_fdot2_body(b, alu);
244
245 progress |= true;
246 }
247 }
248
249 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
250
251 }
252
253 return progress;
254 }
255
256 /* Flushes undefined values to zero */
257
258 static void
259 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
260 {
261 bool progress;
262 unsigned lower_flrp =
263 (nir->options->lower_flrp16 ? 16 : 0) |
264 (nir->options->lower_flrp32 ? 32 : 0) |
265 (nir->options->lower_flrp64 ? 64 : 0);
266
267 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
268 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
269
270 nir_lower_tex_options lower_tex_options = {
271 .lower_txs_lod = true,
272 .lower_txp = ~0,
273 .lower_tex_without_implicit_lod =
274 (quirks & MIDGARD_EXPLICIT_LOD),
275
276 /* TODO: we have native gradient.. */
277 .lower_txd = true,
278 };
279
280 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
281
282 /* Must lower fdot2 after tex is lowered */
283 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
284
285 /* T720 is broken. */
286
287 if (quirks & MIDGARD_BROKEN_LOD)
288 NIR_PASS_V(nir, midgard_nir_lod_errata);
289
290 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
291
292 if (!is_blend)
293 NIR_PASS(progress, nir, nir_fuse_io_16);
294
295 do {
296 progress = false;
297
298 NIR_PASS(progress, nir, nir_lower_var_copies);
299 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
300
301 NIR_PASS(progress, nir, nir_copy_prop);
302 NIR_PASS(progress, nir, nir_opt_remove_phis);
303 NIR_PASS(progress, nir, nir_opt_dce);
304 NIR_PASS(progress, nir, nir_opt_dead_cf);
305 NIR_PASS(progress, nir, nir_opt_cse);
306 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
307 NIR_PASS(progress, nir, nir_opt_algebraic);
308 NIR_PASS(progress, nir, nir_opt_constant_folding);
309
310 if (lower_flrp != 0) {
311 bool lower_flrp_progress = false;
312 NIR_PASS(lower_flrp_progress,
313 nir,
314 nir_lower_flrp,
315 lower_flrp,
316 false /* always_precise */,
317 nir->options->lower_ffma);
318 if (lower_flrp_progress) {
319 NIR_PASS(progress, nir,
320 nir_opt_constant_folding);
321 progress = true;
322 }
323
324 /* Nothing should rematerialize any flrps, so we only
325 * need to do this lowering once.
326 */
327 lower_flrp = 0;
328 }
329
330 NIR_PASS(progress, nir, nir_opt_undef);
331 NIR_PASS(progress, nir, nir_undef_to_zero);
332
333 NIR_PASS(progress, nir, nir_opt_loop_unroll,
334 nir_var_shader_in |
335 nir_var_shader_out |
336 nir_var_function_temp);
337
338 NIR_PASS(progress, nir, nir_opt_vectorize);
339 } while (progress);
340
341 /* Must be run at the end to prevent creation of fsin/fcos ops */
342 NIR_PASS(progress, nir, midgard_nir_scale_trig);
343
344 do {
345 progress = false;
346
347 NIR_PASS(progress, nir, nir_opt_dce);
348 NIR_PASS(progress, nir, nir_opt_algebraic);
349 NIR_PASS(progress, nir, nir_opt_constant_folding);
350 NIR_PASS(progress, nir, nir_copy_prop);
351 } while (progress);
352
353 NIR_PASS(progress, nir, nir_opt_algebraic_late);
354 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
355
356 /* We implement booleans as 32-bit 0/~0 */
357 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
358
359 /* Now that booleans are lowered, we can run out late opts */
360 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
361 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
362
363 NIR_PASS(progress, nir, nir_copy_prop);
364 NIR_PASS(progress, nir, nir_opt_dce);
365
366 /* Take us out of SSA */
367 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
368 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
369
370 /* We are a vector architecture; write combine where possible */
371 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
372 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
373
374 NIR_PASS(progress, nir, nir_opt_dce);
375 }
376
377 /* Do not actually emit a load; instead, cache the constant for inlining */
378
379 static void
380 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
381 {
382 nir_ssa_def def = instr->def;
383
384 midgard_constants *consts = rzalloc(NULL, midgard_constants);
385
386 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
387
388 #define RAW_CONST_COPY(bits) \
389 nir_const_value_to_array(consts->u##bits, instr->value, \
390 instr->def.num_components, u##bits)
391
392 switch (instr->def.bit_size) {
393 case 64:
394 RAW_CONST_COPY(64);
395 break;
396 case 32:
397 RAW_CONST_COPY(32);
398 break;
399 case 16:
400 RAW_CONST_COPY(16);
401 break;
402 case 8:
403 RAW_CONST_COPY(8);
404 break;
405 default:
406 unreachable("Invalid bit_size for load_const instruction\n");
407 }
408
409 /* Shifted for SSA, +1 for off-by-one */
410 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
411 }
412
413 /* Normally constants are embedded implicitly, but for I/O and such we have to
414 * explicitly emit a move with the constant source */
415
416 static void
417 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
418 {
419 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
420
421 if (constant_value) {
422 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
423 attach_constants(ctx, &ins, constant_value, node + 1);
424 emit_mir_instruction(ctx, ins);
425 }
426 }
427
428 static bool
429 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
430 {
431 unsigned comp = src->swizzle[0];
432
433 for (unsigned c = 1; c < nr_components; ++c) {
434 if (src->swizzle[c] != comp)
435 return true;
436 }
437
438 return false;
439 }
440
441 #define ALU_CASE(nir, _op) \
442 case nir_op_##nir: \
443 op = midgard_alu_op_##_op; \
444 assert(src_bitsize == dst_bitsize); \
445 break;
446
447 #define ALU_CASE_RTZ(nir, _op) \
448 case nir_op_##nir: \
449 op = midgard_alu_op_##_op; \
450 roundmode = MIDGARD_RTZ; \
451 break;
452
453 #define ALU_CHECK_CMP(sext) \
454 assert(src_bitsize == 16 || src_bitsize == 32); \
455 assert(dst_bitsize == 16 || dst_bitsize == 32); \
456
457 #define ALU_CASE_BCAST(nir, _op, count) \
458 case nir_op_##nir: \
459 op = midgard_alu_op_##_op; \
460 broadcast_swizzle = count; \
461 ALU_CHECK_CMP(true); \
462 break;
463
464 #define ALU_CASE_CMP(nir, _op, sext) \
465 case nir_op_##nir: \
466 op = midgard_alu_op_##_op; \
467 ALU_CHECK_CMP(sext); \
468 break;
469
470 /* Analyze the sizes of the dest and inputs to determine reg mode. */
471
472 static midgard_reg_mode
473 reg_mode_for_nir(nir_alu_instr *instr)
474 {
475 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
476 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
477 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
478
479 /* We don't have fp16 LUTs, so we'll want to emit code like:
480 *
481 * vlut.fsinr hr0, hr0
482 *
483 * where both input and output are 16-bit but the operation is carried
484 * out in 32-bit
485 */
486
487 switch (instr->op) {
488 case nir_op_fsqrt:
489 case nir_op_frcp:
490 case nir_op_frsq:
491 case nir_op_fsin:
492 case nir_op_fcos:
493 case nir_op_fexp2:
494 case nir_op_flog2:
495 max_bitsize = MAX2(max_bitsize, 32);
496 break;
497
498 /* These get lowered to moves */
499 case nir_op_pack_32_4x8:
500 max_bitsize = 8;
501 break;
502 case nir_op_pack_32_2x16:
503 max_bitsize = 16;
504 break;
505 default:
506 break;
507 }
508
509
510 switch (max_bitsize) {
511 /* Use 16 pipe for 8 since we don't support vec16 yet */
512 case 8:
513 case 16:
514 return midgard_reg_mode_16;
515 case 32:
516 return midgard_reg_mode_32;
517 case 64:
518 return midgard_reg_mode_64;
519 default:
520 unreachable("Invalid bit size");
521 }
522 }
523
524 /* Compare mir_lower_invert */
525 static bool
526 nir_accepts_inot(nir_op op, unsigned src)
527 {
528 switch (op) {
529 case nir_op_ior:
530 case nir_op_iand: /* TODO: b2f16 */
531 case nir_op_ixor:
532 return true;
533 case nir_op_b32csel:
534 /* Only the condition */
535 return (src == 0);
536 default:
537 return false;
538 }
539 }
540
541 static bool
542 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
543 {
544 if (pan_has_dest_mod(dest, op)) {
545 assert((*dest)->is_ssa);
546 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
547 return true;
548 }
549
550 return false;
551 }
552
553 static void
554 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
555 {
556 nir_alu_src src = instr->src[i];
557
558 if (!is_int) {
559 if (pan_has_source_mod(&src, nir_op_fneg))
560 *neg = !(*neg);
561
562 if (pan_has_source_mod(&src, nir_op_fabs))
563 *abs = true;
564 }
565
566 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
567 *not = true;
568
569 if (roundmode) {
570 if (pan_has_source_mod(&src, nir_op_fround_even))
571 *roundmode = MIDGARD_RTE;
572
573 if (pan_has_source_mod(&src, nir_op_ftrunc))
574 *roundmode = MIDGARD_RTZ;
575
576 if (pan_has_source_mod(&src, nir_op_ffloor))
577 *roundmode = MIDGARD_RTN;
578
579 if (pan_has_source_mod(&src, nir_op_fceil))
580 *roundmode = MIDGARD_RTP;
581 }
582
583 unsigned bits = nir_src_bit_size(src.src);
584
585 ins->src[to] = nir_src_index(NULL, &src.src);
586 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
587
588 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
589 ins->swizzle[to][c] = src.swizzle[
590 (!bcast_count || c < bcast_count) ? c :
591 (bcast_count - 1)];
592 }
593 }
594
595 /* Midgard features both fcsel and icsel, depending on whether you want int or
596 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
597 * we should emit an int or float csel depending on what modifiers could be
598 * placed. In the absense of modifiers, this is probably arbitrary. */
599
600 static bool
601 mir_is_bcsel_float(nir_alu_instr *instr)
602 {
603 nir_op intmods[] = {
604 nir_op_i2i8, nir_op_i2i16,
605 nir_op_i2i32, nir_op_i2i64
606 };
607
608 nir_op floatmods[] = {
609 nir_op_fabs, nir_op_fneg,
610 nir_op_f2f16, nir_op_f2f32,
611 nir_op_f2f64
612 };
613
614 nir_op floatdestmods[] = {
615 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
616 nir_op_f2f16, nir_op_f2f32
617 };
618
619 signed score = 0;
620
621 for (unsigned i = 1; i < 3; ++i) {
622 nir_alu_src s = instr->src[i];
623 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
624 if (pan_has_source_mod(&s, intmods[q]))
625 score--;
626 }
627 }
628
629 for (unsigned i = 1; i < 3; ++i) {
630 nir_alu_src s = instr->src[i];
631 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
632 if (pan_has_source_mod(&s, floatmods[q]))
633 score++;
634 }
635 }
636
637 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
638 nir_dest *dest = &instr->dest.dest;
639 if (pan_has_dest_mod(&dest, floatdestmods[q]))
640 score++;
641 }
642
643 return (score > 0);
644 }
645
646 static void
647 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
648 {
649 nir_dest *dest = &instr->dest.dest;
650
651 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
652 return;
653
654 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
655 * is handled elsewhere */
656
657 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
658 midgard_emit_derivatives(ctx, instr);
659 return;
660 }
661
662 bool is_ssa = dest->is_ssa;
663
664 unsigned nr_components = nir_dest_num_components(*dest);
665 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
666 unsigned op = 0;
667
668 /* Number of components valid to check for the instruction (the rest
669 * will be forced to the last), or 0 to use as-is. Relevant as
670 * ball-type instructions have a channel count in NIR but are all vec4
671 * in Midgard */
672
673 unsigned broadcast_swizzle = 0;
674
675 /* What register mode should we operate in? */
676 midgard_reg_mode reg_mode =
677 reg_mode_for_nir(instr);
678
679 /* Should we swap arguments? */
680 bool flip_src12 = false;
681
682 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
683 unsigned dst_bitsize = nir_dest_bit_size(*dest);
684
685 enum midgard_roundmode roundmode = MIDGARD_RTE;
686
687 switch (instr->op) {
688 ALU_CASE(fadd, fadd);
689 ALU_CASE(fmul, fmul);
690 ALU_CASE(fmin, fmin);
691 ALU_CASE(fmax, fmax);
692 ALU_CASE(imin, imin);
693 ALU_CASE(imax, imax);
694 ALU_CASE(umin, umin);
695 ALU_CASE(umax, umax);
696 ALU_CASE(ffloor, ffloor);
697 ALU_CASE(fround_even, froundeven);
698 ALU_CASE(ftrunc, ftrunc);
699 ALU_CASE(fceil, fceil);
700 ALU_CASE(fdot3, fdot3);
701 ALU_CASE(fdot4, fdot4);
702 ALU_CASE(iadd, iadd);
703 ALU_CASE(isub, isub);
704 ALU_CASE(imul, imul);
705
706 /* Zero shoved as second-arg */
707 ALU_CASE(iabs, iabsdiff);
708
709 ALU_CASE(mov, imov);
710
711 ALU_CASE_CMP(feq32, feq, false);
712 ALU_CASE_CMP(fne32, fne, false);
713 ALU_CASE_CMP(flt32, flt, false);
714 ALU_CASE_CMP(ieq32, ieq, true);
715 ALU_CASE_CMP(ine32, ine, true);
716 ALU_CASE_CMP(ilt32, ilt, true);
717 ALU_CASE_CMP(ult32, ult, false);
718
719 /* We don't have a native b2f32 instruction. Instead, like many
720 * GPUs, we exploit booleans as 0/~0 for false/true, and
721 * correspondingly AND
722 * by 1.0 to do the type conversion. For the moment, prime us
723 * to emit:
724 *
725 * iand [whatever], #0
726 *
727 * At the end of emit_alu (as MIR), we'll fix-up the constant
728 */
729
730 ALU_CASE_CMP(b2f32, iand, true);
731 ALU_CASE_CMP(b2f16, iand, true);
732 ALU_CASE_CMP(b2i32, iand, true);
733
734 /* Likewise, we don't have a dedicated f2b32 instruction, but
735 * we can do a "not equal to 0.0" test. */
736
737 ALU_CASE_CMP(f2b32, fne, false);
738 ALU_CASE_CMP(i2b32, ine, true);
739
740 ALU_CASE(frcp, frcp);
741 ALU_CASE(frsq, frsqrt);
742 ALU_CASE(fsqrt, fsqrt);
743 ALU_CASE(fexp2, fexp2);
744 ALU_CASE(flog2, flog2);
745
746 ALU_CASE_RTZ(f2i64, f2i_rte);
747 ALU_CASE_RTZ(f2u64, f2u_rte);
748 ALU_CASE_RTZ(i2f64, i2f_rte);
749 ALU_CASE_RTZ(u2f64, u2f_rte);
750
751 ALU_CASE_RTZ(f2i32, f2i_rte);
752 ALU_CASE_RTZ(f2u32, f2u_rte);
753 ALU_CASE_RTZ(i2f32, i2f_rte);
754 ALU_CASE_RTZ(u2f32, u2f_rte);
755
756 ALU_CASE_RTZ(f2i8, f2i_rte);
757 ALU_CASE_RTZ(f2u8, f2u_rte);
758
759 ALU_CASE_RTZ(f2i16, f2i_rte);
760 ALU_CASE_RTZ(f2u16, f2u_rte);
761 ALU_CASE_RTZ(i2f16, i2f_rte);
762 ALU_CASE_RTZ(u2f16, u2f_rte);
763
764 ALU_CASE(fsin, fsin);
765 ALU_CASE(fcos, fcos);
766
767 /* We'll get 0 in the second arg, so:
768 * ~a = ~(a | 0) = nor(a, 0) */
769 ALU_CASE(inot, inor);
770 ALU_CASE(iand, iand);
771 ALU_CASE(ior, ior);
772 ALU_CASE(ixor, ixor);
773 ALU_CASE(ishl, ishl);
774 ALU_CASE(ishr, iasr);
775 ALU_CASE(ushr, ilsr);
776
777 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
778 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
779 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
780
781 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
782 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
783 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
784
785 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
786 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
787 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
788
789 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
790 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
791 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
792
793 /* Source mods will be shoved in later */
794 ALU_CASE(fabs, fmov);
795 ALU_CASE(fneg, fmov);
796 ALU_CASE(fsat, fmov);
797 ALU_CASE(fsat_signed, fmov);
798 ALU_CASE(fclamp_pos, fmov);
799
800 /* For size conversion, we use a move. Ideally though we would squash
801 * these ops together; maybe that has to happen after in NIR as part of
802 * propagation...? An earlier algebraic pass ensured we step down by
803 * only / exactly one size. If stepping down, we use a dest override to
804 * reduce the size; if stepping up, we use a larger-sized move with a
805 * half source and a sign/zero-extension modifier */
806
807 case nir_op_i2i8:
808 case nir_op_i2i16:
809 case nir_op_i2i32:
810 case nir_op_i2i64:
811 case nir_op_u2u8:
812 case nir_op_u2u16:
813 case nir_op_u2u32:
814 case nir_op_u2u64:
815 case nir_op_f2f16:
816 case nir_op_f2f32:
817 case nir_op_f2f64: {
818 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
819 instr->op == nir_op_f2f64)
820 op = midgard_alu_op_fmov;
821 else
822 op = midgard_alu_op_imov;
823
824 break;
825 }
826
827 /* For greater-or-equal, we lower to less-or-equal and flip the
828 * arguments */
829
830 case nir_op_fge:
831 case nir_op_fge32:
832 case nir_op_ige32:
833 case nir_op_uge32: {
834 op =
835 instr->op == nir_op_fge ? midgard_alu_op_fle :
836 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
837 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
838 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
839 0;
840
841 flip_src12 = true;
842 ALU_CHECK_CMP(false);
843 break;
844 }
845
846 case nir_op_b32csel: {
847 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
848 bool is_float = mir_is_bcsel_float(instr);
849 op = is_float ?
850 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
851 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
852
853 break;
854 }
855
856 case nir_op_unpack_32_2x16:
857 case nir_op_unpack_32_4x8:
858 case nir_op_pack_32_2x16:
859 case nir_op_pack_32_4x8: {
860 op = midgard_alu_op_imov;
861 break;
862 }
863
864 default:
865 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
866 assert(0);
867 return;
868 }
869
870 /* Promote imov to fmov if it might help inline a constant */
871 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
872 && nir_src_bit_size(instr->src[0].src) == 32
873 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
874 nir_src_num_components(instr->src[0].src))) {
875 op = midgard_alu_op_fmov;
876 }
877
878 /* Midgard can perform certain modifiers on output of an ALU op */
879
880 unsigned outmod = 0;
881 bool is_int = midgard_is_integer_op(op);
882
883 if (midgard_is_integer_out_op(op)) {
884 outmod = midgard_outmod_int_wrap;
885 } else if (instr->op == nir_op_fsat) {
886 outmod = midgard_outmod_sat;
887 } else if (instr->op == nir_op_fsat_signed) {
888 outmod = midgard_outmod_sat_signed;
889 } else if (instr->op == nir_op_fclamp_pos) {
890 outmod = midgard_outmod_pos;
891 }
892
893 /* Fetch unit, quirks, etc information */
894 unsigned opcode_props = alu_opcode_props[op].props;
895 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
896
897 /* Look for floating point mods. We have the mods fsat, fsat_signed,
898 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
899 *
900 * fsat_signed(fpos(x)) = fsat(x)
901 * fsat_signed(fsat(x)) = fsat(x)
902 * fpos(fsat_signed(x)) = fsat(x)
903 * fpos(fsat(x)) = fsat(x)
904 * fsat(fsat_signed(x)) = fsat(x)
905 * fsat(fpos(x)) = fsat(x)
906 *
907 * So by cases any composition of output modifiers is equivalent to
908 * fsat alone.
909 */
910
911 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
912 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
913 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
914 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
915 bool prior = (outmod != midgard_outmod_none);
916 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
917
918 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
919 fpos ? midgard_outmod_pos :
920 ssat ? midgard_outmod_sat_signed :
921 outmod;
922 }
923
924 midgard_instruction ins = {
925 .type = TAG_ALU_4,
926 .dest = nir_dest_index(dest),
927 .dest_type = nir_op_infos[instr->op].output_type
928 | nir_dest_bit_size(*dest),
929 .roundmode = roundmode,
930 };
931
932 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
933 &ins.roundmode : NULL;
934
935 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
936 ins.src[i] = ~0;
937
938 if (quirk_flipped_r24) {
939 ins.src[0] = ~0;
940 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
941 } else {
942 for (unsigned i = 0; i < nr_inputs; ++i) {
943 unsigned to = i;
944
945 if (instr->op == nir_op_b32csel) {
946 /* The condition is the first argument; move
947 * the other arguments up one to be a binary
948 * instruction for Midgard with the condition
949 * last */
950
951 if (i == 0)
952 to = 2;
953 else if (flip_src12)
954 to = 2 - i;
955 else
956 to = i - 1;
957 } else if (flip_src12) {
958 to = 1 - to;
959 }
960
961 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
962
963 /* (!c) ? a : b = c ? b : a */
964 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
965 ins.src_invert[2] = false;
966 flip_src12 ^= true;
967 }
968 }
969 }
970
971 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
972 /* Lowered to move */
973 if (instr->op == nir_op_fneg)
974 ins.src_neg[1] ^= true;
975
976 if (instr->op == nir_op_fabs)
977 ins.src_abs[1] = true;
978 }
979
980 ins.mask = mask_of(nr_components);
981
982 midgard_vector_alu alu = {
983 .op = op,
984 .reg_mode = reg_mode,
985 .outmod = outmod,
986 };
987
988 /* Apply writemask if non-SSA, keeping in mind that we can't write to
989 * components that don't exist. Note modifier => SSA => !reg => no
990 * writemask, so we don't have to worry about writemasks here.*/
991
992 if (!is_ssa)
993 ins.mask &= instr->dest.write_mask;
994
995 ins.alu = alu;
996
997 /* Late fixup for emulated instructions */
998
999 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1000 /* Presently, our second argument is an inline #0 constant.
1001 * Switch over to an embedded 1.0 constant (that can't fit
1002 * inline, since we're 32-bit, not 16-bit like the inline
1003 * constants) */
1004
1005 ins.has_inline_constant = false;
1006 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1007 ins.src_types[1] = nir_type_float32;
1008 ins.has_constants = true;
1009
1010 if (instr->op == nir_op_b2f32)
1011 ins.constants.f32[0] = 1.0f;
1012 else
1013 ins.constants.i32[0] = 1;
1014
1015 for (unsigned c = 0; c < 16; ++c)
1016 ins.swizzle[1][c] = 0;
1017 } else if (instr->op == nir_op_b2f16) {
1018 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1019 ins.src_types[1] = nir_type_float16;
1020 ins.has_constants = true;
1021 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1022
1023 for (unsigned c = 0; c < 16; ++c)
1024 ins.swizzle[1][c] = 0;
1025 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1026 /* Lots of instructions need a 0 plonked in */
1027 ins.has_inline_constant = false;
1028 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1029 ins.src_types[1] = nir_type_uint32;
1030 ins.has_constants = true;
1031 ins.constants.u32[0] = 0;
1032
1033 for (unsigned c = 0; c < 16; ++c)
1034 ins.swizzle[1][c] = 0;
1035 } else if (instr->op == nir_op_pack_32_2x16) {
1036 ins.dest_type = nir_type_uint16;
1037 ins.mask = mask_of(nr_components * 2);
1038 ins.is_pack = true;
1039 } else if (instr->op == nir_op_pack_32_4x8) {
1040 ins.dest_type = nir_type_uint8;
1041 ins.mask = mask_of(nr_components * 4);
1042 ins.is_pack = true;
1043 } else if (instr->op == nir_op_unpack_32_2x16) {
1044 ins.dest_type = nir_type_uint32;
1045 ins.mask = mask_of(nr_components >> 1);
1046 ins.is_pack = true;
1047 } else if (instr->op == nir_op_unpack_32_4x8) {
1048 ins.dest_type = nir_type_uint32;
1049 ins.mask = mask_of(nr_components >> 2);
1050 ins.is_pack = true;
1051 }
1052
1053 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1054 /* To avoid duplicating the lookup tables (probably), true LUT
1055 * instructions can only operate as if they were scalars. Lower
1056 * them here by changing the component. */
1057
1058 unsigned orig_mask = ins.mask;
1059
1060 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1061 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1062
1063 for (int i = 0; i < nr_components; ++i) {
1064 /* Mask the associated component, dropping the
1065 * instruction if needed */
1066
1067 ins.mask = 1 << i;
1068 ins.mask &= orig_mask;
1069
1070 if (!ins.mask)
1071 continue;
1072
1073 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1074 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1075
1076 emit_mir_instruction(ctx, ins);
1077 }
1078 } else {
1079 emit_mir_instruction(ctx, ins);
1080 }
1081 }
1082
1083 #undef ALU_CASE
1084
1085 static void
1086 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1087 {
1088 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1089 unsigned nir_mask = 0;
1090 unsigned dsize = 0;
1091
1092 if (is_read) {
1093 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1094 dsize = nir_dest_bit_size(intr->dest);
1095 } else {
1096 nir_mask = nir_intrinsic_write_mask(intr);
1097 dsize = 32;
1098 }
1099
1100 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1101 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1102 mir_set_bytemask(ins, bytemask);
1103 ins->dest_type = nir_type_uint | dsize;
1104 }
1105
1106 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1107 * optimized) versions of UBO #0 */
1108
1109 static midgard_instruction *
1110 emit_ubo_read(
1111 compiler_context *ctx,
1112 nir_instr *instr,
1113 unsigned dest,
1114 unsigned offset,
1115 nir_src *indirect_offset,
1116 unsigned indirect_shift,
1117 unsigned index)
1118 {
1119 /* TODO: half-floats */
1120
1121 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1122 ins.constants.u32[0] = offset;
1123
1124 if (instr->type == nir_instr_type_intrinsic)
1125 mir_set_intr_mask(instr, &ins, true);
1126
1127 if (indirect_offset) {
1128 ins.src[2] = nir_src_index(ctx, indirect_offset);
1129 ins.src_types[2] = nir_type_uint32;
1130 ins.load_store.arg_2 = (indirect_shift << 5);
1131 } else {
1132 ins.load_store.arg_2 = 0x1E;
1133 }
1134
1135 ins.load_store.arg_1 = index;
1136
1137 return emit_mir_instruction(ctx, ins);
1138 }
1139
1140 /* Globals are like UBOs if you squint. And shared memory is like globals if
1141 * you squint even harder */
1142
1143 static void
1144 emit_global(
1145 compiler_context *ctx,
1146 nir_instr *instr,
1147 bool is_read,
1148 unsigned srcdest,
1149 nir_src *offset,
1150 bool is_shared)
1151 {
1152 /* TODO: types */
1153
1154 midgard_instruction ins;
1155
1156 if (is_read)
1157 ins = m_ld_int4(srcdest, 0);
1158 else
1159 ins = m_st_int4(srcdest, 0);
1160
1161 mir_set_offset(ctx, &ins, offset, is_shared);
1162 mir_set_intr_mask(instr, &ins, is_read);
1163
1164 emit_mir_instruction(ctx, ins);
1165 }
1166
1167 static void
1168 emit_varying_read(
1169 compiler_context *ctx,
1170 unsigned dest, unsigned offset,
1171 unsigned nr_comp, unsigned component,
1172 nir_src *indirect_offset, nir_alu_type type, bool flat)
1173 {
1174 /* XXX: Half-floats? */
1175 /* TODO: swizzle, mask */
1176
1177 midgard_instruction ins = m_ld_vary_32(dest, offset);
1178 ins.mask = mask_of(nr_comp);
1179 ins.dest_type = type;
1180
1181 if (type == nir_type_float16) {
1182 /* Ensure we are aligned so we can pack it later */
1183 ins.mask = mask_of(ALIGN_POT(nr_comp, 2));
1184 }
1185
1186 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1187 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1188
1189 midgard_varying_parameter p = {
1190 .is_varying = 1,
1191 .interpolation = midgard_interp_default,
1192 .flat = flat,
1193 };
1194
1195 unsigned u;
1196 memcpy(&u, &p, sizeof(p));
1197 ins.load_store.varying_parameters = u;
1198
1199 if (indirect_offset) {
1200 ins.src[2] = nir_src_index(ctx, indirect_offset);
1201 ins.src_types[2] = nir_type_uint32;
1202 } else
1203 ins.load_store.arg_2 = 0x1E;
1204
1205 ins.load_store.arg_1 = 0x9E;
1206
1207 /* Use the type appropriate load */
1208 switch (type) {
1209 case nir_type_uint32:
1210 case nir_type_bool32:
1211 ins.load_store.op = midgard_op_ld_vary_32u;
1212 break;
1213 case nir_type_int32:
1214 ins.load_store.op = midgard_op_ld_vary_32i;
1215 break;
1216 case nir_type_float32:
1217 ins.load_store.op = midgard_op_ld_vary_32;
1218 break;
1219 case nir_type_float16:
1220 ins.load_store.op = midgard_op_ld_vary_16;
1221 break;
1222 default:
1223 unreachable("Attempted to load unknown type");
1224 break;
1225 }
1226
1227 emit_mir_instruction(ctx, ins);
1228 }
1229
1230 static void
1231 emit_attr_read(
1232 compiler_context *ctx,
1233 unsigned dest, unsigned offset,
1234 unsigned nr_comp, nir_alu_type t)
1235 {
1236 midgard_instruction ins = m_ld_attr_32(dest, offset);
1237 ins.load_store.arg_1 = 0x1E;
1238 ins.load_store.arg_2 = 0x1E;
1239 ins.mask = mask_of(nr_comp);
1240
1241 /* Use the type appropriate load */
1242 switch (t) {
1243 case nir_type_uint:
1244 case nir_type_bool:
1245 ins.load_store.op = midgard_op_ld_attr_32u;
1246 break;
1247 case nir_type_int:
1248 ins.load_store.op = midgard_op_ld_attr_32i;
1249 break;
1250 case nir_type_float:
1251 ins.load_store.op = midgard_op_ld_attr_32;
1252 break;
1253 default:
1254 unreachable("Attempted to load unknown type");
1255 break;
1256 }
1257
1258 emit_mir_instruction(ctx, ins);
1259 }
1260
1261 static void
1262 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1263 unsigned nr_components, unsigned offset)
1264 {
1265 nir_dest nir_dest;
1266
1267 /* Figure out which uniform this is */
1268 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1269 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1270
1271 unsigned dest = nir_dest_index(&nir_dest);
1272
1273 /* Sysvals are prefix uniforms */
1274 unsigned uniform = ((uintptr_t) val) - 1;
1275
1276 /* Emit the read itself -- this is never indirect */
1277 midgard_instruction *ins =
1278 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1279
1280 ins->mask = mask_of(nr_components);
1281 }
1282
1283 static unsigned
1284 compute_builtin_arg(nir_op op)
1285 {
1286 switch (op) {
1287 case nir_intrinsic_load_work_group_id:
1288 return 0x14;
1289 case nir_intrinsic_load_local_invocation_id:
1290 return 0x10;
1291 default:
1292 unreachable("Invalid compute paramater loaded");
1293 }
1294 }
1295
1296 static void
1297 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1298 {
1299 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1300
1301 midgard_instruction *br = ctx->writeout_branch[rt];
1302
1303 assert(!br);
1304
1305 emit_explicit_constant(ctx, src, src);
1306
1307 struct midgard_instruction ins =
1308 v_branch(false, false);
1309
1310 ins.writeout = true;
1311
1312 /* Add dependencies */
1313 ins.src[0] = src;
1314 ins.src_types[0] = nir_type_uint32;
1315 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1316 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1317 for (int i = 0; i < 4; ++i)
1318 ins.swizzle[0][i] = i;
1319
1320 /* Emit the branch */
1321 br = emit_mir_instruction(ctx, ins);
1322 schedule_barrier(ctx);
1323 ctx->writeout_branch[rt] = br;
1324
1325 /* Push our current location = current block count - 1 = where we'll
1326 * jump to. Maybe a bit too clever for my own good */
1327
1328 br->branch.target_block = ctx->block_count - 1;
1329 }
1330
1331 static void
1332 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1333 {
1334 unsigned reg = nir_dest_index(&instr->dest);
1335 midgard_instruction ins = m_ld_compute_id(reg, 0);
1336 ins.mask = mask_of(3);
1337 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1338 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1339 emit_mir_instruction(ctx, ins);
1340 }
1341
1342 static unsigned
1343 vertex_builtin_arg(nir_op op)
1344 {
1345 switch (op) {
1346 case nir_intrinsic_load_vertex_id:
1347 return PAN_VERTEX_ID;
1348 case nir_intrinsic_load_instance_id:
1349 return PAN_INSTANCE_ID;
1350 default:
1351 unreachable("Invalid vertex builtin");
1352 }
1353 }
1354
1355 static void
1356 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1357 {
1358 unsigned reg = nir_dest_index(&instr->dest);
1359 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1360 }
1361
1362 static void
1363 emit_control_barrier(compiler_context *ctx)
1364 {
1365 midgard_instruction ins = {
1366 .type = TAG_TEXTURE_4,
1367 .dest = ~0,
1368 .src = { ~0, ~0, ~0, ~0 },
1369 .texture = {
1370 .op = TEXTURE_OP_BARRIER,
1371
1372 /* TODO: optimize */
1373 .out_of_order = MIDGARD_BARRIER_BUFFER |
1374 MIDGARD_BARRIER_SHARED ,
1375 }
1376 };
1377
1378 emit_mir_instruction(ctx, ins);
1379 }
1380
1381 static const nir_variable *
1382 search_var(struct exec_list *vars, unsigned driver_loc)
1383 {
1384 nir_foreach_variable(var, vars) {
1385 if (var->data.driver_location == driver_loc)
1386 return var;
1387 }
1388
1389 return NULL;
1390 }
1391
1392 static unsigned
1393 mir_get_branch_cond(nir_src *src, bool *invert)
1394 {
1395 /* Wrap it. No swizzle since it's a scalar */
1396
1397 nir_alu_src alu = {
1398 .src = *src
1399 };
1400
1401 *invert = pan_has_source_mod(&alu, nir_op_inot);
1402 return nir_src_index(NULL, &alu.src);
1403 }
1404
1405 static void
1406 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1407 {
1408 unsigned offset = 0, reg;
1409
1410 switch (instr->intrinsic) {
1411 case nir_intrinsic_discard_if:
1412 case nir_intrinsic_discard: {
1413 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1414 struct midgard_instruction discard = v_branch(conditional, false);
1415 discard.branch.target_type = TARGET_DISCARD;
1416
1417 if (conditional) {
1418 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1419 &discard.branch.invert_conditional);
1420 discard.src_types[0] = nir_type_uint32;
1421 }
1422
1423 emit_mir_instruction(ctx, discard);
1424 schedule_barrier(ctx);
1425
1426 break;
1427 }
1428
1429 case nir_intrinsic_load_uniform:
1430 case nir_intrinsic_load_ubo:
1431 case nir_intrinsic_load_global:
1432 case nir_intrinsic_load_shared:
1433 case nir_intrinsic_load_input:
1434 case nir_intrinsic_load_interpolated_input: {
1435 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1436 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1437 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1438 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1439 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1440 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1441
1442 /* Get the base type of the intrinsic */
1443 /* TODO: Infer type? Does it matter? */
1444 nir_alu_type t =
1445 (is_ubo || is_global || is_shared) ? nir_type_uint :
1446 (is_interp) ? nir_type_float :
1447 nir_intrinsic_type(instr);
1448
1449 t = nir_alu_type_get_base_type(t);
1450
1451 if (!(is_ubo || is_global)) {
1452 offset = nir_intrinsic_base(instr);
1453 }
1454
1455 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1456
1457 nir_src *src_offset = nir_get_io_offset_src(instr);
1458
1459 bool direct = nir_src_is_const(*src_offset);
1460 nir_src *indirect_offset = direct ? NULL : src_offset;
1461
1462 if (direct)
1463 offset += nir_src_as_uint(*src_offset);
1464
1465 /* We may need to apply a fractional offset */
1466 int component = (is_flat || is_interp) ?
1467 nir_intrinsic_component(instr) : 0;
1468 reg = nir_dest_index(&instr->dest);
1469
1470 if (is_uniform && !ctx->is_blend) {
1471 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1472 } else if (is_ubo) {
1473 nir_src index = instr->src[0];
1474
1475 /* TODO: Is indirect block number possible? */
1476 assert(nir_src_is_const(index));
1477
1478 uint32_t uindex = nir_src_as_uint(index) + 1;
1479 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1480 } else if (is_global || is_shared) {
1481 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1482 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1483 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1484 } else if (ctx->is_blend) {
1485 /* For blend shaders, load the input color, which is
1486 * preloaded to r0 */
1487
1488 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1489 emit_mir_instruction(ctx, move);
1490 schedule_barrier(ctx);
1491 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1492 emit_attr_read(ctx, reg, offset, nr_comp, t);
1493 } else {
1494 DBG("Unknown load\n");
1495 assert(0);
1496 }
1497
1498 break;
1499 }
1500
1501 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1502 case nir_intrinsic_load_barycentric_pixel:
1503 case nir_intrinsic_load_barycentric_centroid:
1504 break;
1505
1506 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1507
1508 case nir_intrinsic_load_raw_output_pan: {
1509 reg = nir_dest_index(&instr->dest);
1510 assert(ctx->is_blend);
1511
1512 /* T720 and below use different blend opcodes with slightly
1513 * different semantics than T760 and up */
1514
1515 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1516
1517 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1518 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1519 ld.load_store.address = 16;
1520 ld.load_store.arg_2 = 0x1E;
1521 }
1522
1523 emit_mir_instruction(ctx, ld);
1524 break;
1525 }
1526
1527 case nir_intrinsic_load_output: {
1528 reg = nir_dest_index(&instr->dest);
1529 assert(ctx->is_blend);
1530
1531 midgard_instruction ld = m_ld_color_buffer_as_fp16(reg, 0);
1532
1533 for (unsigned c = 4; c < 16; ++c)
1534 ld.swizzle[0][c] = 0;
1535
1536 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1537 ld.load_store.op = midgard_op_ld_color_buffer_as_fp16_old;
1538 ld.load_store.address = 1;
1539 ld.load_store.arg_2 = 0x1E;
1540 }
1541
1542 emit_mir_instruction(ctx, ld);
1543 break;
1544 }
1545
1546 case nir_intrinsic_load_blend_const_color_rgba: {
1547 assert(ctx->is_blend);
1548 reg = nir_dest_index(&instr->dest);
1549
1550 /* Blend constants are embedded directly in the shader and
1551 * patched in, so we use some magic routing */
1552
1553 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1554 ins.has_constants = true;
1555 ins.has_blend_constant = true;
1556 emit_mir_instruction(ctx, ins);
1557 break;
1558 }
1559
1560 case nir_intrinsic_store_output:
1561 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1562
1563 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1564
1565 reg = nir_src_index(ctx, &instr->src[0]);
1566
1567 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1568 const nir_variable *var;
1569 enum midgard_rt_id rt;
1570
1571 var = search_var(&ctx->nir->outputs,
1572 nir_intrinsic_base(instr));
1573 assert(var);
1574 if (var->data.location == FRAG_RESULT_COLOR)
1575 rt = MIDGARD_COLOR_RT0;
1576 else if (var->data.location >= FRAG_RESULT_DATA0)
1577 rt = MIDGARD_COLOR_RT0 + var->data.location -
1578 FRAG_RESULT_DATA0;
1579 else
1580 assert(0);
1581
1582 emit_fragment_store(ctx, reg, rt);
1583 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1584 /* We should have been vectorized, though we don't
1585 * currently check that st_vary is emitted only once
1586 * per slot (this is relevant, since there's not a mask
1587 * parameter available on the store [set to 0 by the
1588 * blob]). We do respect the component by adjusting the
1589 * swizzle. If this is a constant source, we'll need to
1590 * emit that explicitly. */
1591
1592 emit_explicit_constant(ctx, reg, reg);
1593
1594 unsigned dst_component = nir_intrinsic_component(instr);
1595 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1596
1597 midgard_instruction st = m_st_vary_32(reg, offset);
1598 st.load_store.arg_1 = 0x9E;
1599 st.load_store.arg_2 = 0x1E;
1600
1601 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1602 case nir_type_uint:
1603 case nir_type_bool:
1604 st.load_store.op = midgard_op_st_vary_32u;
1605 break;
1606 case nir_type_int:
1607 st.load_store.op = midgard_op_st_vary_32i;
1608 break;
1609 case nir_type_float:
1610 st.load_store.op = midgard_op_st_vary_32;
1611 break;
1612 default:
1613 unreachable("Attempted to store unknown type");
1614 break;
1615 }
1616
1617 /* nir_intrinsic_component(store_intr) encodes the
1618 * destination component start. Source component offset
1619 * adjustment is taken care of in
1620 * install_registers_instr(), when offset_swizzle() is
1621 * called.
1622 */
1623 unsigned src_component = COMPONENT_X;
1624
1625 assert(nr_comp > 0);
1626 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1627 st.swizzle[0][i] = src_component;
1628 if (i >= dst_component && i < dst_component + nr_comp - 1)
1629 src_component++;
1630 }
1631
1632 emit_mir_instruction(ctx, st);
1633 } else {
1634 DBG("Unknown store\n");
1635 assert(0);
1636 }
1637
1638 break;
1639
1640 /* Special case of store_output for lowered blend shaders */
1641 case nir_intrinsic_store_raw_output_pan:
1642 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1643 reg = nir_src_index(ctx, &instr->src[0]);
1644 emit_fragment_store(ctx, reg, ctx->blend_rt);
1645 break;
1646
1647 case nir_intrinsic_store_global:
1648 case nir_intrinsic_store_shared:
1649 reg = nir_src_index(ctx, &instr->src[0]);
1650 emit_explicit_constant(ctx, reg, reg);
1651
1652 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1653 break;
1654
1655 case nir_intrinsic_load_ssbo_address:
1656 emit_sysval_read(ctx, &instr->instr, 1, 0);
1657 break;
1658
1659 case nir_intrinsic_get_buffer_size:
1660 emit_sysval_read(ctx, &instr->instr, 1, 8);
1661 break;
1662
1663 case nir_intrinsic_load_viewport_scale:
1664 case nir_intrinsic_load_viewport_offset:
1665 case nir_intrinsic_load_num_work_groups:
1666 case nir_intrinsic_load_sampler_lod_parameters_pan:
1667 emit_sysval_read(ctx, &instr->instr, 3, 0);
1668 break;
1669
1670 case nir_intrinsic_load_work_group_id:
1671 case nir_intrinsic_load_local_invocation_id:
1672 emit_compute_builtin(ctx, instr);
1673 break;
1674
1675 case nir_intrinsic_load_vertex_id:
1676 case nir_intrinsic_load_instance_id:
1677 emit_vertex_builtin(ctx, instr);
1678 break;
1679
1680 case nir_intrinsic_memory_barrier_buffer:
1681 case nir_intrinsic_memory_barrier_shared:
1682 break;
1683
1684 case nir_intrinsic_control_barrier:
1685 schedule_barrier(ctx);
1686 emit_control_barrier(ctx);
1687 schedule_barrier(ctx);
1688 break;
1689
1690 default:
1691 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1692 assert(0);
1693 break;
1694 }
1695 }
1696
1697 static unsigned
1698 midgard_tex_format(enum glsl_sampler_dim dim)
1699 {
1700 switch (dim) {
1701 case GLSL_SAMPLER_DIM_1D:
1702 case GLSL_SAMPLER_DIM_BUF:
1703 return MALI_TEX_1D;
1704
1705 case GLSL_SAMPLER_DIM_2D:
1706 case GLSL_SAMPLER_DIM_EXTERNAL:
1707 case GLSL_SAMPLER_DIM_RECT:
1708 return MALI_TEX_2D;
1709
1710 case GLSL_SAMPLER_DIM_3D:
1711 return MALI_TEX_3D;
1712
1713 case GLSL_SAMPLER_DIM_CUBE:
1714 return MALI_TEX_CUBE;
1715
1716 default:
1717 DBG("Unknown sampler dim type\n");
1718 assert(0);
1719 return 0;
1720 }
1721 }
1722
1723 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1724 * was successful */
1725
1726 static bool
1727 pan_attach_constant_bias(
1728 compiler_context *ctx,
1729 nir_src lod,
1730 midgard_texture_word *word)
1731 {
1732 /* To attach as constant, it has to *be* constant */
1733
1734 if (!nir_src_is_const(lod))
1735 return false;
1736
1737 float f = nir_src_as_float(lod);
1738
1739 /* Break into fixed-point */
1740 signed lod_int = f;
1741 float lod_frac = f - lod_int;
1742
1743 /* Carry over negative fractions */
1744 if (lod_frac < 0.0) {
1745 lod_int--;
1746 lod_frac += 1.0;
1747 }
1748
1749 /* Encode */
1750 word->bias = float_to_ubyte(lod_frac);
1751 word->bias_int = lod_int;
1752
1753 return true;
1754 }
1755
1756 static void
1757 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1758 unsigned midgard_texop)
1759 {
1760 /* TODO */
1761 //assert (!instr->sampler);
1762
1763 int texture_index = instr->texture_index;
1764 int sampler_index = texture_index;
1765
1766 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1767 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1768
1769 midgard_instruction ins = {
1770 .type = TAG_TEXTURE_4,
1771 .mask = 0xF,
1772 .dest = nir_dest_index(&instr->dest),
1773 .src = { ~0, ~0, ~0, ~0 },
1774 .dest_type = dest_type,
1775 .swizzle = SWIZZLE_IDENTITY_4,
1776 .texture = {
1777 .op = midgard_texop,
1778 .format = midgard_tex_format(instr->sampler_dim),
1779 .texture_handle = texture_index,
1780 .sampler_handle = sampler_index,
1781 .shadow = instr->is_shadow,
1782 }
1783 };
1784
1785 if (instr->is_shadow && !instr->is_new_style_shadow)
1786 for (int i = 0; i < 4; ++i)
1787 ins.swizzle[0][i] = COMPONENT_X;
1788
1789 /* We may need a temporary for the coordinate */
1790
1791 bool needs_temp_coord =
1792 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1793 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1794 (instr->is_shadow);
1795
1796 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1797
1798 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1799 int index = nir_src_index(ctx, &instr->src[i].src);
1800 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1801 unsigned sz = nir_src_bit_size(instr->src[i].src);
1802 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1803
1804 switch (instr->src[i].src_type) {
1805 case nir_tex_src_coord: {
1806 emit_explicit_constant(ctx, index, index);
1807
1808 unsigned coord_mask = mask_of(instr->coord_components);
1809
1810 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1811
1812 if (flip_zw)
1813 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1814
1815 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1816 /* texelFetch is undefined on samplerCube */
1817 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1818
1819 /* For cubemaps, we use a special ld/st op to
1820 * select the face and copy the xy into the
1821 * texture register */
1822
1823 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1824 ld.src[1] = index;
1825 ld.src_types[1] = T;
1826 ld.mask = 0x3; /* xy */
1827 ld.load_store.arg_1 = 0x20;
1828 ld.swizzle[1][3] = COMPONENT_X;
1829 emit_mir_instruction(ctx, ld);
1830
1831 /* xyzw -> xyxx */
1832 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1833 ins.swizzle[1][3] = COMPONENT_X;
1834 } else if (needs_temp_coord) {
1835 /* mov coord_temp, coords */
1836 midgard_instruction mov = v_mov(index, coords);
1837 mov.mask = coord_mask;
1838
1839 if (flip_zw)
1840 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1841
1842 emit_mir_instruction(ctx, mov);
1843 } else {
1844 coords = index;
1845 }
1846
1847 ins.src[1] = coords;
1848 ins.src_types[1] = T;
1849
1850 /* Texelfetch coordinates uses all four elements
1851 * (xyz/index) regardless of texture dimensionality,
1852 * which means it's necessary to zero the unused
1853 * components to keep everything happy */
1854
1855 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1856 /* mov index.zw, #0, or generalized */
1857 midgard_instruction mov =
1858 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1859 mov.has_constants = true;
1860 mov.mask = coord_mask ^ 0xF;
1861 emit_mir_instruction(ctx, mov);
1862 }
1863
1864 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1865 /* Array component in w but NIR wants it in z,
1866 * but if we have a temp coord we already fixed
1867 * that up */
1868
1869 if (nr_components == 3) {
1870 ins.swizzle[1][2] = COMPONENT_Z;
1871 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1872 } else if (nr_components == 2) {
1873 ins.swizzle[1][2] =
1874 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1875 ins.swizzle[1][3] = COMPONENT_X;
1876 } else
1877 unreachable("Invalid texture 2D components");
1878 }
1879
1880 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1881 /* We zeroed */
1882 ins.swizzle[1][2] = COMPONENT_Z;
1883 ins.swizzle[1][3] = COMPONENT_W;
1884 }
1885
1886 break;
1887 }
1888
1889 case nir_tex_src_bias:
1890 case nir_tex_src_lod: {
1891 /* Try as a constant if we can */
1892
1893 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1894 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1895 break;
1896
1897 ins.texture.lod_register = true;
1898 ins.src[2] = index;
1899 ins.src_types[2] = T;
1900
1901 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1902 ins.swizzle[2][c] = COMPONENT_X;
1903
1904 emit_explicit_constant(ctx, index, index);
1905
1906 break;
1907 };
1908
1909 case nir_tex_src_offset: {
1910 ins.texture.offset_register = true;
1911 ins.src[3] = index;
1912 ins.src_types[3] = T;
1913
1914 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1915 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1916
1917 emit_explicit_constant(ctx, index, index);
1918 break;
1919 };
1920
1921 case nir_tex_src_comparator: {
1922 unsigned comp = COMPONENT_Z;
1923
1924 /* mov coord_temp.foo, coords */
1925 midgard_instruction mov = v_mov(index, coords);
1926 mov.mask = 1 << comp;
1927
1928 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1929 mov.swizzle[1][i] = COMPONENT_X;
1930
1931 emit_mir_instruction(ctx, mov);
1932 break;
1933 }
1934
1935 default: {
1936 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1937 assert(0);
1938 }
1939 }
1940 }
1941
1942 emit_mir_instruction(ctx, ins);
1943 }
1944
1945 static void
1946 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1947 {
1948 switch (instr->op) {
1949 case nir_texop_tex:
1950 case nir_texop_txb:
1951 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1952 break;
1953 case nir_texop_txl:
1954 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1955 break;
1956 case nir_texop_txf:
1957 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1958 break;
1959 case nir_texop_txs:
1960 emit_sysval_read(ctx, &instr->instr, 4, 0);
1961 break;
1962 default: {
1963 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1964 assert(0);
1965 }
1966 }
1967 }
1968
1969 static void
1970 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1971 {
1972 switch (instr->type) {
1973 case nir_jump_break: {
1974 /* Emit a branch out of the loop */
1975 struct midgard_instruction br = v_branch(false, false);
1976 br.branch.target_type = TARGET_BREAK;
1977 br.branch.target_break = ctx->current_loop_depth;
1978 emit_mir_instruction(ctx, br);
1979 break;
1980 }
1981
1982 default:
1983 DBG("Unknown jump type %d\n", instr->type);
1984 break;
1985 }
1986 }
1987
1988 static void
1989 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1990 {
1991 switch (instr->type) {
1992 case nir_instr_type_load_const:
1993 emit_load_const(ctx, nir_instr_as_load_const(instr));
1994 break;
1995
1996 case nir_instr_type_intrinsic:
1997 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1998 break;
1999
2000 case nir_instr_type_alu:
2001 emit_alu(ctx, nir_instr_as_alu(instr));
2002 break;
2003
2004 case nir_instr_type_tex:
2005 emit_tex(ctx, nir_instr_as_tex(instr));
2006 break;
2007
2008 case nir_instr_type_jump:
2009 emit_jump(ctx, nir_instr_as_jump(instr));
2010 break;
2011
2012 case nir_instr_type_ssa_undef:
2013 /* Spurious */
2014 break;
2015
2016 default:
2017 DBG("Unhandled instruction type\n");
2018 break;
2019 }
2020 }
2021
2022
2023 /* ALU instructions can inline or embed constants, which decreases register
2024 * pressure and saves space. */
2025
2026 #define CONDITIONAL_ATTACH(idx) { \
2027 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2028 \
2029 if (entry) { \
2030 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2031 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2032 } \
2033 }
2034
2035 static void
2036 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2037 {
2038 mir_foreach_instr_in_block(block, alu) {
2039 /* Other instructions cannot inline constants */
2040 if (alu->type != TAG_ALU_4) continue;
2041 if (alu->compact_branch) continue;
2042
2043 /* If there is already a constant here, we can do nothing */
2044 if (alu->has_constants) continue;
2045
2046 CONDITIONAL_ATTACH(0);
2047
2048 if (!alu->has_constants) {
2049 CONDITIONAL_ATTACH(1)
2050 } else if (!alu->inline_constant) {
2051 /* Corner case: _two_ vec4 constants, for instance with a
2052 * csel. For this case, we can only use a constant
2053 * register for one, we'll have to emit a move for the
2054 * other. */
2055
2056 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2057 unsigned scratch = make_compiler_temp(ctx);
2058
2059 if (entry) {
2060 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2061 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2062
2063 /* Set the source */
2064 alu->src[1] = scratch;
2065
2066 /* Inject us -before- the last instruction which set r31 */
2067 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2068 }
2069 }
2070 }
2071 }
2072
2073 /* Midgard supports two types of constants, embedded constants (128-bit) and
2074 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2075 * constants can be demoted to inline constants, for space savings and
2076 * sometimes a performance boost */
2077
2078 static void
2079 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2080 {
2081 mir_foreach_instr_in_block(block, ins) {
2082 if (!ins->has_constants) continue;
2083 if (ins->has_inline_constant) continue;
2084
2085 /* Blend constants must not be inlined by definition */
2086 if (ins->has_blend_constant) continue;
2087
2088 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2089 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2090 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2091
2092 if (!(is_16 || is_32))
2093 continue;
2094
2095 /* src1 cannot be an inline constant due to encoding
2096 * restrictions. So, if possible we try to flip the arguments
2097 * in that case */
2098
2099 int op = ins->alu.op;
2100
2101 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2102 alu_opcode_props[op].props & OP_COMMUTES) {
2103 mir_flip(ins);
2104 }
2105
2106 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2107 /* Component is from the swizzle. Take a nonzero component */
2108 assert(ins->mask);
2109 unsigned first_comp = ffs(ins->mask) - 1;
2110 unsigned component = ins->swizzle[1][first_comp];
2111
2112 /* Scale constant appropriately, if we can legally */
2113 int16_t scaled_constant = 0;
2114
2115 if (is_16) {
2116 scaled_constant = ins->constants.u16[component];
2117 } else if (midgard_is_integer_op(op)) {
2118 scaled_constant = ins->constants.u32[component];
2119
2120 /* Constant overflow after resize */
2121 if (scaled_constant != ins->constants.u32[component])
2122 continue;
2123 } else {
2124 float original = ins->constants.f32[component];
2125 scaled_constant = _mesa_float_to_half(original);
2126
2127 /* Check for loss of precision. If this is
2128 * mediump, we don't care, but for a highp
2129 * shader, we need to pay attention. NIR
2130 * doesn't yet tell us which mode we're in!
2131 * Practically this prevents most constants
2132 * from being inlined, sadly. */
2133
2134 float fp32 = _mesa_half_to_float(scaled_constant);
2135
2136 if (fp32 != original)
2137 continue;
2138 }
2139
2140 /* Should've been const folded */
2141 if (ins->src_abs[1] || ins->src_neg[1])
2142 continue;
2143
2144 /* Make sure that the constant is not itself a vector
2145 * by checking if all accessed values are the same. */
2146
2147 const midgard_constants *cons = &ins->constants;
2148 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2149
2150 bool is_vector = false;
2151 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2152
2153 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2154 /* We only care if this component is actually used */
2155 if (!(mask & (1 << c)))
2156 continue;
2157
2158 uint32_t test = is_16 ?
2159 cons->u16[ins->swizzle[1][c]] :
2160 cons->u32[ins->swizzle[1][c]];
2161
2162 if (test != value) {
2163 is_vector = true;
2164 break;
2165 }
2166 }
2167
2168 if (is_vector)
2169 continue;
2170
2171 /* Get rid of the embedded constant */
2172 ins->has_constants = false;
2173 ins->src[1] = ~0;
2174 ins->has_inline_constant = true;
2175 ins->inline_constant = scaled_constant;
2176 }
2177 }
2178 }
2179
2180 /* Dead code elimination for branches at the end of a block - only one branch
2181 * per block is legal semantically */
2182
2183 static void
2184 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2185 {
2186 bool branched = false;
2187
2188 mir_foreach_instr_in_block_safe(block, ins) {
2189 if (!midgard_is_branch_unit(ins->unit)) continue;
2190
2191 if (branched)
2192 mir_remove_instruction(ins);
2193
2194 branched = true;
2195 }
2196 }
2197
2198 /* We want to force the invert on AND/OR to the second slot to legalize into
2199 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2200 *
2201 * ~a & #b = ~a & ~(#~b)
2202 * ~a & b = b & ~a
2203 */
2204
2205 static void
2206 midgard_legalize_invert(compiler_context *ctx, midgard_block *block)
2207 {
2208 mir_foreach_instr_in_block(block, ins) {
2209 if (ins->type != TAG_ALU_4) continue;
2210
2211 if (ins->alu.op != midgard_alu_op_iand &&
2212 ins->alu.op != midgard_alu_op_ior) continue;
2213
2214 if (ins->src_invert[1] || !ins->src_invert[0]) continue;
2215
2216 if (ins->has_inline_constant) {
2217 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2218 * inverts on */
2219 ins->inline_constant = ~ins->inline_constant;
2220 ins->src_invert[1] = true;
2221 } else {
2222 /* Flip to the right invert order. Note
2223 * has_inline_constant false by assumption on the
2224 * branch, so flipping makes sense. */
2225 mir_flip(ins);
2226 }
2227 }
2228 }
2229
2230 static unsigned
2231 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2232 {
2233 /* Loop to ourselves */
2234 midgard_instruction *br = ctx->writeout_branch[rt];
2235 struct midgard_instruction ins = v_branch(false, false);
2236 ins.writeout = true;
2237 ins.writeout_depth = br->writeout_depth;
2238 ins.writeout_stencil = br->writeout_stencil;
2239 ins.branch.target_block = ctx->block_count - 1;
2240 ins.constants.u32[0] = br->constants.u32[0];
2241 memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types));
2242 emit_mir_instruction(ctx, ins);
2243
2244 ctx->current_block->epilogue = true;
2245 schedule_barrier(ctx);
2246 return ins.branch.target_block;
2247 }
2248
2249 static midgard_block *
2250 emit_block(compiler_context *ctx, nir_block *block)
2251 {
2252 midgard_block *this_block = ctx->after_block;
2253 ctx->after_block = NULL;
2254
2255 if (!this_block)
2256 this_block = create_empty_block(ctx);
2257
2258 list_addtail(&this_block->base.link, &ctx->blocks);
2259
2260 this_block->scheduled = false;
2261 ++ctx->block_count;
2262
2263 /* Set up current block */
2264 list_inithead(&this_block->base.instructions);
2265 ctx->current_block = this_block;
2266
2267 nir_foreach_instr(instr, block) {
2268 emit_instr(ctx, instr);
2269 ++ctx->instruction_count;
2270 }
2271
2272 return this_block;
2273 }
2274
2275 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2276
2277 static void
2278 emit_if(struct compiler_context *ctx, nir_if *nif)
2279 {
2280 midgard_block *before_block = ctx->current_block;
2281
2282 /* Speculatively emit the branch, but we can't fill it in until later */
2283 bool inv = false;
2284 EMIT(branch, true, true);
2285 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2286 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2287 then_branch->src_types[0] = nir_type_uint32;
2288 then_branch->branch.invert_conditional = !inv;
2289
2290 /* Emit the two subblocks. */
2291 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2292 midgard_block *end_then_block = ctx->current_block;
2293
2294 /* Emit a jump from the end of the then block to the end of the else */
2295 EMIT(branch, false, false);
2296 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2297
2298 /* Emit second block, and check if it's empty */
2299
2300 int else_idx = ctx->block_count;
2301 int count_in = ctx->instruction_count;
2302 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2303 midgard_block *end_else_block = ctx->current_block;
2304 int after_else_idx = ctx->block_count;
2305
2306 /* Now that we have the subblocks emitted, fix up the branches */
2307
2308 assert(then_block);
2309 assert(else_block);
2310
2311 if (ctx->instruction_count == count_in) {
2312 /* The else block is empty, so don't emit an exit jump */
2313 mir_remove_instruction(then_exit);
2314 then_branch->branch.target_block = after_else_idx;
2315 } else {
2316 then_branch->branch.target_block = else_idx;
2317 then_exit->branch.target_block = after_else_idx;
2318 }
2319
2320 /* Wire up the successors */
2321
2322 ctx->after_block = create_empty_block(ctx);
2323
2324 pan_block_add_successor(&before_block->base, &then_block->base);
2325 pan_block_add_successor(&before_block->base, &else_block->base);
2326
2327 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2328 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2329 }
2330
2331 static void
2332 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2333 {
2334 /* Remember where we are */
2335 midgard_block *start_block = ctx->current_block;
2336
2337 /* Allocate a loop number, growing the current inner loop depth */
2338 int loop_idx = ++ctx->current_loop_depth;
2339
2340 /* Get index from before the body so we can loop back later */
2341 int start_idx = ctx->block_count;
2342
2343 /* Emit the body itself */
2344 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2345
2346 /* Branch back to loop back */
2347 struct midgard_instruction br_back = v_branch(false, false);
2348 br_back.branch.target_block = start_idx;
2349 emit_mir_instruction(ctx, br_back);
2350
2351 /* Mark down that branch in the graph. */
2352 pan_block_add_successor(&start_block->base, &loop_block->base);
2353 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2354
2355 /* Find the index of the block about to follow us (note: we don't add
2356 * one; blocks are 0-indexed so we get a fencepost problem) */
2357 int break_block_idx = ctx->block_count;
2358
2359 /* Fix up the break statements we emitted to point to the right place,
2360 * now that we can allocate a block number for them */
2361 ctx->after_block = create_empty_block(ctx);
2362
2363 mir_foreach_block_from(ctx, start_block, _block) {
2364 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2365 if (ins->type != TAG_ALU_4) continue;
2366 if (!ins->compact_branch) continue;
2367
2368 /* We found a branch -- check the type to see if we need to do anything */
2369 if (ins->branch.target_type != TARGET_BREAK) continue;
2370
2371 /* It's a break! Check if it's our break */
2372 if (ins->branch.target_break != loop_idx) continue;
2373
2374 /* Okay, cool, we're breaking out of this loop.
2375 * Rewrite from a break to a goto */
2376
2377 ins->branch.target_type = TARGET_GOTO;
2378 ins->branch.target_block = break_block_idx;
2379
2380 pan_block_add_successor(_block, &ctx->after_block->base);
2381 }
2382 }
2383
2384 /* Now that we've finished emitting the loop, free up the depth again
2385 * so we play nice with recursion amid nested loops */
2386 --ctx->current_loop_depth;
2387
2388 /* Dump loop stats */
2389 ++ctx->loop_count;
2390 }
2391
2392 static midgard_block *
2393 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2394 {
2395 midgard_block *start_block = NULL;
2396
2397 foreach_list_typed(nir_cf_node, node, node, list) {
2398 switch (node->type) {
2399 case nir_cf_node_block: {
2400 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2401
2402 if (!start_block)
2403 start_block = block;
2404
2405 break;
2406 }
2407
2408 case nir_cf_node_if:
2409 emit_if(ctx, nir_cf_node_as_if(node));
2410 break;
2411
2412 case nir_cf_node_loop:
2413 emit_loop(ctx, nir_cf_node_as_loop(node));
2414 break;
2415
2416 case nir_cf_node_function:
2417 assert(0);
2418 break;
2419 }
2420 }
2421
2422 return start_block;
2423 }
2424
2425 /* Due to lookahead, we need to report the first tag executed in the command
2426 * stream and in branch targets. An initial block might be empty, so iterate
2427 * until we find one that 'works' */
2428
2429 static unsigned
2430 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2431 {
2432 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2433
2434 mir_foreach_block_from(ctx, initial_block, _v) {
2435 midgard_block *v = (midgard_block *) _v;
2436 if (v->quadword_count) {
2437 midgard_bundle *initial_bundle =
2438 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2439
2440 return initial_bundle->tag;
2441 }
2442 }
2443
2444 /* Default to a tag 1 which will break from the shader, in case we jump
2445 * to the exit block (i.e. `return` in a compute shader) */
2446
2447 return 1;
2448 }
2449
2450 /* For each fragment writeout instruction, generate a writeout loop to
2451 * associate with it */
2452
2453 static void
2454 mir_add_writeout_loops(compiler_context *ctx)
2455 {
2456 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2457 midgard_instruction *br = ctx->writeout_branch[rt];
2458 if (!br) continue;
2459
2460 unsigned popped = br->branch.target_block;
2461 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2462 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2463 br->branch.target_type = TARGET_GOTO;
2464
2465 /* If we have more RTs, we'll need to restore back after our
2466 * loop terminates */
2467
2468 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2469 midgard_instruction uncond = v_branch(false, false);
2470 uncond.branch.target_block = popped;
2471 uncond.branch.target_type = TARGET_GOTO;
2472 emit_mir_instruction(ctx, uncond);
2473 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2474 schedule_barrier(ctx);
2475 } else {
2476 /* We're last, so we can terminate here */
2477 br->last_writeout = true;
2478 }
2479 }
2480 }
2481
2482 int
2483 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2484 {
2485 struct util_dynarray *compiled = &program->compiled;
2486
2487 midgard_debug = debug_get_option_midgard_debug();
2488
2489 /* TODO: Bound against what? */
2490 compiler_context *ctx = rzalloc(NULL, compiler_context);
2491
2492 ctx->nir = nir;
2493 ctx->stage = nir->info.stage;
2494 ctx->is_blend = is_blend;
2495 ctx->alpha_ref = program->alpha_ref;
2496 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2497 ctx->quirks = midgard_get_quirks(gpu_id);
2498
2499 /* Start off with a safe cutoff, allowing usage of all 16 work
2500 * registers. Later, we'll promote uniform reads to uniform registers
2501 * if we determine it is beneficial to do so */
2502 ctx->uniform_cutoff = 8;
2503
2504 /* Initialize at a global (not block) level hash tables */
2505
2506 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2507 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2508
2509 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2510 * (so we don't accidentally duplicate the epilogue since mesa/st has
2511 * messed with our I/O quite a bit already) */
2512
2513 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2514
2515 if (ctx->stage == MESA_SHADER_VERTEX) {
2516 NIR_PASS_V(nir, nir_lower_viewport_transform);
2517 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2518 }
2519
2520 NIR_PASS_V(nir, nir_lower_var_copies);
2521 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2522 NIR_PASS_V(nir, nir_split_var_copies);
2523 NIR_PASS_V(nir, nir_lower_var_copies);
2524 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2525 NIR_PASS_V(nir, nir_lower_var_copies);
2526 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2527
2528 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2529 NIR_PASS_V(nir, nir_lower_ssbo);
2530
2531 /* Optimisation passes */
2532
2533 optimise_nir(nir, ctx->quirks, is_blend);
2534
2535 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2536 nir_print_shader(nir, stdout);
2537 }
2538
2539 /* Assign sysvals and counts, now that we're sure
2540 * (post-optimisation) */
2541
2542 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2543 program->sysval_count = ctx->sysvals.sysval_count;
2544 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2545
2546 nir_foreach_function(func, nir) {
2547 if (!func->impl)
2548 continue;
2549
2550 list_inithead(&ctx->blocks);
2551 ctx->block_count = 0;
2552 ctx->func = func;
2553 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2554
2555 emit_cf_list(ctx, &func->impl->body);
2556 free(ctx->already_emitted);
2557 break; /* TODO: Multi-function shaders */
2558 }
2559
2560 util_dynarray_init(compiled, NULL);
2561
2562 /* Per-block lowering before opts */
2563
2564 mir_foreach_block(ctx, _block) {
2565 midgard_block *block = (midgard_block *) _block;
2566 inline_alu_constants(ctx, block);
2567 embedded_to_inline_constant(ctx, block);
2568 }
2569 /* MIR-level optimizations */
2570
2571 bool progress = false;
2572
2573 do {
2574 progress = false;
2575 progress |= midgard_opt_dead_code_eliminate(ctx);
2576
2577 mir_foreach_block(ctx, _block) {
2578 midgard_block *block = (midgard_block *) _block;
2579 progress |= midgard_opt_copy_prop(ctx, block);
2580 progress |= midgard_opt_combine_projection(ctx, block);
2581 progress |= midgard_opt_varying_projection(ctx, block);
2582 }
2583 } while (progress);
2584
2585 mir_foreach_block(ctx, _block) {
2586 midgard_block *block = (midgard_block *) _block;
2587 midgard_lower_derivatives(ctx, block);
2588 midgard_legalize_invert(ctx, block);
2589 midgard_cull_dead_branch(ctx, block);
2590 }
2591
2592 if (ctx->stage == MESA_SHADER_FRAGMENT)
2593 mir_add_writeout_loops(ctx);
2594
2595 /* Analyze now that the code is known but before scheduling creates
2596 * pipeline registers which are harder to track */
2597 mir_analyze_helper_terminate(ctx);
2598 mir_analyze_helper_requirements(ctx);
2599
2600 /* Schedule! */
2601 midgard_schedule_program(ctx);
2602 mir_ra(ctx);
2603
2604 /* Now that all the bundles are scheduled and we can calculate block
2605 * sizes, emit actual branch instructions rather than placeholders */
2606
2607 int br_block_idx = 0;
2608
2609 mir_foreach_block(ctx, _block) {
2610 midgard_block *block = (midgard_block *) _block;
2611 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2612 for (int c = 0; c < bundle->instruction_count; ++c) {
2613 midgard_instruction *ins = bundle->instructions[c];
2614
2615 if (!midgard_is_branch_unit(ins->unit)) continue;
2616
2617 /* Parse some basic branch info */
2618 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2619 bool is_conditional = ins->branch.conditional;
2620 bool is_inverted = ins->branch.invert_conditional;
2621 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2622 bool is_writeout = ins->writeout;
2623
2624 /* Determine the block we're jumping to */
2625 int target_number = ins->branch.target_block;
2626
2627 /* Report the destination tag */
2628 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2629
2630 /* Count up the number of quadwords we're
2631 * jumping over = number of quadwords until
2632 * (br_block_idx, target_number) */
2633
2634 int quadword_offset = 0;
2635
2636 if (is_discard) {
2637 /* Ignored */
2638 } else if (target_number > br_block_idx) {
2639 /* Jump forward */
2640
2641 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2642 midgard_block *blk = mir_get_block(ctx, idx);
2643 assert(blk);
2644
2645 quadword_offset += blk->quadword_count;
2646 }
2647 } else {
2648 /* Jump backwards */
2649
2650 for (int idx = br_block_idx; idx >= target_number; --idx) {
2651 midgard_block *blk = mir_get_block(ctx, idx);
2652 assert(blk);
2653
2654 quadword_offset -= blk->quadword_count;
2655 }
2656 }
2657
2658 /* Unconditional extended branches (far jumps)
2659 * have issues, so we always use a conditional
2660 * branch, setting the condition to always for
2661 * unconditional. For compact unconditional
2662 * branches, cond isn't used so it doesn't
2663 * matter what we pick. */
2664
2665 midgard_condition cond =
2666 !is_conditional ? midgard_condition_always :
2667 is_inverted ? midgard_condition_false :
2668 midgard_condition_true;
2669
2670 midgard_jmp_writeout_op op =
2671 is_discard ? midgard_jmp_writeout_op_discard :
2672 is_writeout ? midgard_jmp_writeout_op_writeout :
2673 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2674 midgard_jmp_writeout_op_branch_cond;
2675
2676 if (!is_compact) {
2677 midgard_branch_extended branch =
2678 midgard_create_branch_extended(
2679 cond, op,
2680 dest_tag,
2681 quadword_offset);
2682
2683 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2684 } else if (is_conditional || is_discard) {
2685 midgard_branch_cond branch = {
2686 .op = op,
2687 .dest_tag = dest_tag,
2688 .offset = quadword_offset,
2689 .cond = cond
2690 };
2691
2692 assert(branch.offset == quadword_offset);
2693
2694 memcpy(&ins->br_compact, &branch, sizeof(branch));
2695 } else {
2696 assert(op == midgard_jmp_writeout_op_branch_uncond);
2697
2698 midgard_branch_uncond branch = {
2699 .op = op,
2700 .dest_tag = dest_tag,
2701 .offset = quadword_offset,
2702 .unknown = 1
2703 };
2704
2705 assert(branch.offset == quadword_offset);
2706
2707 memcpy(&ins->br_compact, &branch, sizeof(branch));
2708 }
2709 }
2710 }
2711
2712 ++br_block_idx;
2713 }
2714
2715 /* Emit flat binary from the instruction arrays. Iterate each block in
2716 * sequence. Save instruction boundaries such that lookahead tags can
2717 * be assigned easily */
2718
2719 /* Cache _all_ bundles in source order for lookahead across failed branches */
2720
2721 int bundle_count = 0;
2722 mir_foreach_block(ctx, _block) {
2723 midgard_block *block = (midgard_block *) _block;
2724 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2725 }
2726 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2727 int bundle_idx = 0;
2728 mir_foreach_block(ctx, _block) {
2729 midgard_block *block = (midgard_block *) _block;
2730 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2731 source_order_bundles[bundle_idx++] = bundle;
2732 }
2733 }
2734
2735 int current_bundle = 0;
2736
2737 /* Midgard prefetches instruction types, so during emission we
2738 * need to lookahead. Unless this is the last instruction, in
2739 * which we return 1. */
2740
2741 mir_foreach_block(ctx, _block) {
2742 midgard_block *block = (midgard_block *) _block;
2743 mir_foreach_bundle_in_block(block, bundle) {
2744 int lookahead = 1;
2745
2746 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2747 lookahead = source_order_bundles[current_bundle + 1]->tag;
2748
2749 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
2750 ++current_bundle;
2751 }
2752
2753 /* TODO: Free deeper */
2754 //util_dynarray_fini(&block->instructions);
2755 }
2756
2757 free(source_order_bundles);
2758
2759 /* Report the very first tag executed */
2760 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2761
2762 /* Deal with off-by-one related to the fencepost problem */
2763 program->work_register_count = ctx->work_registers + 1;
2764 program->uniform_cutoff = ctx->uniform_cutoff;
2765
2766 program->blend_patch_offset = ctx->blend_constant_offset;
2767 program->tls_size = ctx->tls_size;
2768
2769 if (midgard_debug & MIDGARD_DBG_SHADERS)
2770 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2771
2772 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2773 unsigned nr_bundles = 0, nr_ins = 0;
2774
2775 /* Count instructions and bundles */
2776
2777 mir_foreach_block(ctx, _block) {
2778 midgard_block *block = (midgard_block *) _block;
2779 nr_bundles += util_dynarray_num_elements(
2780 &block->bundles, midgard_bundle);
2781
2782 mir_foreach_bundle_in_block(block, bun)
2783 nr_ins += bun->instruction_count;
2784 }
2785
2786 /* Calculate thread count. There are certain cutoffs by
2787 * register count for thread count */
2788
2789 unsigned nr_registers = program->work_register_count;
2790
2791 unsigned nr_threads =
2792 (nr_registers <= 4) ? 4 :
2793 (nr_registers <= 8) ? 2 :
2794 1;
2795
2796 /* Dump stats */
2797
2798 fprintf(stderr, "shader%d - %s shader: "
2799 "%u inst, %u bundles, %u quadwords, "
2800 "%u registers, %u threads, %u loops, "
2801 "%u:%u spills:fills\n",
2802 SHADER_DB_COUNT++,
2803 ctx->is_blend ? "PAN_SHADER_BLEND" :
2804 gl_shader_stage_name(ctx->stage),
2805 nr_ins, nr_bundles, ctx->quadword_count,
2806 nr_registers, nr_threads,
2807 ctx->loop_count,
2808 ctx->spills, ctx->fills);
2809 }
2810
2811 ralloc_free(ctx);
2812
2813 return 0;
2814 }