2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
51 #include "panfrost-quirks.h"
52 #include "panfrost/util/pan_lower_framebuffer.h"
54 #include "disassemble.h"
56 static const struct debug_named_value debug_options
[] = {
57 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
58 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
63 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
65 unsigned SHADER_DB_COUNT
= 0;
67 int midgard_debug
= 0;
69 #define DBG(fmt, ...) \
70 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
71 fprintf(stderr, "%s:%d: "fmt, \
72 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 static midgard_block
*
74 create_empty_block(compiler_context
*ctx
)
76 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
78 blk
->base
.predecessors
= _mesa_set_create(blk
,
80 _mesa_key_pointer_equal
);
82 blk
->base
.name
= ctx
->block_source_count
++;
88 schedule_barrier(compiler_context
*ctx
)
90 midgard_block
*temp
= ctx
->after_block
;
91 ctx
->after_block
= create_empty_block(ctx
);
93 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
94 list_inithead(&ctx
->after_block
->base
.instructions
);
95 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
96 ctx
->current_block
= ctx
->after_block
;
97 ctx
->after_block
= temp
;
100 /* Helpers to generate midgard_instruction's using macro magic, since every
101 * driver seems to do it that way */
103 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
105 #define M_LOAD_STORE(name, store, T) \
106 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
107 midgard_instruction i = { \
108 .type = TAG_LOAD_STORE_4, \
111 .src = { ~0, ~0, ~0, ~0 }, \
112 .swizzle = SWIZZLE_IDENTITY_4, \
114 .op = midgard_op_##name, \
121 i.src_types[0] = T; \
130 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
131 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
133 M_LOAD(ld_attr_32
, nir_type_uint32
);
134 M_LOAD(ld_vary_32
, nir_type_uint32
);
135 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
136 M_LOAD(ld_int4
, nir_type_uint32
);
137 M_STORE(st_int4
, nir_type_uint32
);
138 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
139 M_LOAD(ld_color_buffer_as_fp16
, nir_type_float16
);
140 M_STORE(st_vary_32
, nir_type_uint32
);
141 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
142 M_LOAD(ld_compute_id
, nir_type_uint32
);
144 static midgard_instruction
145 v_branch(bool conditional
, bool invert
)
147 midgard_instruction ins
= {
149 .unit
= ALU_ENAB_BRANCH
,
150 .compact_branch
= true,
152 .conditional
= conditional
,
153 .invert_conditional
= invert
156 .src
= { ~0, ~0, ~0, ~0 },
162 static midgard_branch_extended
163 midgard_create_branch_extended( midgard_condition cond
,
164 midgard_jmp_writeout_op op
,
166 signed quadword_offset
)
168 /* The condition code is actually a LUT describing a function to
169 * combine multiple condition codes. However, we only support a single
170 * condition code at the moment, so we just duplicate over a bunch of
173 uint16_t duplicated_cond
=
183 midgard_branch_extended branch
= {
185 .dest_tag
= dest_tag
,
186 .offset
= quadword_offset
,
187 .cond
= duplicated_cond
194 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
196 ins
->has_constants
= true;
197 memcpy(&ins
->constants
, constants
, 16);
201 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
203 return glsl_count_attribute_slots(type
, false);
206 /* Lower fdot2 to a vector multiplication followed by channel addition */
208 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
210 if (alu
->op
!= nir_op_fdot2
)
213 b
->cursor
= nir_before_instr(&alu
->instr
);
215 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
216 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
218 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
220 nir_ssa_def
*sum
= nir_fadd(b
,
221 nir_channel(b
, product
, 0),
222 nir_channel(b
, product
, 1));
224 /* Replace the fdot2 with this sum */
225 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
229 midgard_nir_lower_fdot2(nir_shader
*shader
)
231 bool progress
= false;
233 nir_foreach_function(function
, shader
) {
234 if (!function
->impl
) continue;
237 nir_builder
*b
= &_b
;
238 nir_builder_init(b
, function
->impl
);
240 nir_foreach_block(block
, function
->impl
) {
241 nir_foreach_instr_safe(instr
, block
) {
242 if (instr
->type
!= nir_instr_type_alu
) continue;
244 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
245 midgard_nir_lower_fdot2_body(b
, alu
);
251 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
258 static const nir_variable
*
259 search_var(struct exec_list
*vars
, unsigned driver_loc
)
261 nir_foreach_variable(var
, vars
) {
262 if (var
->data
.driver_location
== driver_loc
)
269 /* Midgard can write all of color, depth and stencil in a single writeout
270 * operation, so we merge depth/stencil stores with color stores.
271 * If there are no color stores, we add a write to the "depth RT".
274 midgard_nir_lower_zs_store(nir_shader
*nir
)
276 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
279 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
281 nir_foreach_variable(var
, &nir
->outputs
) {
282 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
284 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
288 if (!z_var
&& !s_var
)
291 bool progress
= false;
293 nir_foreach_function(function
, nir
) {
294 if (!function
->impl
) continue;
296 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
;
298 nir_foreach_block(block
, function
->impl
) {
299 nir_foreach_instr_safe(instr
, block
) {
300 if (instr
->type
!= nir_instr_type_intrinsic
)
303 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
304 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
307 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
312 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
319 if (!z_store
&& !s_store
) continue;
321 bool replaced
= false;
323 nir_foreach_block(block
, function
->impl
) {
324 nir_foreach_instr_safe(instr
, block
) {
325 if (instr
->type
!= nir_instr_type_intrinsic
)
328 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
329 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
332 const nir_variable
*var
= search_var(&nir
->outputs
, nir_intrinsic_base(intr
));
335 if (var
->data
.location
!= FRAG_RESULT_COLOR
&&
336 var
->data
.location
< FRAG_RESULT_DATA0
)
339 assert(nir_src_is_const(intr
->src
[1]) && "no indirect outputs");
342 nir_builder_init(&b
, function
->impl
);
344 assert(!z_store
|| z_store
->instr
.block
== instr
->block
);
345 assert(!s_store
|| s_store
->instr
.block
== instr
->block
);
346 b
.cursor
= nir_after_block_before_jump(instr
->block
);
348 nir_intrinsic_instr
*combined_store
;
349 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
351 combined_store
->num_components
= intr
->src
[0].ssa
->num_components
;
353 nir_intrinsic_set_base(combined_store
, nir_intrinsic_base(intr
));
355 unsigned writeout
= PAN_WRITEOUT_C
;
357 writeout
|= PAN_WRITEOUT_Z
;
359 writeout
|= PAN_WRITEOUT_S
;
361 nir_intrinsic_set_component(combined_store
, writeout
);
363 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
365 struct nir_ssa_def
*src
[4] = {
368 z_store
? z_store
->src
[0].ssa
: zero
,
369 s_store
? s_store
->src
[0].ssa
: zero
,
372 for (int i
= 0; i
< 4; ++i
)
373 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
375 nir_builder_instr_insert(&b
, &combined_store
->instr
);
377 nir_instr_remove(instr
);
383 /* Insert a store to the depth RT (0xff) if needed */
386 nir_builder_init(&b
, function
->impl
);
388 nir_block
*block
= NULL
;
389 if (z_store
&& s_store
)
390 assert(z_store
->instr
.block
== s_store
->instr
.block
);
393 block
= z_store
->instr
.block
;
395 block
= s_store
->instr
.block
;
397 b
.cursor
= nir_after_block_before_jump(block
);
399 nir_intrinsic_instr
*combined_store
;
400 combined_store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_combined_output_pan
);
402 combined_store
->num_components
= 4;
404 nir_intrinsic_set_base(combined_store
, 0);
406 unsigned writeout
= 0;
408 writeout
|= PAN_WRITEOUT_Z
;
410 writeout
|= PAN_WRITEOUT_S
;
412 nir_intrinsic_set_component(combined_store
, writeout
);
414 struct nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
416 struct nir_ssa_def
*src
[4] = {
417 nir_imm_vec4(&b
, 0, 0, 0, 0),
419 z_store
? z_store
->src
[0].ssa
: zero
,
420 s_store
? s_store
->src
[0].ssa
: zero
,
423 for (int i
= 0; i
< 4; ++i
)
424 combined_store
->src
[i
] = nir_src_for_ssa(src
[i
]);
426 nir_builder_instr_insert(&b
, &combined_store
->instr
);
430 nir_instr_remove(&z_store
->instr
);
433 nir_instr_remove(&s_store
->instr
);
435 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
442 /* Flushes undefined values to zero */
445 optimise_nir(nir_shader
*nir
, unsigned quirks
, bool is_blend
)
448 unsigned lower_flrp
=
449 (nir
->options
->lower_flrp16
? 16 : 0) |
450 (nir
->options
->lower_flrp32
? 32 : 0) |
451 (nir
->options
->lower_flrp64
? 64 : 0);
453 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
454 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
456 nir_lower_tex_options lower_tex_options
= {
457 .lower_txs_lod
= true,
459 .lower_tex_without_implicit_lod
=
460 (quirks
& MIDGARD_EXPLICIT_LOD
),
462 /* TODO: we have native gradient.. */
466 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
468 /* Must lower fdot2 after tex is lowered */
469 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
471 /* T720 is broken. */
473 if (quirks
& MIDGARD_BROKEN_LOD
)
474 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
476 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_early
);
481 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
482 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
484 NIR_PASS(progress
, nir
, nir_copy_prop
);
485 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
486 NIR_PASS(progress
, nir
, nir_opt_dce
);
487 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
488 NIR_PASS(progress
, nir
, nir_opt_cse
);
489 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
490 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
491 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
493 if (lower_flrp
!= 0) {
494 bool lower_flrp_progress
= false;
495 NIR_PASS(lower_flrp_progress
,
499 false /* always_precise */,
500 nir
->options
->lower_ffma
);
501 if (lower_flrp_progress
) {
502 NIR_PASS(progress
, nir
,
503 nir_opt_constant_folding
);
507 /* Nothing should rematerialize any flrps, so we only
508 * need to do this lowering once.
513 NIR_PASS(progress
, nir
, nir_opt_undef
);
514 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
516 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
519 nir_var_function_temp
);
521 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
524 /* Run after opts so it can hit more */
526 NIR_PASS(progress
, nir
, nir_fuse_io_16
);
528 /* Must be run at the end to prevent creation of fsin/fcos ops */
529 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
534 NIR_PASS(progress
, nir
, nir_opt_dce
);
535 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
536 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
537 NIR_PASS(progress
, nir
, nir_copy_prop
);
540 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
541 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
543 /* We implement booleans as 32-bit 0/~0 */
544 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
546 /* Now that booleans are lowered, we can run out late opts */
547 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
548 NIR_PASS(progress
, nir
, midgard_nir_cancel_inot
);
550 NIR_PASS(progress
, nir
, nir_copy_prop
);
551 NIR_PASS(progress
, nir
, nir_opt_dce
);
553 /* Take us out of SSA */
554 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
555 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
557 /* We are a vector architecture; write combine where possible */
558 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
559 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
561 NIR_PASS(progress
, nir
, nir_opt_dce
);
564 /* Do not actually emit a load; instead, cache the constant for inlining */
567 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
569 nir_ssa_def def
= instr
->def
;
571 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
573 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
575 #define RAW_CONST_COPY(bits) \
576 nir_const_value_to_array(consts->u##bits, instr->value, \
577 instr->def.num_components, u##bits)
579 switch (instr
->def
.bit_size
) {
593 unreachable("Invalid bit_size for load_const instruction\n");
596 /* Shifted for SSA, +1 for off-by-one */
597 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
600 /* Normally constants are embedded implicitly, but for I/O and such we have to
601 * explicitly emit a move with the constant source */
604 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
606 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
608 if (constant_value
) {
609 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
610 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
611 emit_mir_instruction(ctx
, ins
);
616 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
618 unsigned comp
= src
->swizzle
[0];
620 for (unsigned c
= 1; c
< nr_components
; ++c
) {
621 if (src
->swizzle
[c
] != comp
)
628 #define ALU_CASE(nir, _op) \
630 op = midgard_alu_op_##_op; \
631 assert(src_bitsize == dst_bitsize); \
634 #define ALU_CASE_RTZ(nir, _op) \
636 op = midgard_alu_op_##_op; \
637 roundmode = MIDGARD_RTZ; \
640 #define ALU_CHECK_CMP(sext) \
641 assert(src_bitsize == 16 || src_bitsize == 32); \
642 assert(dst_bitsize == 16 || dst_bitsize == 32); \
644 #define ALU_CASE_BCAST(nir, _op, count) \
646 op = midgard_alu_op_##_op; \
647 broadcast_swizzle = count; \
648 ALU_CHECK_CMP(true); \
651 #define ALU_CASE_CMP(nir, _op, sext) \
653 op = midgard_alu_op_##_op; \
654 ALU_CHECK_CMP(sext); \
657 /* Analyze the sizes of the dest and inputs to determine reg mode. */
659 static midgard_reg_mode
660 reg_mode_for_nir(nir_alu_instr
*instr
)
662 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
663 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
664 unsigned max_bitsize
= MAX2(src_bitsize
, dst_bitsize
);
666 /* We don't have fp16 LUTs, so we'll want to emit code like:
668 * vlut.fsinr hr0, hr0
670 * where both input and output are 16-bit but the operation is carried
682 max_bitsize
= MAX2(max_bitsize
, 32);
685 /* These get lowered to moves */
686 case nir_op_pack_32_4x8
:
689 case nir_op_pack_32_2x16
:
697 switch (max_bitsize
) {
698 /* Use 16 pipe for 8 since we don't support vec16 yet */
701 return midgard_reg_mode_16
;
703 return midgard_reg_mode_32
;
705 return midgard_reg_mode_64
;
707 unreachable("Invalid bit size");
711 /* Compare mir_lower_invert */
713 nir_accepts_inot(nir_op op
, unsigned src
)
717 case nir_op_iand
: /* TODO: b2f16 */
721 /* Only the condition */
729 mir_accept_dest_mod(compiler_context
*ctx
, nir_dest
**dest
, nir_op op
)
731 if (pan_has_dest_mod(dest
, op
)) {
732 assert((*dest
)->is_ssa
);
733 BITSET_SET(ctx
->already_emitted
, (*dest
)->ssa
.index
);
741 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
, bool *abs
, bool *neg
, bool *not, enum midgard_roundmode
*roundmode
, bool is_int
, unsigned bcast_count
)
743 nir_alu_src src
= instr
->src
[i
];
746 if (pan_has_source_mod(&src
, nir_op_fneg
))
749 if (pan_has_source_mod(&src
, nir_op_fabs
))
753 if (nir_accepts_inot(instr
->op
, i
) && pan_has_source_mod(&src
, nir_op_inot
))
757 if (pan_has_source_mod(&src
, nir_op_fround_even
))
758 *roundmode
= MIDGARD_RTE
;
760 if (pan_has_source_mod(&src
, nir_op_ftrunc
))
761 *roundmode
= MIDGARD_RTZ
;
763 if (pan_has_source_mod(&src
, nir_op_ffloor
))
764 *roundmode
= MIDGARD_RTN
;
766 if (pan_has_source_mod(&src
, nir_op_fceil
))
767 *roundmode
= MIDGARD_RTP
;
770 unsigned bits
= nir_src_bit_size(src
.src
);
772 ins
->src
[to
] = nir_src_index(NULL
, &src
.src
);
773 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
775 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
776 ins
->swizzle
[to
][c
] = src
.swizzle
[
777 (!bcast_count
|| c
< bcast_count
) ? c
:
782 /* Midgard features both fcsel and icsel, depending on whether you want int or
783 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
784 * we should emit an int or float csel depending on what modifiers could be
785 * placed. In the absense of modifiers, this is probably arbitrary. */
788 mir_is_bcsel_float(nir_alu_instr
*instr
)
791 nir_op_i2i8
, nir_op_i2i16
,
792 nir_op_i2i32
, nir_op_i2i64
795 nir_op floatmods
[] = {
796 nir_op_fabs
, nir_op_fneg
,
797 nir_op_f2f16
, nir_op_f2f32
,
801 nir_op floatdestmods
[] = {
802 nir_op_fsat
, nir_op_fsat_signed
, nir_op_fclamp_pos
,
803 nir_op_f2f16
, nir_op_f2f32
808 for (unsigned i
= 1; i
< 3; ++i
) {
809 nir_alu_src s
= instr
->src
[i
];
810 for (unsigned q
= 0; q
< ARRAY_SIZE(intmods
); ++q
) {
811 if (pan_has_source_mod(&s
, intmods
[q
]))
816 for (unsigned i
= 1; i
< 3; ++i
) {
817 nir_alu_src s
= instr
->src
[i
];
818 for (unsigned q
= 0; q
< ARRAY_SIZE(floatmods
); ++q
) {
819 if (pan_has_source_mod(&s
, floatmods
[q
]))
824 for (unsigned q
= 0; q
< ARRAY_SIZE(floatdestmods
); ++q
) {
825 nir_dest
*dest
= &instr
->dest
.dest
;
826 if (pan_has_dest_mod(&dest
, floatdestmods
[q
]))
834 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
836 nir_dest
*dest
= &instr
->dest
.dest
;
838 if (dest
->is_ssa
&& BITSET_TEST(ctx
->already_emitted
, dest
->ssa
.index
))
841 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
842 * is handled elsewhere */
844 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
845 midgard_emit_derivatives(ctx
, instr
);
849 bool is_ssa
= dest
->is_ssa
;
851 unsigned nr_components
= nir_dest_num_components(*dest
);
852 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
855 /* Number of components valid to check for the instruction (the rest
856 * will be forced to the last), or 0 to use as-is. Relevant as
857 * ball-type instructions have a channel count in NIR but are all vec4
860 unsigned broadcast_swizzle
= 0;
862 /* What register mode should we operate in? */
863 midgard_reg_mode reg_mode
=
864 reg_mode_for_nir(instr
);
866 /* Should we swap arguments? */
867 bool flip_src12
= false;
869 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
870 unsigned dst_bitsize
= nir_dest_bit_size(*dest
);
872 enum midgard_roundmode roundmode
= MIDGARD_RTE
;
875 ALU_CASE(fadd
, fadd
);
876 ALU_CASE(fmul
, fmul
);
877 ALU_CASE(fmin
, fmin
);
878 ALU_CASE(fmax
, fmax
);
879 ALU_CASE(imin
, imin
);
880 ALU_CASE(imax
, imax
);
881 ALU_CASE(umin
, umin
);
882 ALU_CASE(umax
, umax
);
883 ALU_CASE(ffloor
, ffloor
);
884 ALU_CASE(fround_even
, froundeven
);
885 ALU_CASE(ftrunc
, ftrunc
);
886 ALU_CASE(fceil
, fceil
);
887 ALU_CASE(fdot3
, fdot3
);
888 ALU_CASE(fdot4
, fdot4
);
889 ALU_CASE(iadd
, iadd
);
890 ALU_CASE(isub
, isub
);
891 ALU_CASE(imul
, imul
);
893 /* Zero shoved as second-arg */
894 ALU_CASE(iabs
, iabsdiff
);
898 ALU_CASE_CMP(feq32
, feq
, false);
899 ALU_CASE_CMP(fne32
, fne
, false);
900 ALU_CASE_CMP(flt32
, flt
, false);
901 ALU_CASE_CMP(ieq32
, ieq
, true);
902 ALU_CASE_CMP(ine32
, ine
, true);
903 ALU_CASE_CMP(ilt32
, ilt
, true);
904 ALU_CASE_CMP(ult32
, ult
, false);
906 /* We don't have a native b2f32 instruction. Instead, like many
907 * GPUs, we exploit booleans as 0/~0 for false/true, and
908 * correspondingly AND
909 * by 1.0 to do the type conversion. For the moment, prime us
912 * iand [whatever], #0
914 * At the end of emit_alu (as MIR), we'll fix-up the constant
917 ALU_CASE_CMP(b2f32
, iand
, true);
918 ALU_CASE_CMP(b2f16
, iand
, true);
919 ALU_CASE_CMP(b2i32
, iand
, true);
921 /* Likewise, we don't have a dedicated f2b32 instruction, but
922 * we can do a "not equal to 0.0" test. */
924 ALU_CASE_CMP(f2b32
, fne
, false);
925 ALU_CASE_CMP(i2b32
, ine
, true);
927 ALU_CASE(frcp
, frcp
);
928 ALU_CASE(frsq
, frsqrt
);
929 ALU_CASE(fsqrt
, fsqrt
);
930 ALU_CASE(fexp2
, fexp2
);
931 ALU_CASE(flog2
, flog2
);
933 ALU_CASE_RTZ(f2i64
, f2i_rte
);
934 ALU_CASE_RTZ(f2u64
, f2u_rte
);
935 ALU_CASE_RTZ(i2f64
, i2f_rte
);
936 ALU_CASE_RTZ(u2f64
, u2f_rte
);
938 ALU_CASE_RTZ(f2i32
, f2i_rte
);
939 ALU_CASE_RTZ(f2u32
, f2u_rte
);
940 ALU_CASE_RTZ(i2f32
, i2f_rte
);
941 ALU_CASE_RTZ(u2f32
, u2f_rte
);
943 ALU_CASE_RTZ(f2i8
, f2i_rte
);
944 ALU_CASE_RTZ(f2u8
, f2u_rte
);
946 ALU_CASE_RTZ(f2i16
, f2i_rte
);
947 ALU_CASE_RTZ(f2u16
, f2u_rte
);
948 ALU_CASE_RTZ(i2f16
, i2f_rte
);
949 ALU_CASE_RTZ(u2f16
, u2f_rte
);
951 ALU_CASE(fsin
, fsin
);
952 ALU_CASE(fcos
, fcos
);
954 /* We'll get 0 in the second arg, so:
955 * ~a = ~(a | 0) = nor(a, 0) */
956 ALU_CASE(inot
, inor
);
957 ALU_CASE(iand
, iand
);
959 ALU_CASE(ixor
, ixor
);
960 ALU_CASE(ishl
, ishl
);
961 ALU_CASE(ishr
, iasr
);
962 ALU_CASE(ushr
, ilsr
);
964 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
965 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
966 ALU_CASE_CMP(b32all_fequal4
, fball_eq
, true);
968 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
969 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
970 ALU_CASE_CMP(b32any_fnequal4
, fbany_neq
, true);
972 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
973 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
974 ALU_CASE_CMP(b32all_iequal4
, iball_eq
, true);
976 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
977 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
978 ALU_CASE_CMP(b32any_inequal4
, ibany_neq
, true);
980 /* Source mods will be shoved in later */
981 ALU_CASE(fabs
, fmov
);
982 ALU_CASE(fneg
, fmov
);
983 ALU_CASE(fsat
, fmov
);
984 ALU_CASE(fsat_signed
, fmov
);
985 ALU_CASE(fclamp_pos
, fmov
);
987 /* For size conversion, we use a move. Ideally though we would squash
988 * these ops together; maybe that has to happen after in NIR as part of
989 * propagation...? An earlier algebraic pass ensured we step down by
990 * only / exactly one size. If stepping down, we use a dest override to
991 * reduce the size; if stepping up, we use a larger-sized move with a
992 * half source and a sign/zero-extension modifier */
1004 case nir_op_f2f64
: {
1005 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
1006 instr
->op
== nir_op_f2f64
)
1007 op
= midgard_alu_op_fmov
;
1009 op
= midgard_alu_op_imov
;
1014 /* For greater-or-equal, we lower to less-or-equal and flip the
1020 case nir_op_uge32
: {
1022 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1023 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1024 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1025 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1029 ALU_CHECK_CMP(false);
1033 case nir_op_b32csel
: {
1034 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1035 bool is_float
= mir_is_bcsel_float(instr
);
1037 (mixed
? midgard_alu_op_fcsel_v
: midgard_alu_op_fcsel
) :
1038 (mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
);
1043 case nir_op_unpack_32_2x16
:
1044 case nir_op_unpack_32_4x8
:
1045 case nir_op_pack_32_2x16
:
1046 case nir_op_pack_32_4x8
: {
1047 op
= midgard_alu_op_imov
;
1052 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1057 /* Promote imov to fmov if it might help inline a constant */
1058 if (op
== midgard_alu_op_imov
&& nir_src_is_const(instr
->src
[0].src
)
1059 && nir_src_bit_size(instr
->src
[0].src
) == 32
1060 && nir_is_same_comp_swizzle(instr
->src
[0].swizzle
,
1061 nir_src_num_components(instr
->src
[0].src
))) {
1062 op
= midgard_alu_op_fmov
;
1065 /* Midgard can perform certain modifiers on output of an ALU op */
1067 unsigned outmod
= 0;
1068 bool is_int
= midgard_is_integer_op(op
);
1070 if (midgard_is_integer_out_op(op
)) {
1071 outmod
= midgard_outmod_int_wrap
;
1072 } else if (instr
->op
== nir_op_fsat
) {
1073 outmod
= midgard_outmod_sat
;
1074 } else if (instr
->op
== nir_op_fsat_signed
) {
1075 outmod
= midgard_outmod_sat_signed
;
1076 } else if (instr
->op
== nir_op_fclamp_pos
) {
1077 outmod
= midgard_outmod_pos
;
1080 /* Fetch unit, quirks, etc information */
1081 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1082 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1084 /* Look for floating point mods. We have the mods fsat, fsat_signed,
1085 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
1087 * fsat_signed(fpos(x)) = fsat(x)
1088 * fsat_signed(fsat(x)) = fsat(x)
1089 * fpos(fsat_signed(x)) = fsat(x)
1090 * fpos(fsat(x)) = fsat(x)
1091 * fsat(fsat_signed(x)) = fsat(x)
1092 * fsat(fpos(x)) = fsat(x)
1094 * So by cases any composition of output modifiers is equivalent to
1098 if (!is_int
&& !(opcode_props
& OP_TYPE_CONVERT
)) {
1099 bool fpos
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fclamp_pos
);
1100 bool fsat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat
);
1101 bool ssat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat_signed
);
1102 bool prior
= (outmod
!= midgard_outmod_none
);
1103 int count
= (int) prior
+ (int) fpos
+ (int) ssat
+ (int) fsat
;
1105 outmod
= ((count
> 1) || fsat
) ? midgard_outmod_sat
:
1106 fpos
? midgard_outmod_pos
:
1107 ssat
? midgard_outmod_sat_signed
:
1111 midgard_instruction ins
= {
1113 .dest
= nir_dest_index(dest
),
1114 .dest_type
= nir_op_infos
[instr
->op
].output_type
1115 | nir_dest_bit_size(*dest
),
1116 .roundmode
= roundmode
,
1119 enum midgard_roundmode
*roundptr
= (opcode_props
& MIDGARD_ROUNDS
) ?
1120 &ins
.roundmode
: NULL
;
1122 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
1125 if (quirk_flipped_r24
) {
1127 mir_copy_src(&ins
, instr
, 0, 1, &ins
.src_abs
[1], &ins
.src_neg
[1], &ins
.src_invert
[1], roundptr
, is_int
, broadcast_swizzle
);
1129 for (unsigned i
= 0; i
< nr_inputs
; ++i
) {
1132 if (instr
->op
== nir_op_b32csel
) {
1133 /* The condition is the first argument; move
1134 * the other arguments up one to be a binary
1135 * instruction for Midgard with the condition
1140 else if (flip_src12
)
1144 } else if (flip_src12
) {
1148 mir_copy_src(&ins
, instr
, i
, to
, &ins
.src_abs
[to
], &ins
.src_neg
[to
], &ins
.src_invert
[to
], roundptr
, is_int
, broadcast_swizzle
);
1150 /* (!c) ? a : b = c ? b : a */
1151 if (instr
->op
== nir_op_b32csel
&& ins
.src_invert
[2]) {
1152 ins
.src_invert
[2] = false;
1158 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1159 /* Lowered to move */
1160 if (instr
->op
== nir_op_fneg
)
1161 ins
.src_neg
[1] ^= true;
1163 if (instr
->op
== nir_op_fabs
)
1164 ins
.src_abs
[1] = true;
1167 ins
.mask
= mask_of(nr_components
);
1169 midgard_vector_alu alu
= {
1171 .reg_mode
= reg_mode
,
1175 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1176 * components that don't exist. Note modifier => SSA => !reg => no
1177 * writemask, so we don't have to worry about writemasks here.*/
1180 ins
.mask
&= instr
->dest
.write_mask
;
1184 /* Late fixup for emulated instructions */
1186 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1187 /* Presently, our second argument is an inline #0 constant.
1188 * Switch over to an embedded 1.0 constant (that can't fit
1189 * inline, since we're 32-bit, not 16-bit like the inline
1192 ins
.has_inline_constant
= false;
1193 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1194 ins
.src_types
[1] = nir_type_float32
;
1195 ins
.has_constants
= true;
1197 if (instr
->op
== nir_op_b2f32
)
1198 ins
.constants
.f32
[0] = 1.0f
;
1200 ins
.constants
.i32
[0] = 1;
1202 for (unsigned c
= 0; c
< 16; ++c
)
1203 ins
.swizzle
[1][c
] = 0;
1204 } else if (instr
->op
== nir_op_b2f16
) {
1205 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1206 ins
.src_types
[1] = nir_type_float16
;
1207 ins
.has_constants
= true;
1208 ins
.constants
.i16
[0] = _mesa_float_to_half(1.0);
1210 for (unsigned c
= 0; c
< 16; ++c
)
1211 ins
.swizzle
[1][c
] = 0;
1212 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1213 /* Lots of instructions need a 0 plonked in */
1214 ins
.has_inline_constant
= false;
1215 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1216 ins
.src_types
[1] = nir_type_uint32
;
1217 ins
.has_constants
= true;
1218 ins
.constants
.u32
[0] = 0;
1220 for (unsigned c
= 0; c
< 16; ++c
)
1221 ins
.swizzle
[1][c
] = 0;
1222 } else if (instr
->op
== nir_op_pack_32_2x16
) {
1223 ins
.dest_type
= nir_type_uint16
;
1224 ins
.mask
= mask_of(nr_components
* 2);
1226 } else if (instr
->op
== nir_op_pack_32_4x8
) {
1227 ins
.dest_type
= nir_type_uint8
;
1228 ins
.mask
= mask_of(nr_components
* 4);
1230 } else if (instr
->op
== nir_op_unpack_32_2x16
) {
1231 ins
.dest_type
= nir_type_uint32
;
1232 ins
.mask
= mask_of(nr_components
>> 1);
1234 } else if (instr
->op
== nir_op_unpack_32_4x8
) {
1235 ins
.dest_type
= nir_type_uint32
;
1236 ins
.mask
= mask_of(nr_components
>> 2);
1240 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1241 /* To avoid duplicating the lookup tables (probably), true LUT
1242 * instructions can only operate as if they were scalars. Lower
1243 * them here by changing the component. */
1245 unsigned orig_mask
= ins
.mask
;
1247 unsigned swizzle_back
[MIR_VEC_COMPONENTS
];
1248 memcpy(&swizzle_back
, ins
.swizzle
[0], sizeof(swizzle_back
));
1250 midgard_instruction ins_split
[MIR_VEC_COMPONENTS
];
1251 unsigned ins_count
= 0;
1253 for (int i
= 0; i
< nr_components
; ++i
) {
1254 /* Mask the associated component, dropping the
1255 * instruction if needed */
1258 ins
.mask
&= orig_mask
;
1260 for (unsigned j
= 0; j
< ins_count
; ++j
) {
1261 if (swizzle_back
[i
] == ins_split
[j
].swizzle
[0][0]) {
1262 ins_split
[j
].mask
|= ins
.mask
;
1271 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1272 ins
.swizzle
[0][j
] = swizzle_back
[i
]; /* Pull from the correct component */
1274 ins_split
[ins_count
] = ins
;
1279 for (unsigned i
= 0; i
< ins_count
; ++i
) {
1280 emit_mir_instruction(ctx
, ins_split
[i
]);
1283 emit_mir_instruction(ctx
, ins
);
1290 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1292 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1293 unsigned nir_mask
= 0;
1297 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1298 dsize
= nir_dest_bit_size(intr
->dest
);
1300 nir_mask
= nir_intrinsic_write_mask(intr
);
1304 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1305 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1306 mir_set_bytemask(ins
, bytemask
);
1307 ins
->dest_type
= nir_type_uint
| dsize
;
1310 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1311 * optimized) versions of UBO #0 */
1313 static midgard_instruction
*
1315 compiler_context
*ctx
,
1319 nir_src
*indirect_offset
,
1320 unsigned indirect_shift
,
1323 /* TODO: half-floats */
1325 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1326 ins
.constants
.u32
[0] = offset
;
1328 if (instr
->type
== nir_instr_type_intrinsic
)
1329 mir_set_intr_mask(instr
, &ins
, true);
1331 if (indirect_offset
) {
1332 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1333 ins
.src_types
[2] = nir_type_uint32
;
1334 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1336 /* X component for the whole swizzle to prevent register
1337 * pressure from ballooning from the extra components */
1338 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[2]); ++i
)
1339 ins
.swizzle
[2][i
] = 0;
1341 ins
.load_store
.arg_2
= 0x1E;
1344 ins
.load_store
.arg_1
= index
;
1346 return emit_mir_instruction(ctx
, ins
);
1349 /* Globals are like UBOs if you squint. And shared memory is like globals if
1350 * you squint even harder */
1354 compiler_context
*ctx
,
1363 midgard_instruction ins
;
1366 ins
= m_ld_int4(srcdest
, 0);
1368 ins
= m_st_int4(srcdest
, 0);
1370 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1371 mir_set_intr_mask(instr
, &ins
, is_read
);
1373 emit_mir_instruction(ctx
, ins
);
1378 compiler_context
*ctx
,
1379 unsigned dest
, unsigned offset
,
1380 unsigned nr_comp
, unsigned component
,
1381 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1383 /* XXX: Half-floats? */
1384 /* TODO: swizzle, mask */
1386 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1387 ins
.mask
= mask_of(nr_comp
);
1388 ins
.dest_type
= type
;
1390 if (type
== nir_type_float16
) {
1391 /* Ensure we are aligned so we can pack it later */
1392 ins
.mask
= mask_of(ALIGN_POT(nr_comp
, 2));
1395 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1396 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1398 midgard_varying_parameter p
= {
1400 .interpolation
= midgard_interp_default
,
1405 memcpy(&u
, &p
, sizeof(p
));
1406 ins
.load_store
.varying_parameters
= u
;
1408 if (indirect_offset
) {
1409 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1410 ins
.src_types
[2] = nir_type_uint32
;
1412 ins
.load_store
.arg_2
= 0x1E;
1414 ins
.load_store
.arg_1
= 0x9E;
1416 /* Use the type appropriate load */
1418 case nir_type_uint32
:
1419 case nir_type_bool32
:
1420 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1422 case nir_type_int32
:
1423 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1425 case nir_type_float32
:
1426 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1428 case nir_type_float16
:
1429 ins
.load_store
.op
= midgard_op_ld_vary_16
;
1432 unreachable("Attempted to load unknown type");
1436 emit_mir_instruction(ctx
, ins
);
1441 compiler_context
*ctx
,
1442 unsigned dest
, unsigned offset
,
1443 unsigned nr_comp
, nir_alu_type t
)
1445 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1446 ins
.load_store
.arg_1
= 0x1E;
1447 ins
.load_store
.arg_2
= 0x1E;
1448 ins
.mask
= mask_of(nr_comp
);
1450 /* Use the type appropriate load */
1454 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1457 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1459 case nir_type_float
:
1460 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1463 unreachable("Attempted to load unknown type");
1467 emit_mir_instruction(ctx
, ins
);
1471 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1472 unsigned nr_components
, unsigned offset
)
1476 /* Figure out which uniform this is */
1477 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1478 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1480 unsigned dest
= nir_dest_index(&nir_dest
);
1482 /* Sysvals are prefix uniforms */
1483 unsigned uniform
= ((uintptr_t) val
) - 1;
1485 /* Emit the read itself -- this is never indirect */
1486 midgard_instruction
*ins
=
1487 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1489 ins
->mask
= mask_of(nr_components
);
1493 compute_builtin_arg(nir_op op
)
1496 case nir_intrinsic_load_work_group_id
:
1498 case nir_intrinsic_load_local_invocation_id
:
1501 unreachable("Invalid compute paramater loaded");
1506 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned src_z
, unsigned src_s
, enum midgard_rt_id rt
)
1508 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1510 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1514 emit_explicit_constant(ctx
, src
, src
);
1516 struct midgard_instruction ins
=
1517 v_branch(false, false);
1519 bool depth_only
= (rt
== MIDGARD_ZS_RT
);
1521 ins
.writeout
= depth_only
? 0 : PAN_WRITEOUT_C
;
1523 /* Add dependencies */
1525 ins
.src_types
[0] = nir_type_uint32
;
1526 ins
.constants
.u32
[0] = depth_only
? 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1527 for (int i
= 0; i
< 4; ++i
)
1528 ins
.swizzle
[0][i
] = i
;
1531 emit_explicit_constant(ctx
, src_z
, src_z
);
1533 ins
.src_types
[2] = nir_type_uint32
;
1534 ins
.writeout
|= PAN_WRITEOUT_Z
;
1537 emit_explicit_constant(ctx
, src_s
, src_s
);
1539 ins
.src_types
[3] = nir_type_uint32
;
1540 ins
.writeout
|= PAN_WRITEOUT_S
;
1543 /* Emit the branch */
1544 br
= emit_mir_instruction(ctx
, ins
);
1545 schedule_barrier(ctx
);
1546 ctx
->writeout_branch
[rt
] = br
;
1548 /* Push our current location = current block count - 1 = where we'll
1549 * jump to. Maybe a bit too clever for my own good */
1551 br
->branch
.target_block
= ctx
->block_count
- 1;
1555 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1557 unsigned reg
= nir_dest_index(&instr
->dest
);
1558 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1559 ins
.mask
= mask_of(3);
1560 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1561 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1562 emit_mir_instruction(ctx
, ins
);
1566 vertex_builtin_arg(nir_op op
)
1569 case nir_intrinsic_load_vertex_id
:
1570 return PAN_VERTEX_ID
;
1571 case nir_intrinsic_load_instance_id
:
1572 return PAN_INSTANCE_ID
;
1574 unreachable("Invalid vertex builtin");
1579 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1581 unsigned reg
= nir_dest_index(&instr
->dest
);
1582 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1586 emit_control_barrier(compiler_context
*ctx
)
1588 midgard_instruction ins
= {
1589 .type
= TAG_TEXTURE_4
,
1591 .src
= { ~0, ~0, ~0, ~0 },
1593 .op
= TEXTURE_OP_BARRIER
,
1595 /* TODO: optimize */
1596 .out_of_order
= MIDGARD_BARRIER_BUFFER
|
1597 MIDGARD_BARRIER_SHARED
,
1601 emit_mir_instruction(ctx
, ins
);
1605 mir_get_branch_cond(nir_src
*src
, bool *invert
)
1607 /* Wrap it. No swizzle since it's a scalar */
1613 *invert
= pan_has_source_mod(&alu
, nir_op_inot
);
1614 return nir_src_index(NULL
, &alu
.src
);
1618 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1620 unsigned offset
= 0, reg
;
1622 switch (instr
->intrinsic
) {
1623 case nir_intrinsic_discard_if
:
1624 case nir_intrinsic_discard
: {
1625 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1626 struct midgard_instruction discard
= v_branch(conditional
, false);
1627 discard
.branch
.target_type
= TARGET_DISCARD
;
1630 discard
.src
[0] = mir_get_branch_cond(&instr
->src
[0],
1631 &discard
.branch
.invert_conditional
);
1632 discard
.src_types
[0] = nir_type_uint32
;
1635 emit_mir_instruction(ctx
, discard
);
1636 schedule_barrier(ctx
);
1641 case nir_intrinsic_load_uniform
:
1642 case nir_intrinsic_load_ubo
:
1643 case nir_intrinsic_load_global
:
1644 case nir_intrinsic_load_shared
:
1645 case nir_intrinsic_load_input
:
1646 case nir_intrinsic_load_interpolated_input
: {
1647 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1648 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1649 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1650 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1651 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1652 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1654 /* Get the base type of the intrinsic */
1655 /* TODO: Infer type? Does it matter? */
1657 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1658 (is_interp
) ? nir_type_float
:
1659 nir_intrinsic_type(instr
);
1661 t
= nir_alu_type_get_base_type(t
);
1663 if (!(is_ubo
|| is_global
)) {
1664 offset
= nir_intrinsic_base(instr
);
1667 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1669 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1671 bool direct
= nir_src_is_const(*src_offset
);
1672 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1675 offset
+= nir_src_as_uint(*src_offset
);
1677 /* We may need to apply a fractional offset */
1678 int component
= (is_flat
|| is_interp
) ?
1679 nir_intrinsic_component(instr
) : 0;
1680 reg
= nir_dest_index(&instr
->dest
);
1682 if (is_uniform
&& !ctx
->is_blend
) {
1683 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1684 } else if (is_ubo
) {
1685 nir_src index
= instr
->src
[0];
1687 /* TODO: Is indirect block number possible? */
1688 assert(nir_src_is_const(index
));
1690 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1691 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1692 } else if (is_global
|| is_shared
) {
1693 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1694 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1695 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
| nir_dest_bit_size(instr
->dest
), is_flat
);
1696 } else if (ctx
->is_blend
) {
1697 /* ctx->blend_input will be precoloured to r0, where
1698 * the input is preloaded */
1700 if (ctx
->blend_input
== ~0)
1701 ctx
->blend_input
= reg
;
1703 emit_mir_instruction(ctx
, v_mov(ctx
->blend_input
, reg
));
1704 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1705 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1707 DBG("Unknown load\n");
1714 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1715 case nir_intrinsic_load_barycentric_pixel
:
1716 case nir_intrinsic_load_barycentric_centroid
:
1719 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1721 case nir_intrinsic_load_raw_output_pan
: {
1722 reg
= nir_dest_index(&instr
->dest
);
1724 /* T720 and below use different blend opcodes with slightly
1725 * different semantics than T760 and up */
1727 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1729 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1730 ld
.load_store
.op
= midgard_op_ld_color_buffer_32u_old
;
1731 ld
.load_store
.address
= 16;
1732 ld
.load_store
.arg_2
= 0x1E;
1735 emit_mir_instruction(ctx
, ld
);
1739 case nir_intrinsic_load_output
: {
1740 reg
= nir_dest_index(&instr
->dest
);
1742 midgard_instruction ld
= m_ld_color_buffer_as_fp16(reg
, 0);
1744 for (unsigned c
= 4; c
< 16; ++c
)
1745 ld
.swizzle
[0][c
] = 0;
1747 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1748 ld
.load_store
.op
= midgard_op_ld_color_buffer_as_fp16_old
;
1749 ld
.load_store
.address
= 1;
1750 ld
.load_store
.arg_2
= 0x1E;
1753 emit_mir_instruction(ctx
, ld
);
1757 case nir_intrinsic_load_blend_const_color_rgba
: {
1758 assert(ctx
->is_blend
);
1759 reg
= nir_dest_index(&instr
->dest
);
1761 /* Blend constants are embedded directly in the shader and
1762 * patched in, so we use some magic routing */
1764 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1765 ins
.has_constants
= true;
1766 ins
.has_blend_constant
= true;
1767 emit_mir_instruction(ctx
, ins
);
1771 case nir_intrinsic_store_output
:
1772 case nir_intrinsic_store_combined_output_pan
:
1773 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1775 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1777 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1779 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1780 bool combined
= instr
->intrinsic
==
1781 nir_intrinsic_store_combined_output_pan
;
1783 const nir_variable
*var
;
1784 enum midgard_rt_id rt
;
1786 var
= search_var(&ctx
->nir
->outputs
,
1787 nir_intrinsic_base(instr
));
1789 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1790 rt
= MIDGARD_COLOR_RT0
;
1791 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1792 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1799 unsigned reg_z
= ~0, reg_s
= ~0;
1801 unsigned writeout
= nir_intrinsic_component(instr
);
1802 if (writeout
& PAN_WRITEOUT_Z
)
1803 reg_z
= nir_src_index(ctx
, &instr
->src
[2]);
1804 if (writeout
& PAN_WRITEOUT_S
)
1805 reg_s
= nir_src_index(ctx
, &instr
->src
[3]);
1808 emit_fragment_store(ctx
, reg
, reg_z
, reg_s
, rt
);
1809 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1810 assert(instr
->intrinsic
== nir_intrinsic_store_output
);
1812 /* We should have been vectorized, though we don't
1813 * currently check that st_vary is emitted only once
1814 * per slot (this is relevant, since there's not a mask
1815 * parameter available on the store [set to 0 by the
1816 * blob]). We do respect the component by adjusting the
1817 * swizzle. If this is a constant source, we'll need to
1818 * emit that explicitly. */
1820 emit_explicit_constant(ctx
, reg
, reg
);
1822 unsigned dst_component
= nir_intrinsic_component(instr
);
1823 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1825 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1826 st
.load_store
.arg_1
= 0x9E;
1827 st
.load_store
.arg_2
= 0x1E;
1829 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1832 st
.load_store
.op
= midgard_op_st_vary_32u
;
1835 st
.load_store
.op
= midgard_op_st_vary_32i
;
1837 case nir_type_float
:
1838 st
.load_store
.op
= midgard_op_st_vary_32
;
1841 unreachable("Attempted to store unknown type");
1845 /* nir_intrinsic_component(store_intr) encodes the
1846 * destination component start. Source component offset
1847 * adjustment is taken care of in
1848 * install_registers_instr(), when offset_swizzle() is
1851 unsigned src_component
= COMPONENT_X
;
1853 assert(nr_comp
> 0);
1854 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1855 st
.swizzle
[0][i
] = src_component
;
1856 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1860 emit_mir_instruction(ctx
, st
);
1862 DBG("Unknown store\n");
1868 /* Special case of store_output for lowered blend shaders */
1869 case nir_intrinsic_store_raw_output_pan
:
1870 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1871 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1872 emit_fragment_store(ctx
, reg
, ~0, ~0, ctx
->blend_rt
);
1875 case nir_intrinsic_store_global
:
1876 case nir_intrinsic_store_shared
:
1877 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1878 emit_explicit_constant(ctx
, reg
, reg
);
1880 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1883 case nir_intrinsic_load_ssbo_address
:
1884 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1887 case nir_intrinsic_get_buffer_size
:
1888 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1891 case nir_intrinsic_load_viewport_scale
:
1892 case nir_intrinsic_load_viewport_offset
:
1893 case nir_intrinsic_load_num_work_groups
:
1894 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1895 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1898 case nir_intrinsic_load_work_group_id
:
1899 case nir_intrinsic_load_local_invocation_id
:
1900 emit_compute_builtin(ctx
, instr
);
1903 case nir_intrinsic_load_vertex_id
:
1904 case nir_intrinsic_load_instance_id
:
1905 emit_vertex_builtin(ctx
, instr
);
1908 case nir_intrinsic_memory_barrier_buffer
:
1909 case nir_intrinsic_memory_barrier_shared
:
1912 case nir_intrinsic_control_barrier
:
1913 schedule_barrier(ctx
);
1914 emit_control_barrier(ctx
);
1915 schedule_barrier(ctx
);
1919 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1926 midgard_tex_format(enum glsl_sampler_dim dim
)
1929 case GLSL_SAMPLER_DIM_1D
:
1930 case GLSL_SAMPLER_DIM_BUF
:
1933 case GLSL_SAMPLER_DIM_2D
:
1934 case GLSL_SAMPLER_DIM_MS
:
1935 case GLSL_SAMPLER_DIM_EXTERNAL
:
1936 case GLSL_SAMPLER_DIM_RECT
:
1939 case GLSL_SAMPLER_DIM_3D
:
1942 case GLSL_SAMPLER_DIM_CUBE
:
1943 return MALI_TEX_CUBE
;
1946 DBG("Unknown sampler dim type\n");
1952 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1956 pan_attach_constant_bias(
1957 compiler_context
*ctx
,
1959 midgard_texture_word
*word
)
1961 /* To attach as constant, it has to *be* constant */
1963 if (!nir_src_is_const(lod
))
1966 float f
= nir_src_as_float(lod
);
1968 /* Break into fixed-point */
1970 float lod_frac
= f
- lod_int
;
1972 /* Carry over negative fractions */
1973 if (lod_frac
< 0.0) {
1979 word
->bias
= float_to_ubyte(lod_frac
);
1980 word
->bias_int
= lod_int
;
1986 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1987 unsigned midgard_texop
)
1990 //assert (!instr->sampler);
1992 int texture_index
= instr
->texture_index
;
1993 int sampler_index
= texture_index
;
1995 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
1996 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(instr
->dest
);
1998 midgard_instruction ins
= {
1999 .type
= TAG_TEXTURE_4
,
2001 .dest
= nir_dest_index(&instr
->dest
),
2002 .src
= { ~0, ~0, ~0, ~0 },
2003 .dest_type
= dest_type
,
2004 .swizzle
= SWIZZLE_IDENTITY_4
,
2006 .op
= midgard_texop
,
2007 .format
= midgard_tex_format(instr
->sampler_dim
),
2008 .texture_handle
= texture_index
,
2009 .sampler_handle
= sampler_index
,
2010 .shadow
= instr
->is_shadow
,
2014 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
2015 for (int i
= 0; i
< 4; ++i
)
2016 ins
.swizzle
[0][i
] = COMPONENT_X
;
2018 /* We may need a temporary for the coordinate */
2020 bool needs_temp_coord
=
2021 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
2022 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
2025 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
2027 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
2028 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
2029 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
2030 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
2031 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
2033 switch (instr
->src
[i
].src_type
) {
2034 case nir_tex_src_coord
: {
2035 emit_explicit_constant(ctx
, index
, index
);
2037 unsigned coord_mask
= mask_of(instr
->coord_components
);
2039 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
2042 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
2044 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2045 /* texelFetch is undefined on samplerCube */
2046 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
2048 /* For cubemaps, we use a special ld/st op to
2049 * select the face and copy the xy into the
2050 * texture register */
2052 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
2054 ld
.src_types
[1] = T
;
2055 ld
.mask
= 0x3; /* xy */
2056 ld
.load_store
.arg_1
= 0x20;
2057 ld
.swizzle
[1][3] = COMPONENT_X
;
2058 emit_mir_instruction(ctx
, ld
);
2061 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2062 ins
.swizzle
[1][3] = COMPONENT_X
;
2063 } else if (needs_temp_coord
) {
2064 /* mov coord_temp, coords */
2065 midgard_instruction mov
= v_mov(index
, coords
);
2066 mov
.mask
= coord_mask
;
2069 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
2071 emit_mir_instruction(ctx
, mov
);
2076 ins
.src
[1] = coords
;
2077 ins
.src_types
[1] = T
;
2079 /* Texelfetch coordinates uses all four elements
2080 * (xyz/index) regardless of texture dimensionality,
2081 * which means it's necessary to zero the unused
2082 * components to keep everything happy */
2084 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2085 /* mov index.zw, #0, or generalized */
2086 midgard_instruction mov
=
2087 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
2088 mov
.has_constants
= true;
2089 mov
.mask
= coord_mask
^ 0xF;
2090 emit_mir_instruction(ctx
, mov
);
2093 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
2094 /* Array component in w but NIR wants it in z,
2095 * but if we have a temp coord we already fixed
2098 if (nr_components
== 3) {
2099 ins
.swizzle
[1][2] = COMPONENT_Z
;
2100 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
2101 } else if (nr_components
== 2) {
2103 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2104 ins
.swizzle
[1][3] = COMPONENT_X
;
2106 unreachable("Invalid texture 2D components");
2109 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2111 ins
.swizzle
[1][2] = COMPONENT_Z
;
2112 ins
.swizzle
[1][3] = COMPONENT_W
;
2118 case nir_tex_src_bias
:
2119 case nir_tex_src_lod
: {
2120 /* Try as a constant if we can */
2122 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
2123 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
2126 ins
.texture
.lod_register
= true;
2128 ins
.src_types
[2] = T
;
2130 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2131 ins
.swizzle
[2][c
] = COMPONENT_X
;
2133 emit_explicit_constant(ctx
, index
, index
);
2138 case nir_tex_src_offset
: {
2139 ins
.texture
.offset_register
= true;
2141 ins
.src_types
[3] = T
;
2143 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2144 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
2146 emit_explicit_constant(ctx
, index
, index
);
2150 case nir_tex_src_comparator
:
2151 case nir_tex_src_ms_index
: {
2152 unsigned comp
= COMPONENT_Z
;
2154 /* mov coord_temp.foo, coords */
2155 midgard_instruction mov
= v_mov(index
, coords
);
2156 mov
.mask
= 1 << comp
;
2158 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2159 mov
.swizzle
[1][i
] = COMPONENT_X
;
2161 emit_mir_instruction(ctx
, mov
);
2166 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2172 emit_mir_instruction(ctx
, ins
);
2176 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2178 switch (instr
->op
) {
2181 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2184 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2187 case nir_texop_txf_ms
:
2188 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2191 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
2194 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
2201 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2203 switch (instr
->type
) {
2204 case nir_jump_break
: {
2205 /* Emit a branch out of the loop */
2206 struct midgard_instruction br
= v_branch(false, false);
2207 br
.branch
.target_type
= TARGET_BREAK
;
2208 br
.branch
.target_break
= ctx
->current_loop_depth
;
2209 emit_mir_instruction(ctx
, br
);
2214 DBG("Unknown jump type %d\n", instr
->type
);
2220 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2222 switch (instr
->type
) {
2223 case nir_instr_type_load_const
:
2224 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2227 case nir_instr_type_intrinsic
:
2228 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2231 case nir_instr_type_alu
:
2232 emit_alu(ctx
, nir_instr_as_alu(instr
));
2235 case nir_instr_type_tex
:
2236 emit_tex(ctx
, nir_instr_as_tex(instr
));
2239 case nir_instr_type_jump
:
2240 emit_jump(ctx
, nir_instr_as_jump(instr
));
2243 case nir_instr_type_ssa_undef
:
2248 DBG("Unhandled instruction type\n");
2254 /* ALU instructions can inline or embed constants, which decreases register
2255 * pressure and saves space. */
2257 #define CONDITIONAL_ATTACH(idx) { \
2258 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2261 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2262 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2267 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2269 mir_foreach_instr_in_block(block
, alu
) {
2270 /* Other instructions cannot inline constants */
2271 if (alu
->type
!= TAG_ALU_4
) continue;
2272 if (alu
->compact_branch
) continue;
2274 /* If there is already a constant here, we can do nothing */
2275 if (alu
->has_constants
) continue;
2277 CONDITIONAL_ATTACH(0);
2279 if (!alu
->has_constants
) {
2280 CONDITIONAL_ATTACH(1)
2281 } else if (!alu
->inline_constant
) {
2282 /* Corner case: _two_ vec4 constants, for instance with a
2283 * csel. For this case, we can only use a constant
2284 * register for one, we'll have to emit a move for the
2287 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2288 unsigned scratch
= make_compiler_temp(ctx
);
2291 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2292 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2294 /* Set the source */
2295 alu
->src
[1] = scratch
;
2297 /* Inject us -before- the last instruction which set r31 */
2298 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2304 /* Midgard supports two types of constants, embedded constants (128-bit) and
2305 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2306 * constants can be demoted to inline constants, for space savings and
2307 * sometimes a performance boost */
2310 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2312 mir_foreach_instr_in_block(block
, ins
) {
2313 if (!ins
->has_constants
) continue;
2314 if (ins
->has_inline_constant
) continue;
2316 /* Blend constants must not be inlined by definition */
2317 if (ins
->has_blend_constant
) continue;
2319 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2320 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2321 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2323 if (!(is_16
|| is_32
))
2326 /* src1 cannot be an inline constant due to encoding
2327 * restrictions. So, if possible we try to flip the arguments
2330 int op
= ins
->alu
.op
;
2332 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2333 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2337 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2338 /* Component is from the swizzle. Take a nonzero component */
2340 unsigned first_comp
= ffs(ins
->mask
) - 1;
2341 unsigned component
= ins
->swizzle
[1][first_comp
];
2343 /* Scale constant appropriately, if we can legally */
2344 int16_t scaled_constant
= 0;
2347 scaled_constant
= ins
->constants
.u16
[component
];
2348 } else if (midgard_is_integer_op(op
)) {
2349 scaled_constant
= ins
->constants
.u32
[component
];
2351 /* Constant overflow after resize */
2352 if (scaled_constant
!= ins
->constants
.u32
[component
])
2355 float original
= ins
->constants
.f32
[component
];
2356 scaled_constant
= _mesa_float_to_half(original
);
2358 /* Check for loss of precision. If this is
2359 * mediump, we don't care, but for a highp
2360 * shader, we need to pay attention. NIR
2361 * doesn't yet tell us which mode we're in!
2362 * Practically this prevents most constants
2363 * from being inlined, sadly. */
2365 float fp32
= _mesa_half_to_float(scaled_constant
);
2367 if (fp32
!= original
)
2371 /* Should've been const folded */
2372 if (ins
->src_abs
[1] || ins
->src_neg
[1])
2375 /* Make sure that the constant is not itself a vector
2376 * by checking if all accessed values are the same. */
2378 const midgard_constants
*cons
= &ins
->constants
;
2379 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2381 bool is_vector
= false;
2382 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2384 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2385 /* We only care if this component is actually used */
2386 if (!(mask
& (1 << c
)))
2389 uint32_t test
= is_16
?
2390 cons
->u16
[ins
->swizzle
[1][c
]] :
2391 cons
->u32
[ins
->swizzle
[1][c
]];
2393 if (test
!= value
) {
2402 /* Get rid of the embedded constant */
2403 ins
->has_constants
= false;
2405 ins
->has_inline_constant
= true;
2406 ins
->inline_constant
= scaled_constant
;
2411 /* Dead code elimination for branches at the end of a block - only one branch
2412 * per block is legal semantically */
2415 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2417 bool branched
= false;
2419 mir_foreach_instr_in_block_safe(block
, ins
) {
2420 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2423 mir_remove_instruction(ins
);
2429 /* We want to force the invert on AND/OR to the second slot to legalize into
2430 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2432 * ~a & #b = ~a & ~(#~b)
2437 midgard_legalize_invert(compiler_context
*ctx
, midgard_block
*block
)
2439 mir_foreach_instr_in_block(block
, ins
) {
2440 if (ins
->type
!= TAG_ALU_4
) continue;
2442 if (ins
->alu
.op
!= midgard_alu_op_iand
&&
2443 ins
->alu
.op
!= midgard_alu_op_ior
) continue;
2445 if (ins
->src_invert
[1] || !ins
->src_invert
[0]) continue;
2447 if (ins
->has_inline_constant
) {
2448 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2450 ins
->inline_constant
= ~ins
->inline_constant
;
2451 ins
->src_invert
[1] = true;
2453 /* Flip to the right invert order. Note
2454 * has_inline_constant false by assumption on the
2455 * branch, so flipping makes sense. */
2462 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2464 /* Loop to ourselves */
2465 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2466 struct midgard_instruction ins
= v_branch(false, false);
2467 ins
.writeout
= br
->writeout
;
2468 ins
.branch
.target_block
= ctx
->block_count
- 1;
2469 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2470 memcpy(&ins
.src_types
, &br
->src_types
, sizeof(ins
.src_types
));
2471 emit_mir_instruction(ctx
, ins
);
2473 ctx
->current_block
->epilogue
= true;
2474 schedule_barrier(ctx
);
2475 return ins
.branch
.target_block
;
2478 static midgard_block
*
2479 emit_block_init(compiler_context
*ctx
)
2481 midgard_block
*this_block
= ctx
->after_block
;
2482 ctx
->after_block
= NULL
;
2485 this_block
= create_empty_block(ctx
);
2487 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2489 this_block
->scheduled
= false;
2492 /* Set up current block */
2493 list_inithead(&this_block
->base
.instructions
);
2494 ctx
->current_block
= this_block
;
2499 static midgard_block
*
2500 emit_block(compiler_context
*ctx
, nir_block
*block
)
2502 midgard_block
*this_block
= emit_block_init(ctx
);
2504 nir_foreach_instr(instr
, block
) {
2505 emit_instr(ctx
, instr
);
2506 ++ctx
->instruction_count
;
2512 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2515 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2517 midgard_block
*before_block
= ctx
->current_block
;
2519 /* Speculatively emit the branch, but we can't fill it in until later */
2521 EMIT(branch
, true, true);
2522 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2523 then_branch
->src
[0] = mir_get_branch_cond(&nif
->condition
, &inv
);
2524 then_branch
->src_types
[0] = nir_type_uint32
;
2525 then_branch
->branch
.invert_conditional
= !inv
;
2527 /* Emit the two subblocks. */
2528 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2529 midgard_block
*end_then_block
= ctx
->current_block
;
2531 /* Emit a jump from the end of the then block to the end of the else */
2532 EMIT(branch
, false, false);
2533 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2535 /* Emit second block, and check if it's empty */
2537 int else_idx
= ctx
->block_count
;
2538 int count_in
= ctx
->instruction_count
;
2539 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2540 midgard_block
*end_else_block
= ctx
->current_block
;
2541 int after_else_idx
= ctx
->block_count
;
2543 /* Now that we have the subblocks emitted, fix up the branches */
2548 if (ctx
->instruction_count
== count_in
) {
2549 /* The else block is empty, so don't emit an exit jump */
2550 mir_remove_instruction(then_exit
);
2551 then_branch
->branch
.target_block
= after_else_idx
;
2553 then_branch
->branch
.target_block
= else_idx
;
2554 then_exit
->branch
.target_block
= after_else_idx
;
2557 /* Wire up the successors */
2559 ctx
->after_block
= create_empty_block(ctx
);
2561 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2562 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2564 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2565 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2569 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2571 /* Remember where we are */
2572 midgard_block
*start_block
= ctx
->current_block
;
2574 /* Allocate a loop number, growing the current inner loop depth */
2575 int loop_idx
= ++ctx
->current_loop_depth
;
2577 /* Get index from before the body so we can loop back later */
2578 int start_idx
= ctx
->block_count
;
2580 /* Emit the body itself */
2581 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2583 /* Branch back to loop back */
2584 struct midgard_instruction br_back
= v_branch(false, false);
2585 br_back
.branch
.target_block
= start_idx
;
2586 emit_mir_instruction(ctx
, br_back
);
2588 /* Mark down that branch in the graph. */
2589 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2590 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2592 /* Find the index of the block about to follow us (note: we don't add
2593 * one; blocks are 0-indexed so we get a fencepost problem) */
2594 int break_block_idx
= ctx
->block_count
;
2596 /* Fix up the break statements we emitted to point to the right place,
2597 * now that we can allocate a block number for them */
2598 ctx
->after_block
= create_empty_block(ctx
);
2600 mir_foreach_block_from(ctx
, start_block
, _block
) {
2601 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2602 if (ins
->type
!= TAG_ALU_4
) continue;
2603 if (!ins
->compact_branch
) continue;
2605 /* We found a branch -- check the type to see if we need to do anything */
2606 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2608 /* It's a break! Check if it's our break */
2609 if (ins
->branch
.target_break
!= loop_idx
) continue;
2611 /* Okay, cool, we're breaking out of this loop.
2612 * Rewrite from a break to a goto */
2614 ins
->branch
.target_type
= TARGET_GOTO
;
2615 ins
->branch
.target_block
= break_block_idx
;
2617 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2621 /* Now that we've finished emitting the loop, free up the depth again
2622 * so we play nice with recursion amid nested loops */
2623 --ctx
->current_loop_depth
;
2625 /* Dump loop stats */
2629 static midgard_block
*
2630 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2632 midgard_block
*start_block
= NULL
;
2634 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2635 switch (node
->type
) {
2636 case nir_cf_node_block
: {
2637 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2640 start_block
= block
;
2645 case nir_cf_node_if
:
2646 emit_if(ctx
, nir_cf_node_as_if(node
));
2649 case nir_cf_node_loop
:
2650 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2653 case nir_cf_node_function
:
2662 /* Due to lookahead, we need to report the first tag executed in the command
2663 * stream and in branch targets. An initial block might be empty, so iterate
2664 * until we find one that 'works' */
2667 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2669 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2671 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2672 midgard_block
*v
= (midgard_block
*) _v
;
2673 if (v
->quadword_count
) {
2674 midgard_bundle
*initial_bundle
=
2675 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2677 return initial_bundle
->tag
;
2681 /* Default to a tag 1 which will break from the shader, in case we jump
2682 * to the exit block (i.e. `return` in a compute shader) */
2687 /* For each fragment writeout instruction, generate a writeout loop to
2688 * associate with it */
2691 mir_add_writeout_loops(compiler_context
*ctx
)
2693 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2694 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2697 unsigned popped
= br
->branch
.target_block
;
2698 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2699 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2700 br
->branch
.target_type
= TARGET_GOTO
;
2702 /* If we have more RTs, we'll need to restore back after our
2703 * loop terminates */
2705 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2706 midgard_instruction uncond
= v_branch(false, false);
2707 uncond
.branch
.target_block
= popped
;
2708 uncond
.branch
.target_type
= TARGET_GOTO
;
2709 emit_mir_instruction(ctx
, uncond
);
2710 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2711 schedule_barrier(ctx
);
2713 /* We're last, so we can terminate here */
2714 br
->last_writeout
= true;
2720 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2722 struct util_dynarray
*compiled
= &program
->compiled
;
2724 midgard_debug
= debug_get_option_midgard_debug();
2726 /* TODO: Bound against what? */
2727 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2730 ctx
->stage
= nir
->info
.stage
;
2731 ctx
->is_blend
= is_blend
;
2732 ctx
->alpha_ref
= program
->alpha_ref
;
2733 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2734 ctx
->blend_input
= ~0;
2735 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2737 /* Start off with a safe cutoff, allowing usage of all 16 work
2738 * registers. Later, we'll promote uniform reads to uniform registers
2739 * if we determine it is beneficial to do so */
2740 ctx
->uniform_cutoff
= 8;
2742 /* Initialize at a global (not block) level hash tables */
2744 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2745 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2747 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2748 * (so we don't accidentally duplicate the epilogue since mesa/st has
2749 * messed with our I/O quite a bit already) */
2751 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2753 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2754 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2755 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2758 NIR_PASS_V(nir
, nir_lower_var_copies
);
2759 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2760 NIR_PASS_V(nir
, nir_split_var_copies
);
2761 NIR_PASS_V(nir
, nir_lower_var_copies
);
2762 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2763 NIR_PASS_V(nir
, nir_lower_var_copies
);
2764 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2766 unsigned pan_quirks
= panfrost_get_quirks(gpu_id
);
2767 NIR_PASS_V(nir
, pan_lower_framebuffer
,
2768 program
->rt_formats
, is_blend
, pan_quirks
);
2770 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
2772 NIR_PASS_V(nir
, nir_lower_ssbo
);
2773 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2775 /* Optimisation passes */
2777 optimise_nir(nir
, ctx
->quirks
, is_blend
);
2779 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2780 nir_print_shader(nir
, stdout
);
2783 /* Assign sysvals and counts, now that we're sure
2784 * (post-optimisation) */
2786 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2787 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2788 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2790 nir_foreach_function(func
, nir
) {
2794 list_inithead(&ctx
->blocks
);
2795 ctx
->block_count
= 0;
2797 ctx
->already_emitted
= calloc(BITSET_WORDS(func
->impl
->ssa_alloc
), sizeof(BITSET_WORD
));
2799 if (nir
->info
.outputs_read
&& !is_blend
) {
2800 emit_block_init(ctx
);
2802 struct midgard_instruction wait
= v_branch(false, false);
2803 wait
.branch
.target_type
= TARGET_TILEBUF_WAIT
;
2805 emit_mir_instruction(ctx
, wait
);
2807 ++ctx
->instruction_count
;
2810 emit_cf_list(ctx
, &func
->impl
->body
);
2811 free(ctx
->already_emitted
);
2812 break; /* TODO: Multi-function shaders */
2815 util_dynarray_init(compiled
, NULL
);
2817 /* Per-block lowering before opts */
2819 mir_foreach_block(ctx
, _block
) {
2820 midgard_block
*block
= (midgard_block
*) _block
;
2821 inline_alu_constants(ctx
, block
);
2822 embedded_to_inline_constant(ctx
, block
);
2824 /* MIR-level optimizations */
2826 bool progress
= false;
2830 progress
|= midgard_opt_dead_code_eliminate(ctx
);
2832 mir_foreach_block(ctx
, _block
) {
2833 midgard_block
*block
= (midgard_block
*) _block
;
2834 progress
|= midgard_opt_copy_prop(ctx
, block
);
2835 progress
|= midgard_opt_combine_projection(ctx
, block
);
2836 progress
|= midgard_opt_varying_projection(ctx
, block
);
2840 mir_foreach_block(ctx
, _block
) {
2841 midgard_block
*block
= (midgard_block
*) _block
;
2842 midgard_lower_derivatives(ctx
, block
);
2843 midgard_legalize_invert(ctx
, block
);
2844 midgard_cull_dead_branch(ctx
, block
);
2847 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2848 mir_add_writeout_loops(ctx
);
2850 /* Analyze now that the code is known but before scheduling creates
2851 * pipeline registers which are harder to track */
2852 mir_analyze_helper_terminate(ctx
);
2853 mir_analyze_helper_requirements(ctx
);
2856 midgard_schedule_program(ctx
);
2859 /* Now that all the bundles are scheduled and we can calculate block
2860 * sizes, emit actual branch instructions rather than placeholders */
2862 int br_block_idx
= 0;
2864 mir_foreach_block(ctx
, _block
) {
2865 midgard_block
*block
= (midgard_block
*) _block
;
2866 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2867 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2868 midgard_instruction
*ins
= bundle
->instructions
[c
];
2870 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2872 /* Parse some basic branch info */
2873 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2874 bool is_conditional
= ins
->branch
.conditional
;
2875 bool is_inverted
= ins
->branch
.invert_conditional
;
2876 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2877 bool is_tilebuf_wait
= ins
->branch
.target_type
== TARGET_TILEBUF_WAIT
;
2878 bool is_special
= is_discard
|| is_tilebuf_wait
;
2879 bool is_writeout
= ins
->writeout
;
2881 /* Determine the block we're jumping to */
2882 int target_number
= ins
->branch
.target_block
;
2884 /* Report the destination tag */
2885 int dest_tag
= is_discard
? 0 :
2886 is_tilebuf_wait
? bundle
->tag
:
2887 midgard_get_first_tag_from_block(ctx
, target_number
);
2889 /* Count up the number of quadwords we're
2890 * jumping over = number of quadwords until
2891 * (br_block_idx, target_number) */
2893 int quadword_offset
= 0;
2897 } else if (is_tilebuf_wait
) {
2898 quadword_offset
= -1;
2899 } else if (target_number
> br_block_idx
) {
2902 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2903 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2906 quadword_offset
+= blk
->quadword_count
;
2909 /* Jump backwards */
2911 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2912 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2915 quadword_offset
-= blk
->quadword_count
;
2919 /* Unconditional extended branches (far jumps)
2920 * have issues, so we always use a conditional
2921 * branch, setting the condition to always for
2922 * unconditional. For compact unconditional
2923 * branches, cond isn't used so it doesn't
2924 * matter what we pick. */
2926 midgard_condition cond
=
2927 !is_conditional
? midgard_condition_always
:
2928 is_inverted
? midgard_condition_false
:
2929 midgard_condition_true
;
2931 midgard_jmp_writeout_op op
=
2932 is_discard
? midgard_jmp_writeout_op_discard
:
2933 is_tilebuf_wait
? midgard_jmp_writeout_op_tilebuffer_pending
:
2934 is_writeout
? midgard_jmp_writeout_op_writeout
:
2935 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2936 midgard_jmp_writeout_op_branch_cond
;
2939 midgard_branch_extended branch
=
2940 midgard_create_branch_extended(
2945 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2946 } else if (is_conditional
|| is_special
) {
2947 midgard_branch_cond branch
= {
2949 .dest_tag
= dest_tag
,
2950 .offset
= quadword_offset
,
2954 assert(branch
.offset
== quadword_offset
);
2956 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2958 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2960 midgard_branch_uncond branch
= {
2962 .dest_tag
= dest_tag
,
2963 .offset
= quadword_offset
,
2967 assert(branch
.offset
== quadword_offset
);
2969 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2977 /* Emit flat binary from the instruction arrays. Iterate each block in
2978 * sequence. Save instruction boundaries such that lookahead tags can
2979 * be assigned easily */
2981 /* Cache _all_ bundles in source order for lookahead across failed branches */
2983 int bundle_count
= 0;
2984 mir_foreach_block(ctx
, _block
) {
2985 midgard_block
*block
= (midgard_block
*) _block
;
2986 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2988 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2990 mir_foreach_block(ctx
, _block
) {
2991 midgard_block
*block
= (midgard_block
*) _block
;
2992 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2993 source_order_bundles
[bundle_idx
++] = bundle
;
2997 int current_bundle
= 0;
2999 /* Midgard prefetches instruction types, so during emission we
3000 * need to lookahead. Unless this is the last instruction, in
3001 * which we return 1. */
3003 mir_foreach_block(ctx
, _block
) {
3004 midgard_block
*block
= (midgard_block
*) _block
;
3005 mir_foreach_bundle_in_block(block
, bundle
) {
3008 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
3009 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
3011 emit_binary_bundle(ctx
, block
, bundle
, compiled
, lookahead
);
3015 /* TODO: Free deeper */
3016 //util_dynarray_fini(&block->instructions);
3019 free(source_order_bundles
);
3021 /* Report the very first tag executed */
3022 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3024 /* Deal with off-by-one related to the fencepost problem */
3025 program
->work_register_count
= ctx
->work_registers
+ 1;
3026 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3028 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3029 program
->tls_size
= ctx
->tls_size
;
3031 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3032 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
3034 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
3035 unsigned nr_bundles
= 0, nr_ins
= 0;
3037 /* Count instructions and bundles */
3039 mir_foreach_block(ctx
, _block
) {
3040 midgard_block
*block
= (midgard_block
*) _block
;
3041 nr_bundles
+= util_dynarray_num_elements(
3042 &block
->bundles
, midgard_bundle
);
3044 mir_foreach_bundle_in_block(block
, bun
)
3045 nr_ins
+= bun
->instruction_count
;
3048 /* Calculate thread count. There are certain cutoffs by
3049 * register count for thread count */
3051 unsigned nr_registers
= program
->work_register_count
;
3053 unsigned nr_threads
=
3054 (nr_registers
<= 4) ? 4 :
3055 (nr_registers
<= 8) ? 2 :
3060 fprintf(stderr
, "shader%d - %s shader: "
3061 "%u inst, %u bundles, %u quadwords, "
3062 "%u registers, %u threads, %u loops, "
3063 "%u:%u spills:fills\n",
3065 ctx
->is_blend
? "PAN_SHADER_BLEND" :
3066 gl_shader_stage_name(ctx
->stage
),
3067 nr_ins
, nr_bundles
, ctx
->quadword_count
,
3068 nr_registers
, nr_threads
,
3070 ctx
->spills
, ctx
->fills
);