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pan/midgard: Lower SSBOs in NIR
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
44
45 #include "midgard.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
49 #include "helpers.h"
50 #include "compiler.h"
51 #include "midgard_quirks.h"
52
53 #include "disassemble.h"
54
55 static const struct debug_named_value debug_options[] = {
56 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
59 DEBUG_NAMED_VALUE_END
60 };
61
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
63
64 unsigned SHADER_DB_COUNT = 0;
65
66 int midgard_debug = 0;
67
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72 static midgard_block *
73 create_empty_block(compiler_context *ctx)
74 {
75 midgard_block *blk = rzalloc(ctx, midgard_block);
76
77 blk->predecessors = _mesa_set_create(blk,
78 _mesa_hash_pointer,
79 _mesa_key_pointer_equal);
80
81 blk->source_id = ctx->block_source_count++;
82
83 return blk;
84 }
85
86 static void
87 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
88 {
89 assert(block);
90 assert(successor);
91
92 /* Deduplicate */
93 for (unsigned i = 0; i < block->nr_successors; ++i) {
94 if (block->successors[i] == successor)
95 return;
96 }
97
98 block->successors[block->nr_successors++] = successor;
99 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
100
101 /* Note the predecessor in the other direction */
102 _mesa_set_add(successor->predecessors, block);
103 }
104
105 static void
106 schedule_barrier(compiler_context *ctx)
107 {
108 midgard_block *temp = ctx->after_block;
109 ctx->after_block = create_empty_block(ctx);
110 ctx->block_count++;
111 list_addtail(&ctx->after_block->link, &ctx->blocks);
112 list_inithead(&ctx->after_block->instructions);
113 midgard_block_add_successor(ctx->current_block, ctx->after_block);
114 ctx->current_block = ctx->after_block;
115 ctx->after_block = temp;
116 }
117
118 /* Helpers to generate midgard_instruction's using macro magic, since every
119 * driver seems to do it that way */
120
121 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
122
123 #define M_LOAD_STORE(name, store) \
124 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
125 midgard_instruction i = { \
126 .type = TAG_LOAD_STORE_4, \
127 .mask = 0xF, \
128 .dest = ~0, \
129 .src = { ~0, ~0, ~0, ~0 }, \
130 .swizzle = SWIZZLE_IDENTITY_4, \
131 .load_store = { \
132 .op = midgard_op_##name, \
133 .address = address \
134 } \
135 }; \
136 \
137 if (store) \
138 i.src[0] = ssa; \
139 else \
140 i.dest = ssa; \
141 \
142 return i; \
143 }
144
145 #define M_LOAD(name) M_LOAD_STORE(name, false)
146 #define M_STORE(name) M_LOAD_STORE(name, true)
147
148 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
149 * the corresponding Midgard source */
150
151 static midgard_vector_alu_src
152 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
153 bool half, bool sext)
154 {
155 /* Figure out how many components there are so we can adjust.
156 * Specifically we want to broadcast the last channel so things like
157 * ball2/3 work.
158 */
159
160 if (broadcast_count && src) {
161 uint8_t last_component = src->swizzle[broadcast_count - 1];
162
163 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
164 src->swizzle[c] = last_component;
165 }
166 }
167
168 midgard_vector_alu_src alu_src = {
169 .rep_low = 0,
170 .rep_high = 0,
171 .half = half
172 };
173
174 if (is_int) {
175 alu_src.mod = midgard_int_normal;
176
177 /* Sign/zero-extend if needed */
178
179 if (half) {
180 alu_src.mod = sext ?
181 midgard_int_sign_extend
182 : midgard_int_zero_extend;
183 }
184
185 /* These should have been lowered away */
186 if (src)
187 assert(!(src->abs || src->negate));
188 } else {
189 if (src)
190 alu_src.mod = (src->abs << 0) | (src->negate << 1);
191 }
192
193 return alu_src;
194 }
195
196 /* load/store instructions have both 32-bit and 16-bit variants, depending on
197 * whether we are using vectors composed of highp or mediump. At the moment, we
198 * don't support half-floats -- this requires changes in other parts of the
199 * compiler -- therefore the 16-bit versions are commented out. */
200
201 //M_LOAD(ld_attr_16);
202 M_LOAD(ld_attr_32);
203 //M_LOAD(ld_vary_16);
204 M_LOAD(ld_vary_32);
205 M_LOAD(ld_ubo_int4);
206 M_LOAD(ld_int4);
207 M_STORE(st_int4);
208 M_LOAD(ld_color_buffer_32u);
209 //M_STORE(st_vary_16);
210 M_STORE(st_vary_32);
211 M_LOAD(ld_cubemap_coords);
212 M_LOAD(ld_compute_id);
213
214 static midgard_instruction
215 v_branch(bool conditional, bool invert)
216 {
217 midgard_instruction ins = {
218 .type = TAG_ALU_4,
219 .unit = ALU_ENAB_BRANCH,
220 .compact_branch = true,
221 .branch = {
222 .conditional = conditional,
223 .invert_conditional = invert
224 },
225 .dest = ~0,
226 .src = { ~0, ~0, ~0, ~0 },
227 };
228
229 return ins;
230 }
231
232 static midgard_branch_extended
233 midgard_create_branch_extended( midgard_condition cond,
234 midgard_jmp_writeout_op op,
235 unsigned dest_tag,
236 signed quadword_offset)
237 {
238 /* The condition code is actually a LUT describing a function to
239 * combine multiple condition codes. However, we only support a single
240 * condition code at the moment, so we just duplicate over a bunch of
241 * times. */
242
243 uint16_t duplicated_cond =
244 (cond << 14) |
245 (cond << 12) |
246 (cond << 10) |
247 (cond << 8) |
248 (cond << 6) |
249 (cond << 4) |
250 (cond << 2) |
251 (cond << 0);
252
253 midgard_branch_extended branch = {
254 .op = op,
255 .dest_tag = dest_tag,
256 .offset = quadword_offset,
257 .cond = duplicated_cond
258 };
259
260 return branch;
261 }
262
263 static void
264 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
265 {
266 ins->has_constants = true;
267 memcpy(&ins->constants, constants, 16);
268 }
269
270 static int
271 glsl_type_size(const struct glsl_type *type, bool bindless)
272 {
273 return glsl_count_attribute_slots(type, false);
274 }
275
276 /* Lower fdot2 to a vector multiplication followed by channel addition */
277 static void
278 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
279 {
280 if (alu->op != nir_op_fdot2)
281 return;
282
283 b->cursor = nir_before_instr(&alu->instr);
284
285 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
286 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
287
288 nir_ssa_def *product = nir_fmul(b, src0, src1);
289
290 nir_ssa_def *sum = nir_fadd(b,
291 nir_channel(b, product, 0),
292 nir_channel(b, product, 1));
293
294 /* Replace the fdot2 with this sum */
295 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
296 }
297
298 /* TODO: ssbo_size */
299 static int
300 midgard_sysval_for_ssbo(nir_intrinsic_instr *instr)
301 {
302 nir_src index = instr->src[0];
303 assert(nir_src_is_const(index));
304 uint32_t uindex = nir_src_as_uint(index);
305
306 return PAN_SYSVAL(SSBO, uindex);
307 }
308
309 static int
310 midgard_sysval_for_sampler(nir_intrinsic_instr *instr)
311 {
312 /* TODO: indirect samplers !!! */
313 nir_src index = instr->src[0];
314 assert(nir_src_is_const(index));
315 uint32_t uindex = nir_src_as_uint(index);
316
317 return PAN_SYSVAL(SAMPLER, uindex);
318 }
319
320 static unsigned
321 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
322 {
323 switch (instr->intrinsic) {
324 case nir_intrinsic_load_viewport_scale:
325 return PAN_SYSVAL_VIEWPORT_SCALE;
326 case nir_intrinsic_load_viewport_offset:
327 return PAN_SYSVAL_VIEWPORT_OFFSET;
328 case nir_intrinsic_load_num_work_groups:
329 return PAN_SYSVAL_NUM_WORK_GROUPS;
330 case nir_intrinsic_load_ssbo_address:
331 return midgard_sysval_for_ssbo(instr);
332 case nir_intrinsic_load_sampler_lod_parameters_pan:
333 return midgard_sysval_for_sampler(instr);
334 default:
335 return ~0;
336 }
337 }
338
339 static int sysval_for_instr(compiler_context *ctx, nir_instr *instr,
340 unsigned *dest)
341 {
342 nir_intrinsic_instr *intr;
343 nir_dest *dst = NULL;
344 nir_tex_instr *tex;
345 unsigned sysval = ~0;
346
347 switch (instr->type) {
348 case nir_instr_type_intrinsic:
349 intr = nir_instr_as_intrinsic(instr);
350 sysval = midgard_nir_sysval_for_intrinsic(intr);
351 dst = &intr->dest;
352 break;
353 case nir_instr_type_tex:
354 tex = nir_instr_as_tex(instr);
355 if (tex->op != nir_texop_txs)
356 break;
357
358 sysval = PAN_SYSVAL(TEXTURE_SIZE,
359 PAN_TXS_SYSVAL_ID(tex->texture_index,
360 nir_tex_instr_dest_size(tex) -
361 (tex->is_array ? 1 : 0),
362 tex->is_array));
363 dst = &tex->dest;
364 break;
365 default:
366 break;
367 }
368
369 if (dest && dst)
370 *dest = nir_dest_index(ctx, dst);
371
372 return sysval;
373 }
374
375 static void
376 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
377 {
378 int sysval;
379
380 sysval = sysval_for_instr(ctx, instr, NULL);
381 if (sysval < 0)
382 return;
383
384 /* We have a sysval load; check if it's already been assigned */
385
386 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
387 return;
388
389 /* It hasn't -- so assign it now! */
390
391 unsigned id = ctx->sysval_count++;
392 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
393 ctx->sysvals[id] = sysval;
394 }
395
396 static void
397 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
398 {
399 ctx->sysval_count = 0;
400
401 nir_foreach_function(function, shader) {
402 if (!function->impl) continue;
403
404 nir_foreach_block(block, function->impl) {
405 nir_foreach_instr_safe(instr, block) {
406 midgard_nir_assign_sysval_body(ctx, instr);
407 }
408 }
409 }
410 }
411
412 static bool
413 midgard_nir_lower_fdot2(nir_shader *shader)
414 {
415 bool progress = false;
416
417 nir_foreach_function(function, shader) {
418 if (!function->impl) continue;
419
420 nir_builder _b;
421 nir_builder *b = &_b;
422 nir_builder_init(b, function->impl);
423
424 nir_foreach_block(block, function->impl) {
425 nir_foreach_instr_safe(instr, block) {
426 if (instr->type != nir_instr_type_alu) continue;
427
428 nir_alu_instr *alu = nir_instr_as_alu(instr);
429 midgard_nir_lower_fdot2_body(b, alu);
430
431 progress |= true;
432 }
433 }
434
435 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
436
437 }
438
439 return progress;
440 }
441
442 /* Midgard can't write depth and stencil separately. It has to happen in a
443 * single store operation containing both. Let's add a panfrost specific
444 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
445 * one.
446 */
447 static bool
448 midgard_nir_lower_zs_store(nir_shader *nir)
449 {
450 if (nir->info.stage != MESA_SHADER_FRAGMENT)
451 return false;
452
453 nir_variable *z_var = NULL, *s_var = NULL;
454
455 nir_foreach_variable(var, &nir->outputs) {
456 if (var->data.location == FRAG_RESULT_DEPTH)
457 z_var = var;
458 else if (var->data.location == FRAG_RESULT_STENCIL)
459 s_var = var;
460 }
461
462 if (!z_var && !s_var)
463 return false;
464
465 bool progress = false;
466
467 nir_foreach_function(function, nir) {
468 if (!function->impl) continue;
469
470 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
471
472 nir_foreach_block(block, function->impl) {
473 nir_foreach_instr_safe(instr, block) {
474 if (instr->type != nir_instr_type_intrinsic)
475 continue;
476
477 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
478 if (intr->intrinsic != nir_intrinsic_store_output)
479 continue;
480
481 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
482 assert(!z_store);
483 z_store = intr;
484 last_store = intr;
485 }
486
487 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
488 assert(!s_store);
489 s_store = intr;
490 last_store = intr;
491 }
492 }
493 }
494
495 if (!z_store && !s_store) continue;
496
497 nir_builder b;
498 nir_builder_init(&b, function->impl);
499
500 b.cursor = nir_before_instr(&last_store->instr);
501
502 nir_ssa_def *zs_store_src;
503
504 if (z_store && s_store) {
505 nir_ssa_def *srcs[2] = {
506 nir_ssa_for_src(&b, z_store->src[0], 1),
507 nir_ssa_for_src(&b, s_store->src[0], 1),
508 };
509
510 zs_store_src = nir_vec(&b, srcs, 2);
511 } else {
512 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
513 }
514
515 nir_intrinsic_instr *zs_store;
516
517 zs_store = nir_intrinsic_instr_create(b.shader,
518 nir_intrinsic_store_zs_output_pan);
519 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
520 zs_store->num_components = z_store && s_store ? 2 : 1;
521 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
522
523 /* Replace the Z and S store by a ZS store */
524 nir_builder_instr_insert(&b, &zs_store->instr);
525
526 if (z_store)
527 nir_instr_remove(&z_store->instr);
528
529 if (s_store)
530 nir_instr_remove(&s_store->instr);
531
532 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
533 progress = true;
534 }
535
536 return progress;
537 }
538
539 /* Flushes undefined values to zero */
540
541 static void
542 optimise_nir(nir_shader *nir, unsigned quirks)
543 {
544 bool progress;
545 unsigned lower_flrp =
546 (nir->options->lower_flrp16 ? 16 : 0) |
547 (nir->options->lower_flrp32 ? 32 : 0) |
548 (nir->options->lower_flrp64 ? 64 : 0);
549
550 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
551 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
552
553 nir_lower_tex_options lower_tex_options = {
554 .lower_txs_lod = true,
555 .lower_txp = ~0,
556 .lower_tex_without_implicit_lod =
557 (quirks & MIDGARD_EXPLICIT_LOD),
558
559 /* TODO: we have native gradient.. */
560 .lower_txd = true,
561 };
562
563 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
564
565 /* Must lower fdot2 after tex is lowered */
566 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
567
568 /* T720 is broken. */
569
570 if (quirks & MIDGARD_BROKEN_LOD)
571 NIR_PASS_V(nir, midgard_nir_lod_errata);
572
573 do {
574 progress = false;
575
576 NIR_PASS(progress, nir, nir_lower_var_copies);
577 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
578
579 NIR_PASS(progress, nir, nir_copy_prop);
580 NIR_PASS(progress, nir, nir_opt_remove_phis);
581 NIR_PASS(progress, nir, nir_opt_dce);
582 NIR_PASS(progress, nir, nir_opt_dead_cf);
583 NIR_PASS(progress, nir, nir_opt_cse);
584 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
585 NIR_PASS(progress, nir, nir_opt_algebraic);
586 NIR_PASS(progress, nir, nir_opt_constant_folding);
587
588 if (lower_flrp != 0) {
589 bool lower_flrp_progress = false;
590 NIR_PASS(lower_flrp_progress,
591 nir,
592 nir_lower_flrp,
593 lower_flrp,
594 false /* always_precise */,
595 nir->options->lower_ffma);
596 if (lower_flrp_progress) {
597 NIR_PASS(progress, nir,
598 nir_opt_constant_folding);
599 progress = true;
600 }
601
602 /* Nothing should rematerialize any flrps, so we only
603 * need to do this lowering once.
604 */
605 lower_flrp = 0;
606 }
607
608 NIR_PASS(progress, nir, nir_opt_undef);
609 NIR_PASS(progress, nir, nir_undef_to_zero);
610
611 NIR_PASS(progress, nir, nir_opt_loop_unroll,
612 nir_var_shader_in |
613 nir_var_shader_out |
614 nir_var_function_temp);
615
616 NIR_PASS(progress, nir, nir_opt_vectorize);
617 } while (progress);
618
619 /* Must be run at the end to prevent creation of fsin/fcos ops */
620 NIR_PASS(progress, nir, midgard_nir_scale_trig);
621
622 do {
623 progress = false;
624
625 NIR_PASS(progress, nir, nir_opt_dce);
626 NIR_PASS(progress, nir, nir_opt_algebraic);
627 NIR_PASS(progress, nir, nir_opt_constant_folding);
628 NIR_PASS(progress, nir, nir_copy_prop);
629 } while (progress);
630
631 NIR_PASS(progress, nir, nir_opt_algebraic_late);
632
633 /* We implement booleans as 32-bit 0/~0 */
634 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
635
636 /* Now that booleans are lowered, we can run out late opts */
637 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
638
639 /* Lower mods for float ops only. Integer ops don't support modifiers
640 * (saturate doesn't make sense on integers, neg/abs require dedicated
641 * instructions) */
642
643 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
644 NIR_PASS(progress, nir, nir_copy_prop);
645 NIR_PASS(progress, nir, nir_opt_dce);
646
647 /* Take us out of SSA */
648 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
649 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
650
651 /* We are a vector architecture; write combine where possible */
652 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
653 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
654
655 NIR_PASS(progress, nir, nir_opt_dce);
656 }
657
658 /* Do not actually emit a load; instead, cache the constant for inlining */
659
660 static void
661 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
662 {
663 nir_ssa_def def = instr->def;
664
665 midgard_constants *consts = rzalloc(NULL, midgard_constants);
666
667 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
668
669 #define RAW_CONST_COPY(bits) \
670 nir_const_value_to_array(consts->u##bits, instr->value, \
671 instr->def.num_components, u##bits)
672
673 switch (instr->def.bit_size) {
674 case 64:
675 RAW_CONST_COPY(64);
676 break;
677 case 32:
678 RAW_CONST_COPY(32);
679 break;
680 case 16:
681 RAW_CONST_COPY(16);
682 break;
683 case 8:
684 RAW_CONST_COPY(8);
685 break;
686 default:
687 unreachable("Invalid bit_size for load_const instruction\n");
688 }
689
690 /* Shifted for SSA, +1 for off-by-one */
691 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
692 }
693
694 /* Normally constants are embedded implicitly, but for I/O and such we have to
695 * explicitly emit a move with the constant source */
696
697 static void
698 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
699 {
700 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
701
702 if (constant_value) {
703 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
704 attach_constants(ctx, &ins, constant_value, node + 1);
705 emit_mir_instruction(ctx, ins);
706 }
707 }
708
709 static bool
710 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
711 {
712 unsigned comp = src->swizzle[0];
713
714 for (unsigned c = 1; c < nr_components; ++c) {
715 if (src->swizzle[c] != comp)
716 return true;
717 }
718
719 return false;
720 }
721
722 #define ALU_CASE(nir, _op) \
723 case nir_op_##nir: \
724 op = midgard_alu_op_##_op; \
725 assert(src_bitsize == dst_bitsize); \
726 break;
727
728 #define ALU_CASE_BCAST(nir, _op, count) \
729 case nir_op_##nir: \
730 op = midgard_alu_op_##_op; \
731 broadcast_swizzle = count; \
732 assert(src_bitsize == dst_bitsize); \
733 break;
734 static bool
735 nir_is_fzero_constant(nir_src src)
736 {
737 if (!nir_src_is_const(src))
738 return false;
739
740 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
741 if (nir_src_comp_as_float(src, c) != 0.0)
742 return false;
743 }
744
745 return true;
746 }
747
748 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
749 * special treatment override this anyway. */
750
751 static midgard_reg_mode
752 reg_mode_for_nir(nir_alu_instr *instr)
753 {
754 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
755
756 switch (src_bitsize) {
757 case 8:
758 return midgard_reg_mode_8;
759 case 16:
760 return midgard_reg_mode_16;
761 case 32:
762 return midgard_reg_mode_32;
763 case 64:
764 return midgard_reg_mode_64;
765 default:
766 unreachable("Invalid bit size");
767 }
768 }
769
770 static void
771 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
772 {
773 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
774 * is handled elsewhere */
775
776 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
777 midgard_emit_derivatives(ctx, instr);
778 return;
779 }
780
781 bool is_ssa = instr->dest.dest.is_ssa;
782
783 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
784 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
785 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
786
787 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
788 * supported. A few do not and are commented for now. Also, there are a
789 * number of NIR ops which Midgard does not support and need to be
790 * lowered, also TODO. This switch block emits the opcode and calling
791 * convention of the Midgard instruction; actual packing is done in
792 * emit_alu below */
793
794 unsigned op;
795
796 /* Number of components valid to check for the instruction (the rest
797 * will be forced to the last), or 0 to use as-is. Relevant as
798 * ball-type instructions have a channel count in NIR but are all vec4
799 * in Midgard */
800
801 unsigned broadcast_swizzle = 0;
802
803 /* What register mode should we operate in? */
804 midgard_reg_mode reg_mode =
805 reg_mode_for_nir(instr);
806
807 /* Do we need a destination override? Used for inline
808 * type conversion */
809
810 midgard_dest_override dest_override =
811 midgard_dest_override_none;
812
813 /* Should we use a smaller respective source and sign-extend? */
814
815 bool half_1 = false, sext_1 = false;
816 bool half_2 = false, sext_2 = false;
817
818 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
819 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
820
821 switch (instr->op) {
822 ALU_CASE(fadd, fadd);
823 ALU_CASE(fmul, fmul);
824 ALU_CASE(fmin, fmin);
825 ALU_CASE(fmax, fmax);
826 ALU_CASE(imin, imin);
827 ALU_CASE(imax, imax);
828 ALU_CASE(umin, umin);
829 ALU_CASE(umax, umax);
830 ALU_CASE(ffloor, ffloor);
831 ALU_CASE(fround_even, froundeven);
832 ALU_CASE(ftrunc, ftrunc);
833 ALU_CASE(fceil, fceil);
834 ALU_CASE(fdot3, fdot3);
835 ALU_CASE(fdot4, fdot4);
836 ALU_CASE(iadd, iadd);
837 ALU_CASE(isub, isub);
838 ALU_CASE(imul, imul);
839
840 /* Zero shoved as second-arg */
841 ALU_CASE(iabs, iabsdiff);
842
843 ALU_CASE(mov, imov);
844
845 ALU_CASE(feq32, feq);
846 ALU_CASE(fne32, fne);
847 ALU_CASE(flt32, flt);
848 ALU_CASE(ieq32, ieq);
849 ALU_CASE(ine32, ine);
850 ALU_CASE(ilt32, ilt);
851 ALU_CASE(ult32, ult);
852
853 /* We don't have a native b2f32 instruction. Instead, like many
854 * GPUs, we exploit booleans as 0/~0 for false/true, and
855 * correspondingly AND
856 * by 1.0 to do the type conversion. For the moment, prime us
857 * to emit:
858 *
859 * iand [whatever], #0
860 *
861 * At the end of emit_alu (as MIR), we'll fix-up the constant
862 */
863
864 ALU_CASE(b2f32, iand);
865 ALU_CASE(b2i32, iand);
866
867 /* Likewise, we don't have a dedicated f2b32 instruction, but
868 * we can do a "not equal to 0.0" test. */
869
870 ALU_CASE(f2b32, fne);
871 ALU_CASE(i2b32, ine);
872
873 ALU_CASE(frcp, frcp);
874 ALU_CASE(frsq, frsqrt);
875 ALU_CASE(fsqrt, fsqrt);
876 ALU_CASE(fexp2, fexp2);
877 ALU_CASE(flog2, flog2);
878
879 ALU_CASE(f2i64, f2i_rtz);
880 ALU_CASE(f2u64, f2u_rtz);
881 ALU_CASE(i2f64, i2f_rtz);
882 ALU_CASE(u2f64, u2f_rtz);
883
884 ALU_CASE(f2i32, f2i_rtz);
885 ALU_CASE(f2u32, f2u_rtz);
886 ALU_CASE(i2f32, i2f_rtz);
887 ALU_CASE(u2f32, u2f_rtz);
888
889 ALU_CASE(f2i16, f2i_rtz);
890 ALU_CASE(f2u16, f2u_rtz);
891 ALU_CASE(i2f16, i2f_rtz);
892 ALU_CASE(u2f16, u2f_rtz);
893
894 ALU_CASE(fsin, fsin);
895 ALU_CASE(fcos, fcos);
896
897 /* We'll set invert */
898 ALU_CASE(inot, imov);
899 ALU_CASE(iand, iand);
900 ALU_CASE(ior, ior);
901 ALU_CASE(ixor, ixor);
902 ALU_CASE(ishl, ishl);
903 ALU_CASE(ishr, iasr);
904 ALU_CASE(ushr, ilsr);
905
906 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
907 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
908 ALU_CASE(b32all_fequal4, fball_eq);
909
910 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
911 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
912 ALU_CASE(b32any_fnequal4, fbany_neq);
913
914 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
915 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
916 ALU_CASE(b32all_iequal4, iball_eq);
917
918 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
919 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
920 ALU_CASE(b32any_inequal4, ibany_neq);
921
922 /* Source mods will be shoved in later */
923 ALU_CASE(fabs, fmov);
924 ALU_CASE(fneg, fmov);
925 ALU_CASE(fsat, fmov);
926
927 /* For size conversion, we use a move. Ideally though we would squash
928 * these ops together; maybe that has to happen after in NIR as part of
929 * propagation...? An earlier algebraic pass ensured we step down by
930 * only / exactly one size. If stepping down, we use a dest override to
931 * reduce the size; if stepping up, we use a larger-sized move with a
932 * half source and a sign/zero-extension modifier */
933
934 case nir_op_i2i8:
935 case nir_op_i2i16:
936 case nir_op_i2i32:
937 case nir_op_i2i64:
938 /* If we end up upscale, we'll need a sign-extend on the
939 * operand (the second argument) */
940
941 sext_2 = true;
942 /* fallthrough */
943 case nir_op_u2u8:
944 case nir_op_u2u16:
945 case nir_op_u2u32:
946 case nir_op_u2u64:
947 case nir_op_f2f16:
948 case nir_op_f2f32:
949 case nir_op_f2f64: {
950 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
951 instr->op == nir_op_f2f64)
952 op = midgard_alu_op_fmov;
953 else
954 op = midgard_alu_op_imov;
955
956 if (dst_bitsize == (src_bitsize * 2)) {
957 /* Converting up */
958 half_2 = true;
959
960 /* Use a greater register mode */
961 reg_mode++;
962 } else if (src_bitsize == (dst_bitsize * 2)) {
963 /* Converting down */
964 dest_override = midgard_dest_override_lower;
965 }
966
967 break;
968 }
969
970 /* For greater-or-equal, we lower to less-or-equal and flip the
971 * arguments */
972
973 case nir_op_fge:
974 case nir_op_fge32:
975 case nir_op_ige32:
976 case nir_op_uge32: {
977 op =
978 instr->op == nir_op_fge ? midgard_alu_op_fle :
979 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
980 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
981 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
982 0;
983
984 /* Swap via temporary */
985 nir_alu_src temp = instr->src[1];
986 instr->src[1] = instr->src[0];
987 instr->src[0] = temp;
988
989 break;
990 }
991
992 case nir_op_b32csel: {
993 /* Midgard features both fcsel and icsel, depending on
994 * the type of the arguments/output. However, as long
995 * as we're careful we can _always_ use icsel and
996 * _never_ need fcsel, since the latter does additional
997 * floating-point-specific processing whereas the
998 * former just moves bits on the wire. It's not obvious
999 * why these are separate opcodes, save for the ability
1000 * to do things like sat/pos/abs/neg for free */
1001
1002 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
1003 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
1004
1005 /* The condition is the first argument; move the other
1006 * arguments up one to be a binary instruction for
1007 * Midgard with the condition last */
1008
1009 nir_alu_src temp = instr->src[2];
1010
1011 instr->src[2] = instr->src[0];
1012 instr->src[0] = instr->src[1];
1013 instr->src[1] = temp;
1014
1015 break;
1016 }
1017
1018 default:
1019 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
1020 assert(0);
1021 return;
1022 }
1023
1024 /* Midgard can perform certain modifiers on output of an ALU op */
1025 unsigned outmod;
1026
1027 if (midgard_is_integer_out_op(op)) {
1028 outmod = midgard_outmod_int_wrap;
1029 } else {
1030 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
1031 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
1032 }
1033
1034 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1035
1036 if (instr->op == nir_op_fmax) {
1037 if (nir_is_fzero_constant(instr->src[0].src)) {
1038 op = midgard_alu_op_fmov;
1039 nr_inputs = 1;
1040 outmod = midgard_outmod_pos;
1041 instr->src[0] = instr->src[1];
1042 } else if (nir_is_fzero_constant(instr->src[1].src)) {
1043 op = midgard_alu_op_fmov;
1044 nr_inputs = 1;
1045 outmod = midgard_outmod_pos;
1046 }
1047 }
1048
1049 /* Fetch unit, quirks, etc information */
1050 unsigned opcode_props = alu_opcode_props[op].props;
1051 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
1052
1053 /* src0 will always exist afaik, but src1 will not for 1-argument
1054 * instructions. The latter can only be fetched if the instruction
1055 * needs it, or else we may segfault. */
1056
1057 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
1058 unsigned src1 = nr_inputs >= 2 ? nir_alu_src_index(ctx, &instr->src[1]) : ~0;
1059 unsigned src2 = nr_inputs == 3 ? nir_alu_src_index(ctx, &instr->src[2]) : ~0;
1060 assert(nr_inputs <= 3);
1061
1062 /* Rather than use the instruction generation helpers, we do it
1063 * ourselves here to avoid the mess */
1064
1065 midgard_instruction ins = {
1066 .type = TAG_ALU_4,
1067 .src = {
1068 quirk_flipped_r24 ? ~0 : src0,
1069 quirk_flipped_r24 ? src0 : src1,
1070 src2,
1071 ~0
1072 },
1073 .dest = dest,
1074 };
1075
1076 nir_alu_src *nirmods[3] = { NULL };
1077
1078 if (nr_inputs >= 2) {
1079 nirmods[0] = &instr->src[0];
1080 nirmods[1] = &instr->src[1];
1081 } else if (nr_inputs == 1) {
1082 nirmods[quirk_flipped_r24] = &instr->src[0];
1083 } else {
1084 assert(0);
1085 }
1086
1087 if (nr_inputs == 3)
1088 nirmods[2] = &instr->src[2];
1089
1090 /* These were lowered to a move, so apply the corresponding mod */
1091
1092 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1093 nir_alu_src *s = nirmods[quirk_flipped_r24];
1094
1095 if (instr->op == nir_op_fneg)
1096 s->negate = !s->negate;
1097
1098 if (instr->op == nir_op_fabs)
1099 s->abs = !s->abs;
1100 }
1101
1102 bool is_int = midgard_is_integer_op(op);
1103
1104 ins.mask = mask_of(nr_components);
1105
1106 midgard_vector_alu alu = {
1107 .op = op,
1108 .reg_mode = reg_mode,
1109 .dest_override = dest_override,
1110 .outmod = outmod,
1111
1112 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
1113 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
1114 };
1115
1116 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1117
1118 if (!is_ssa)
1119 ins.mask &= instr->dest.write_mask;
1120
1121 for (unsigned m = 0; m < 3; ++m) {
1122 if (!nirmods[m])
1123 continue;
1124
1125 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
1126 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
1127
1128 /* Replicate. TODO: remove when vec16 lands */
1129 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
1130 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
1131 }
1132
1133 if (nr_inputs == 3) {
1134 /* Conditions can't have mods */
1135 assert(!nirmods[2]->abs);
1136 assert(!nirmods[2]->negate);
1137 }
1138
1139 ins.alu = alu;
1140
1141 /* Late fixup for emulated instructions */
1142
1143 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1144 /* Presently, our second argument is an inline #0 constant.
1145 * Switch over to an embedded 1.0 constant (that can't fit
1146 * inline, since we're 32-bit, not 16-bit like the inline
1147 * constants) */
1148
1149 ins.has_inline_constant = false;
1150 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1151 ins.has_constants = true;
1152
1153 if (instr->op == nir_op_b2f32)
1154 ins.constants.f32[0] = 1.0f;
1155 else
1156 ins.constants.i32[0] = 1;
1157
1158 for (unsigned c = 0; c < 16; ++c)
1159 ins.swizzle[1][c] = 0;
1160 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1161 /* Lots of instructions need a 0 plonked in */
1162 ins.has_inline_constant = false;
1163 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1164 ins.has_constants = true;
1165 ins.constants.u32[0] = 0;
1166
1167 for (unsigned c = 0; c < 16; ++c)
1168 ins.swizzle[1][c] = 0;
1169 } else if (instr->op == nir_op_inot) {
1170 ins.invert = true;
1171 }
1172
1173 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1174 /* To avoid duplicating the lookup tables (probably), true LUT
1175 * instructions can only operate as if they were scalars. Lower
1176 * them here by changing the component. */
1177
1178 unsigned orig_mask = ins.mask;
1179
1180 for (int i = 0; i < nr_components; ++i) {
1181 /* Mask the associated component, dropping the
1182 * instruction if needed */
1183
1184 ins.mask = 1 << i;
1185 ins.mask &= orig_mask;
1186
1187 if (!ins.mask)
1188 continue;
1189
1190 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1191 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1192
1193 emit_mir_instruction(ctx, ins);
1194 }
1195 } else {
1196 emit_mir_instruction(ctx, ins);
1197 }
1198 }
1199
1200 #undef ALU_CASE
1201
1202 static void
1203 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1204 {
1205 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1206 unsigned nir_mask = 0;
1207 unsigned dsize = 0;
1208
1209 if (is_read) {
1210 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1211 dsize = nir_dest_bit_size(intr->dest);
1212 } else {
1213 nir_mask = nir_intrinsic_write_mask(intr);
1214 dsize = 32;
1215 }
1216
1217 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1218 unsigned bytemask = mir_to_bytemask(mir_mode_for_destsize(dsize), nir_mask);
1219 mir_set_bytemask(ins, bytemask);
1220
1221 if (dsize == 64)
1222 ins->load_64 = true;
1223 }
1224
1225 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1226 * optimized) versions of UBO #0 */
1227
1228 static midgard_instruction *
1229 emit_ubo_read(
1230 compiler_context *ctx,
1231 nir_instr *instr,
1232 unsigned dest,
1233 unsigned offset,
1234 nir_src *indirect_offset,
1235 unsigned indirect_shift,
1236 unsigned index)
1237 {
1238 /* TODO: half-floats */
1239
1240 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1241 ins.constants.u32[0] = offset;
1242
1243 if (instr->type == nir_instr_type_intrinsic)
1244 mir_set_intr_mask(instr, &ins, true);
1245
1246 if (indirect_offset) {
1247 ins.src[2] = nir_src_index(ctx, indirect_offset);
1248 ins.load_store.arg_2 = (indirect_shift << 5);
1249 } else {
1250 ins.load_store.arg_2 = 0x1E;
1251 }
1252
1253 ins.load_store.arg_1 = index;
1254
1255 return emit_mir_instruction(ctx, ins);
1256 }
1257
1258 /* SSBO reads are like UBO reads if you squint */
1259
1260 static void
1261 emit_global(
1262 compiler_context *ctx,
1263 nir_instr *instr,
1264 bool is_read,
1265 unsigned srcdest,
1266 nir_src *indirect_offset)
1267 {
1268 /* TODO: types */
1269
1270 midgard_instruction ins;
1271
1272 if (is_read)
1273 ins = m_ld_int4(srcdest, 0);
1274 else
1275 ins = m_st_int4(srcdest, 0);
1276
1277 /* The source array:
1278 *
1279 * src[0] = store ? value : unused
1280 * src[1] = arg_1
1281 * src[2] = arg_2
1282 *
1283 * We would like arg_1 = the address and
1284 * arg_2 = the offset.
1285 */
1286
1287 /* TODO: What is this? */
1288 ins.load_store.arg_1 = 0x7E;
1289 ins.src[2] = nir_src_index(ctx, indirect_offset);
1290 mir_set_intr_mask(instr, &ins, is_read);
1291
1292 emit_mir_instruction(ctx, ins);
1293 }
1294
1295 static void
1296 emit_varying_read(
1297 compiler_context *ctx,
1298 unsigned dest, unsigned offset,
1299 unsigned nr_comp, unsigned component,
1300 nir_src *indirect_offset, nir_alu_type type, bool flat)
1301 {
1302 /* XXX: Half-floats? */
1303 /* TODO: swizzle, mask */
1304
1305 midgard_instruction ins = m_ld_vary_32(dest, offset);
1306 ins.mask = mask_of(nr_comp);
1307
1308 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1309 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1310
1311 midgard_varying_parameter p = {
1312 .is_varying = 1,
1313 .interpolation = midgard_interp_default,
1314 .flat = flat,
1315 };
1316
1317 unsigned u;
1318 memcpy(&u, &p, sizeof(p));
1319 ins.load_store.varying_parameters = u;
1320
1321 if (indirect_offset)
1322 ins.src[2] = nir_src_index(ctx, indirect_offset);
1323 else
1324 ins.load_store.arg_2 = 0x1E;
1325
1326 ins.load_store.arg_1 = 0x9E;
1327
1328 /* Use the type appropriate load */
1329 switch (type) {
1330 case nir_type_uint:
1331 case nir_type_bool:
1332 ins.load_store.op = midgard_op_ld_vary_32u;
1333 break;
1334 case nir_type_int:
1335 ins.load_store.op = midgard_op_ld_vary_32i;
1336 break;
1337 case nir_type_float:
1338 ins.load_store.op = midgard_op_ld_vary_32;
1339 break;
1340 default:
1341 unreachable("Attempted to load unknown type");
1342 break;
1343 }
1344
1345 emit_mir_instruction(ctx, ins);
1346 }
1347
1348 static void
1349 emit_attr_read(
1350 compiler_context *ctx,
1351 unsigned dest, unsigned offset,
1352 unsigned nr_comp, nir_alu_type t)
1353 {
1354 midgard_instruction ins = m_ld_attr_32(dest, offset);
1355 ins.load_store.arg_1 = 0x1E;
1356 ins.load_store.arg_2 = 0x1E;
1357 ins.mask = mask_of(nr_comp);
1358
1359 /* Use the type appropriate load */
1360 switch (t) {
1361 case nir_type_uint:
1362 case nir_type_bool:
1363 ins.load_store.op = midgard_op_ld_attr_32u;
1364 break;
1365 case nir_type_int:
1366 ins.load_store.op = midgard_op_ld_attr_32i;
1367 break;
1368 case nir_type_float:
1369 ins.load_store.op = midgard_op_ld_attr_32;
1370 break;
1371 default:
1372 unreachable("Attempted to load unknown type");
1373 break;
1374 }
1375
1376 emit_mir_instruction(ctx, ins);
1377 }
1378
1379 void
1380 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override,
1381 unsigned nr_components)
1382 {
1383 unsigned dest = 0;
1384
1385 /* Figure out which uniform this is */
1386 int sysval = sysval_for_instr(ctx, instr, &dest);
1387 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1388
1389 if (dest_override >= 0)
1390 dest = dest_override;
1391
1392 /* Sysvals are prefix uniforms */
1393 unsigned uniform = ((uintptr_t) val) - 1;
1394
1395 /* Emit the read itself -- this is never indirect */
1396 midgard_instruction *ins =
1397 emit_ubo_read(ctx, instr, dest, uniform * 16, NULL, 0, 0);
1398
1399 ins->mask = mask_of(nr_components);
1400 }
1401
1402 static unsigned
1403 compute_builtin_arg(nir_op op)
1404 {
1405 switch (op) {
1406 case nir_intrinsic_load_work_group_id:
1407 return 0x14;
1408 case nir_intrinsic_load_local_invocation_id:
1409 return 0x10;
1410 default:
1411 unreachable("Invalid compute paramater loaded");
1412 }
1413 }
1414
1415 static void
1416 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1417 {
1418 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1419
1420 midgard_instruction *br = ctx->writeout_branch[rt];
1421
1422 assert(!br);
1423
1424 emit_explicit_constant(ctx, src, src);
1425
1426 struct midgard_instruction ins =
1427 v_branch(false, false);
1428
1429 ins.writeout = true;
1430
1431 /* Add dependencies */
1432 ins.src[0] = src;
1433 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1434 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1435
1436 /* Emit the branch */
1437 br = emit_mir_instruction(ctx, ins);
1438 schedule_barrier(ctx);
1439 ctx->writeout_branch[rt] = br;
1440
1441 /* Push our current location = current block count - 1 = where we'll
1442 * jump to. Maybe a bit too clever for my own good */
1443
1444 br->branch.target_block = ctx->block_count - 1;
1445 }
1446
1447 static void
1448 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1449 {
1450 unsigned reg = nir_dest_index(ctx, &instr->dest);
1451 midgard_instruction ins = m_ld_compute_id(reg, 0);
1452 ins.mask = mask_of(3);
1453 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1454 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1455 emit_mir_instruction(ctx, ins);
1456 }
1457
1458 static unsigned
1459 vertex_builtin_arg(nir_op op)
1460 {
1461 switch (op) {
1462 case nir_intrinsic_load_vertex_id:
1463 return PAN_VERTEX_ID;
1464 case nir_intrinsic_load_instance_id:
1465 return PAN_INSTANCE_ID;
1466 default:
1467 unreachable("Invalid vertex builtin");
1468 }
1469 }
1470
1471 static void
1472 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1473 {
1474 unsigned reg = nir_dest_index(ctx, &instr->dest);
1475 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1476 }
1477
1478 static void
1479 emit_control_barrier(compiler_context *ctx)
1480 {
1481 midgard_instruction ins = {
1482 .type = TAG_TEXTURE_4,
1483 .src = { ~0, ~0, ~0, ~0 },
1484 .texture = {
1485 .op = TEXTURE_OP_BARRIER,
1486
1487 /* TODO: optimize */
1488 .barrier_buffer = 1,
1489 .barrier_shared = 1
1490 }
1491 };
1492
1493 emit_mir_instruction(ctx, ins);
1494 }
1495
1496 static const nir_variable *
1497 search_var(struct exec_list *vars, unsigned driver_loc)
1498 {
1499 nir_foreach_variable(var, vars) {
1500 if (var->data.driver_location == driver_loc)
1501 return var;
1502 }
1503
1504 return NULL;
1505 }
1506
1507 static void
1508 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1509 {
1510 unsigned offset = 0, reg;
1511
1512 switch (instr->intrinsic) {
1513 case nir_intrinsic_discard_if:
1514 case nir_intrinsic_discard: {
1515 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1516 struct midgard_instruction discard = v_branch(conditional, false);
1517 discard.branch.target_type = TARGET_DISCARD;
1518
1519 if (conditional)
1520 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1521
1522 emit_mir_instruction(ctx, discard);
1523 schedule_barrier(ctx);
1524
1525 break;
1526 }
1527
1528 case nir_intrinsic_load_uniform:
1529 case nir_intrinsic_load_ubo:
1530 case nir_intrinsic_load_global:
1531 case nir_intrinsic_load_input:
1532 case nir_intrinsic_load_interpolated_input: {
1533 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1534 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1535 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1536 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1537 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1538
1539 /* Get the base type of the intrinsic */
1540 /* TODO: Infer type? Does it matter? */
1541 nir_alu_type t =
1542 (is_ubo || is_global) ? nir_type_uint :
1543 (is_interp) ? nir_type_float :
1544 nir_intrinsic_type(instr);
1545
1546 t = nir_alu_type_get_base_type(t);
1547
1548 if (!(is_ubo || is_global)) {
1549 offset = nir_intrinsic_base(instr);
1550 }
1551
1552 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1553
1554 nir_src *src_offset = nir_get_io_offset_src(instr);
1555
1556 bool direct = nir_src_is_const(*src_offset);
1557 nir_src *indirect_offset = direct ? NULL : src_offset;
1558
1559 if (direct)
1560 offset += nir_src_as_uint(*src_offset);
1561
1562 /* We may need to apply a fractional offset */
1563 int component = (is_flat || is_interp) ?
1564 nir_intrinsic_component(instr) : 0;
1565 reg = nir_dest_index(ctx, &instr->dest);
1566
1567 if (is_uniform && !ctx->is_blend) {
1568 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysval_count + offset) * 16, indirect_offset, 4, 0);
1569 } else if (is_ubo) {
1570 nir_src index = instr->src[0];
1571
1572 /* TODO: Is indirect block number possible? */
1573 assert(nir_src_is_const(index));
1574
1575 uint32_t uindex = nir_src_as_uint(index) + 1;
1576 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1577 } else if (is_global) {
1578 emit_global(ctx, &instr->instr, true, reg, indirect_offset);
1579 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1580 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1581 } else if (ctx->is_blend) {
1582 /* For blend shaders, load the input color, which is
1583 * preloaded to r0 */
1584
1585 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1586 emit_mir_instruction(ctx, move);
1587 schedule_barrier(ctx);
1588 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1589 emit_attr_read(ctx, reg, offset, nr_comp, t);
1590 } else {
1591 DBG("Unknown load\n");
1592 assert(0);
1593 }
1594
1595 break;
1596 }
1597
1598 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1599 case nir_intrinsic_load_barycentric_pixel:
1600 case nir_intrinsic_load_barycentric_centroid:
1601 break;
1602
1603 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1604
1605 case nir_intrinsic_load_raw_output_pan:
1606 case nir_intrinsic_load_output_u8_as_fp16_pan:
1607 reg = nir_dest_index(ctx, &instr->dest);
1608 assert(ctx->is_blend);
1609
1610 /* T720 and below use different blend opcodes with slightly
1611 * different semantics than T760 and up */
1612
1613 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1614 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1615
1616 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1617 ld.load_store.op = old_blend ?
1618 midgard_op_ld_color_buffer_u8_as_fp16_old :
1619 midgard_op_ld_color_buffer_u8_as_fp16;
1620
1621 if (old_blend) {
1622 ld.load_store.address = 1;
1623 ld.load_store.arg_2 = 0x1E;
1624 }
1625
1626 for (unsigned c = 2; c < 16; ++c)
1627 ld.swizzle[0][c] = 0;
1628 }
1629
1630 emit_mir_instruction(ctx, ld);
1631 break;
1632
1633 case nir_intrinsic_load_blend_const_color_rgba: {
1634 assert(ctx->is_blend);
1635 reg = nir_dest_index(ctx, &instr->dest);
1636
1637 /* Blend constants are embedded directly in the shader and
1638 * patched in, so we use some magic routing */
1639
1640 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1641 ins.has_constants = true;
1642 ins.has_blend_constant = true;
1643 emit_mir_instruction(ctx, ins);
1644 break;
1645 }
1646
1647 case nir_intrinsic_store_zs_output_pan: {
1648 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1649 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1650 MIDGARD_ZS_RT);
1651
1652 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1653
1654 if (!nir_intrinsic_component(instr))
1655 br->writeout_depth = true;
1656 if (nir_intrinsic_component(instr) ||
1657 instr->num_components)
1658 br->writeout_stencil = true;
1659 assert(br->writeout_depth | br->writeout_stencil);
1660 break;
1661 }
1662
1663 case nir_intrinsic_store_output:
1664 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1665
1666 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1667
1668 reg = nir_src_index(ctx, &instr->src[0]);
1669
1670 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1671 const nir_variable *var;
1672 enum midgard_rt_id rt;
1673
1674 var = search_var(&ctx->nir->outputs,
1675 nir_intrinsic_base(instr));
1676 assert(var);
1677 if (var->data.location == FRAG_RESULT_COLOR)
1678 rt = MIDGARD_COLOR_RT0;
1679 else if (var->data.location >= FRAG_RESULT_DATA0)
1680 rt = MIDGARD_COLOR_RT0 + var->data.location -
1681 FRAG_RESULT_DATA0;
1682 else
1683 assert(0);
1684
1685 emit_fragment_store(ctx, reg, rt);
1686 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1687 /* We should have been vectorized, though we don't
1688 * currently check that st_vary is emitted only once
1689 * per slot (this is relevant, since there's not a mask
1690 * parameter available on the store [set to 0 by the
1691 * blob]). We do respect the component by adjusting the
1692 * swizzle. If this is a constant source, we'll need to
1693 * emit that explicitly. */
1694
1695 emit_explicit_constant(ctx, reg, reg);
1696
1697 unsigned dst_component = nir_intrinsic_component(instr);
1698 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1699
1700 midgard_instruction st = m_st_vary_32(reg, offset);
1701 st.load_store.arg_1 = 0x9E;
1702 st.load_store.arg_2 = 0x1E;
1703
1704 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1705 case nir_type_uint:
1706 case nir_type_bool:
1707 st.load_store.op = midgard_op_st_vary_32u;
1708 break;
1709 case nir_type_int:
1710 st.load_store.op = midgard_op_st_vary_32i;
1711 break;
1712 case nir_type_float:
1713 st.load_store.op = midgard_op_st_vary_32;
1714 break;
1715 default:
1716 unreachable("Attempted to store unknown type");
1717 break;
1718 }
1719
1720 /* nir_intrinsic_component(store_intr) encodes the
1721 * destination component start. Source component offset
1722 * adjustment is taken care of in
1723 * install_registers_instr(), when offset_swizzle() is
1724 * called.
1725 */
1726 unsigned src_component = COMPONENT_X;
1727
1728 assert(nr_comp > 0);
1729 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1730 st.swizzle[0][i] = src_component;
1731 if (i >= dst_component && i < dst_component + nr_comp - 1)
1732 src_component++;
1733 }
1734
1735 emit_mir_instruction(ctx, st);
1736 } else {
1737 DBG("Unknown store\n");
1738 assert(0);
1739 }
1740
1741 break;
1742
1743 /* Special case of store_output for lowered blend shaders */
1744 case nir_intrinsic_store_raw_output_pan:
1745 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1746 reg = nir_src_index(ctx, &instr->src[0]);
1747
1748 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1749 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1750 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1751 * of:
1752 *
1753 * imov r0.xyzw, r0.xxxx
1754 */
1755
1756 unsigned expanded = make_compiler_temp(ctx);
1757
1758 midgard_instruction splatter = v_mov(reg, expanded);
1759
1760 for (unsigned c = 0; c < 16; ++c)
1761 splatter.swizzle[1][c] = 0;
1762
1763 emit_mir_instruction(ctx, splatter);
1764 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1765 } else
1766 emit_fragment_store(ctx, reg, ctx->blend_rt);
1767
1768 break;
1769
1770 case nir_intrinsic_store_global:
1771 reg = nir_src_index(ctx, &instr->src[0]);
1772 emit_explicit_constant(ctx, reg, reg);
1773 emit_global(ctx, &instr->instr, false, reg, &instr->src[1]);
1774 break;
1775
1776 case nir_intrinsic_load_ssbo_address:
1777 emit_sysval_read(ctx, &instr->instr, ~0, 1);
1778 break;
1779
1780 case nir_intrinsic_load_viewport_scale:
1781 case nir_intrinsic_load_viewport_offset:
1782 case nir_intrinsic_load_num_work_groups:
1783 case nir_intrinsic_load_sampler_lod_parameters_pan:
1784 emit_sysval_read(ctx, &instr->instr, ~0, 3);
1785 break;
1786
1787 case nir_intrinsic_load_work_group_id:
1788 case nir_intrinsic_load_local_invocation_id:
1789 emit_compute_builtin(ctx, instr);
1790 break;
1791
1792 case nir_intrinsic_load_vertex_id:
1793 case nir_intrinsic_load_instance_id:
1794 emit_vertex_builtin(ctx, instr);
1795 break;
1796
1797 case nir_intrinsic_memory_barrier_buffer:
1798 case nir_intrinsic_memory_barrier_shared:
1799 break;
1800
1801 case nir_intrinsic_control_barrier:
1802 schedule_barrier(ctx);
1803 emit_control_barrier(ctx);
1804 schedule_barrier(ctx);
1805 break;
1806
1807 default:
1808 printf ("Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1809 assert(0);
1810 break;
1811 }
1812 }
1813
1814 static unsigned
1815 midgard_tex_format(enum glsl_sampler_dim dim)
1816 {
1817 switch (dim) {
1818 case GLSL_SAMPLER_DIM_1D:
1819 case GLSL_SAMPLER_DIM_BUF:
1820 return MALI_TEX_1D;
1821
1822 case GLSL_SAMPLER_DIM_2D:
1823 case GLSL_SAMPLER_DIM_EXTERNAL:
1824 case GLSL_SAMPLER_DIM_RECT:
1825 return MALI_TEX_2D;
1826
1827 case GLSL_SAMPLER_DIM_3D:
1828 return MALI_TEX_3D;
1829
1830 case GLSL_SAMPLER_DIM_CUBE:
1831 return MALI_TEX_CUBE;
1832
1833 default:
1834 DBG("Unknown sampler dim type\n");
1835 assert(0);
1836 return 0;
1837 }
1838 }
1839
1840 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1841 * was successful */
1842
1843 static bool
1844 pan_attach_constant_bias(
1845 compiler_context *ctx,
1846 nir_src lod,
1847 midgard_texture_word *word)
1848 {
1849 /* To attach as constant, it has to *be* constant */
1850
1851 if (!nir_src_is_const(lod))
1852 return false;
1853
1854 float f = nir_src_as_float(lod);
1855
1856 /* Break into fixed-point */
1857 signed lod_int = f;
1858 float lod_frac = f - lod_int;
1859
1860 /* Carry over negative fractions */
1861 if (lod_frac < 0.0) {
1862 lod_int--;
1863 lod_frac += 1.0;
1864 }
1865
1866 /* Encode */
1867 word->bias = float_to_ubyte(lod_frac);
1868 word->bias_int = lod_int;
1869
1870 return true;
1871 }
1872
1873 static enum mali_sampler_type
1874 midgard_sampler_type(nir_alu_type t) {
1875 switch (nir_alu_type_get_base_type(t))
1876 {
1877 case nir_type_float:
1878 return MALI_SAMPLER_FLOAT;
1879 case nir_type_int:
1880 return MALI_SAMPLER_SIGNED;
1881 case nir_type_uint:
1882 return MALI_SAMPLER_UNSIGNED;
1883 default:
1884 unreachable("Unknown sampler type");
1885 }
1886 }
1887
1888 static void
1889 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1890 unsigned midgard_texop)
1891 {
1892 /* TODO */
1893 //assert (!instr->sampler);
1894 //assert (!instr->texture_array_size);
1895
1896 int texture_index = instr->texture_index;
1897 int sampler_index = texture_index;
1898
1899 /* No helper to build texture words -- we do it all here */
1900 midgard_instruction ins = {
1901 .type = TAG_TEXTURE_4,
1902 .mask = 0xF,
1903 .dest = nir_dest_index(ctx, &instr->dest),
1904 .src = { ~0, ~0, ~0, ~0 },
1905 .swizzle = SWIZZLE_IDENTITY_4,
1906 .texture = {
1907 .op = midgard_texop,
1908 .format = midgard_tex_format(instr->sampler_dim),
1909 .texture_handle = texture_index,
1910 .sampler_handle = sampler_index,
1911
1912 /* TODO: half */
1913 .in_reg_full = 1,
1914 .out_full = 1,
1915
1916 .sampler_type = midgard_sampler_type(instr->dest_type),
1917 .shadow = instr->is_shadow,
1918 }
1919 };
1920
1921 /* We may need a temporary for the coordinate */
1922
1923 bool needs_temp_coord =
1924 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1925 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1926 (instr->is_shadow);
1927
1928 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1929
1930 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1931 int index = nir_src_index(ctx, &instr->src[i].src);
1932 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1933
1934 switch (instr->src[i].src_type) {
1935 case nir_tex_src_coord: {
1936 emit_explicit_constant(ctx, index, index);
1937
1938 unsigned coord_mask = mask_of(instr->coord_components);
1939
1940 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1941
1942 if (flip_zw)
1943 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1944
1945 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1946 /* texelFetch is undefined on samplerCube */
1947 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1948
1949 /* For cubemaps, we use a special ld/st op to
1950 * select the face and copy the xy into the
1951 * texture register */
1952
1953 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1954 ld.src[1] = index;
1955 ld.mask = 0x3; /* xy */
1956 ld.load_store.arg_1 = 0x20;
1957 ld.swizzle[1][3] = COMPONENT_X;
1958 emit_mir_instruction(ctx, ld);
1959
1960 /* xyzw -> xyxx */
1961 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1962 ins.swizzle[1][3] = COMPONENT_X;
1963 } else if (needs_temp_coord) {
1964 /* mov coord_temp, coords */
1965 midgard_instruction mov = v_mov(index, coords);
1966 mov.mask = coord_mask;
1967
1968 if (flip_zw)
1969 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1970
1971 emit_mir_instruction(ctx, mov);
1972 } else {
1973 coords = index;
1974 }
1975
1976 ins.src[1] = coords;
1977
1978 /* Texelfetch coordinates uses all four elements
1979 * (xyz/index) regardless of texture dimensionality,
1980 * which means it's necessary to zero the unused
1981 * components to keep everything happy */
1982
1983 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1984 /* mov index.zw, #0, or generalized */
1985 midgard_instruction mov =
1986 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1987 mov.has_constants = true;
1988 mov.mask = coord_mask ^ 0xF;
1989 emit_mir_instruction(ctx, mov);
1990 }
1991
1992 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1993 /* Array component in w but NIR wants it in z,
1994 * but if we have a temp coord we already fixed
1995 * that up */
1996
1997 if (nr_components == 3) {
1998 ins.swizzle[1][2] = COMPONENT_Z;
1999 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
2000 } else if (nr_components == 2) {
2001 ins.swizzle[1][2] =
2002 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
2003 ins.swizzle[1][3] = COMPONENT_X;
2004 } else
2005 unreachable("Invalid texture 2D components");
2006 }
2007
2008 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2009 /* We zeroed */
2010 ins.swizzle[1][2] = COMPONENT_Z;
2011 ins.swizzle[1][3] = COMPONENT_W;
2012 }
2013
2014 break;
2015 }
2016
2017 case nir_tex_src_bias:
2018 case nir_tex_src_lod: {
2019 /* Try as a constant if we can */
2020
2021 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2022 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2023 break;
2024
2025 ins.texture.lod_register = true;
2026 ins.src[2] = index;
2027
2028 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2029 ins.swizzle[2][c] = COMPONENT_X;
2030
2031 emit_explicit_constant(ctx, index, index);
2032
2033 break;
2034 };
2035
2036 case nir_tex_src_offset: {
2037 ins.texture.offset_register = true;
2038 ins.src[3] = index;
2039
2040 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2041 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2042
2043 emit_explicit_constant(ctx, index, index);
2044 break;
2045 };
2046
2047 case nir_tex_src_comparator: {
2048 unsigned comp = COMPONENT_Z;
2049
2050 /* mov coord_temp.foo, coords */
2051 midgard_instruction mov = v_mov(index, coords);
2052 mov.mask = 1 << comp;
2053
2054 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2055 mov.swizzle[1][i] = COMPONENT_X;
2056
2057 emit_mir_instruction(ctx, mov);
2058 break;
2059 }
2060
2061 default: {
2062 printf ("Unknown texture source type: %d\n", instr->src[i].src_type);
2063 assert(0);
2064 }
2065 }
2066 }
2067
2068 emit_mir_instruction(ctx, ins);
2069
2070 /* Used for .cont and .last hinting */
2071 ctx->texture_op_count++;
2072 }
2073
2074 static void
2075 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2076 {
2077 switch (instr->op) {
2078 case nir_texop_tex:
2079 case nir_texop_txb:
2080 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2081 break;
2082 case nir_texop_txl:
2083 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2084 break;
2085 case nir_texop_txf:
2086 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2087 break;
2088 case nir_texop_txs:
2089 emit_sysval_read(ctx, &instr->instr, ~0, 4);
2090 break;
2091 default: {
2092 printf ("Unhandled texture op: %d\n", instr->op);
2093 assert(0);
2094 }
2095 }
2096 }
2097
2098 static void
2099 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2100 {
2101 switch (instr->type) {
2102 case nir_jump_break: {
2103 /* Emit a branch out of the loop */
2104 struct midgard_instruction br = v_branch(false, false);
2105 br.branch.target_type = TARGET_BREAK;
2106 br.branch.target_break = ctx->current_loop_depth;
2107 emit_mir_instruction(ctx, br);
2108 break;
2109 }
2110
2111 default:
2112 DBG("Unknown jump type %d\n", instr->type);
2113 break;
2114 }
2115 }
2116
2117 static void
2118 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2119 {
2120 switch (instr->type) {
2121 case nir_instr_type_load_const:
2122 emit_load_const(ctx, nir_instr_as_load_const(instr));
2123 break;
2124
2125 case nir_instr_type_intrinsic:
2126 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2127 break;
2128
2129 case nir_instr_type_alu:
2130 emit_alu(ctx, nir_instr_as_alu(instr));
2131 break;
2132
2133 case nir_instr_type_tex:
2134 emit_tex(ctx, nir_instr_as_tex(instr));
2135 break;
2136
2137 case nir_instr_type_jump:
2138 emit_jump(ctx, nir_instr_as_jump(instr));
2139 break;
2140
2141 case nir_instr_type_ssa_undef:
2142 /* Spurious */
2143 break;
2144
2145 default:
2146 DBG("Unhandled instruction type\n");
2147 break;
2148 }
2149 }
2150
2151
2152 /* ALU instructions can inline or embed constants, which decreases register
2153 * pressure and saves space. */
2154
2155 #define CONDITIONAL_ATTACH(idx) { \
2156 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2157 \
2158 if (entry) { \
2159 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2160 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2161 } \
2162 }
2163
2164 static void
2165 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2166 {
2167 mir_foreach_instr_in_block(block, alu) {
2168 /* Other instructions cannot inline constants */
2169 if (alu->type != TAG_ALU_4) continue;
2170 if (alu->compact_branch) continue;
2171
2172 /* If there is already a constant here, we can do nothing */
2173 if (alu->has_constants) continue;
2174
2175 CONDITIONAL_ATTACH(0);
2176
2177 if (!alu->has_constants) {
2178 CONDITIONAL_ATTACH(1)
2179 } else if (!alu->inline_constant) {
2180 /* Corner case: _two_ vec4 constants, for instance with a
2181 * csel. For this case, we can only use a constant
2182 * register for one, we'll have to emit a move for the
2183 * other. Note, if both arguments are constants, then
2184 * necessarily neither argument depends on the value of
2185 * any particular register. As the destination register
2186 * will be wiped, that means we can spill the constant
2187 * to the destination register.
2188 */
2189
2190 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2191 unsigned scratch = alu->dest;
2192
2193 if (entry) {
2194 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2195 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2196
2197 /* Set the source */
2198 alu->src[1] = scratch;
2199
2200 /* Inject us -before- the last instruction which set r31 */
2201 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2202 }
2203 }
2204 }
2205 }
2206
2207 /* Being a little silly with the names, but returns the op that is the bitwise
2208 * inverse of the op with the argument switched. I.e. (f and g are
2209 * contrapositives):
2210 *
2211 * f(a, b) = ~g(b, a)
2212 *
2213 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2214 *
2215 * f(a, b) = ~g(b, a)
2216 * ~f(a, b) = g(b, a)
2217 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2218 * f(a, b) = h(a, b)
2219 *
2220 * Thus we define this function in pairs.
2221 */
2222
2223 static inline midgard_alu_op
2224 mir_contrapositive(midgard_alu_op op)
2225 {
2226 switch (op) {
2227 case midgard_alu_op_flt:
2228 return midgard_alu_op_fle;
2229 case midgard_alu_op_fle:
2230 return midgard_alu_op_flt;
2231
2232 case midgard_alu_op_ilt:
2233 return midgard_alu_op_ile;
2234 case midgard_alu_op_ile:
2235 return midgard_alu_op_ilt;
2236
2237 default:
2238 unreachable("No known contrapositive");
2239 }
2240 }
2241
2242 /* Midgard supports two types of constants, embedded constants (128-bit) and
2243 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2244 * constants can be demoted to inline constants, for space savings and
2245 * sometimes a performance boost */
2246
2247 static void
2248 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2249 {
2250 mir_foreach_instr_in_block(block, ins) {
2251 if (!ins->has_constants) continue;
2252 if (ins->has_inline_constant) continue;
2253
2254 /* Blend constants must not be inlined by definition */
2255 if (ins->has_blend_constant) continue;
2256
2257 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2258 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2259 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2260
2261 if (!(is_16 || is_32))
2262 continue;
2263
2264 /* src1 cannot be an inline constant due to encoding
2265 * restrictions. So, if possible we try to flip the arguments
2266 * in that case */
2267
2268 int op = ins->alu.op;
2269
2270 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2271 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2272
2273 switch (op) {
2274 /* Conditionals can be inverted */
2275 case midgard_alu_op_flt:
2276 case midgard_alu_op_ilt:
2277 case midgard_alu_op_fle:
2278 case midgard_alu_op_ile:
2279 ins->alu.op = mir_contrapositive(ins->alu.op);
2280 ins->invert = true;
2281 flip = true;
2282 break;
2283
2284 case midgard_alu_op_fcsel:
2285 case midgard_alu_op_icsel:
2286 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2287 default:
2288 break;
2289 }
2290
2291 if (flip)
2292 mir_flip(ins);
2293 }
2294
2295 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2296 /* Extract the source information */
2297
2298 midgard_vector_alu_src *src;
2299 int q = ins->alu.src2;
2300 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2301 src = m;
2302
2303 /* Component is from the swizzle. Take a nonzero component */
2304 assert(ins->mask);
2305 unsigned first_comp = ffs(ins->mask) - 1;
2306 unsigned component = ins->swizzle[1][first_comp];
2307
2308 /* Scale constant appropriately, if we can legally */
2309 uint16_t scaled_constant = 0;
2310
2311 if (is_16) {
2312 scaled_constant = ins->constants.u16[component];
2313 } else if (midgard_is_integer_op(op)) {
2314 scaled_constant = ins->constants.u32[component];
2315
2316 /* Constant overflow after resize */
2317 if (scaled_constant != ins->constants.u32[component])
2318 continue;
2319 } else {
2320 float original = ins->constants.f32[component];
2321 scaled_constant = _mesa_float_to_half(original);
2322
2323 /* Check for loss of precision. If this is
2324 * mediump, we don't care, but for a highp
2325 * shader, we need to pay attention. NIR
2326 * doesn't yet tell us which mode we're in!
2327 * Practically this prevents most constants
2328 * from being inlined, sadly. */
2329
2330 float fp32 = _mesa_half_to_float(scaled_constant);
2331
2332 if (fp32 != original)
2333 continue;
2334 }
2335
2336 /* We don't know how to handle these with a constant */
2337
2338 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2339 DBG("Bailing inline constant...\n");
2340 continue;
2341 }
2342
2343 /* Make sure that the constant is not itself a vector
2344 * by checking if all accessed values are the same. */
2345
2346 const midgard_constants *cons = &ins->constants;
2347 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2348
2349 bool is_vector = false;
2350 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2351
2352 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2353 /* We only care if this component is actually used */
2354 if (!(mask & (1 << c)))
2355 continue;
2356
2357 uint32_t test = is_16 ?
2358 cons->u16[ins->swizzle[1][c]] :
2359 cons->u32[ins->swizzle[1][c]];
2360
2361 if (test != value) {
2362 is_vector = true;
2363 break;
2364 }
2365 }
2366
2367 if (is_vector)
2368 continue;
2369
2370 /* Get rid of the embedded constant */
2371 ins->has_constants = false;
2372 ins->src[1] = ~0;
2373 ins->has_inline_constant = true;
2374 ins->inline_constant = scaled_constant;
2375 }
2376 }
2377 }
2378
2379 /* Dead code elimination for branches at the end of a block - only one branch
2380 * per block is legal semantically */
2381
2382 static void
2383 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2384 {
2385 bool branched = false;
2386
2387 mir_foreach_instr_in_block_safe(block, ins) {
2388 if (!midgard_is_branch_unit(ins->unit)) continue;
2389
2390 if (branched)
2391 mir_remove_instruction(ins);
2392
2393 branched = true;
2394 }
2395 }
2396
2397 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2398 * the move can be propagated away entirely */
2399
2400 static bool
2401 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2402 {
2403 /* Nothing to do */
2404 if (comp == midgard_outmod_none)
2405 return true;
2406
2407 if (*outmod == midgard_outmod_none) {
2408 *outmod = comp;
2409 return true;
2410 }
2411
2412 /* TODO: Compose rules */
2413 return false;
2414 }
2415
2416 static bool
2417 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2418 {
2419 bool progress = false;
2420
2421 mir_foreach_instr_in_block_safe(block, ins) {
2422 if (ins->type != TAG_ALU_4) continue;
2423 if (ins->alu.op != midgard_alu_op_fmov) continue;
2424 if (ins->alu.outmod != midgard_outmod_pos) continue;
2425
2426 /* TODO: Registers? */
2427 unsigned src = ins->src[1];
2428 if (src & IS_REG) continue;
2429
2430 /* There might be a source modifier, too */
2431 if (mir_nontrivial_source2_mod(ins)) continue;
2432
2433 /* Backpropagate the modifier */
2434 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2435 if (v->type != TAG_ALU_4) continue;
2436 if (v->dest != src) continue;
2437
2438 /* Can we even take a float outmod? */
2439 if (midgard_is_integer_out_op(v->alu.op)) continue;
2440
2441 midgard_outmod_float temp = v->alu.outmod;
2442 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2443
2444 /* Throw in the towel.. */
2445 if (!progress) break;
2446
2447 /* Otherwise, transfer the modifier */
2448 v->alu.outmod = temp;
2449 ins->alu.outmod = midgard_outmod_none;
2450
2451 break;
2452 }
2453 }
2454
2455 return progress;
2456 }
2457
2458 static unsigned
2459 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2460 {
2461 /* Loop to ourselves */
2462 midgard_instruction *br = ctx->writeout_branch[rt];
2463 struct midgard_instruction ins = v_branch(false, false);
2464 ins.writeout = true;
2465 ins.writeout_depth = br->writeout_depth;
2466 ins.writeout_stencil = br->writeout_stencil;
2467 ins.branch.target_block = ctx->block_count - 1;
2468 ins.constants.u32[0] = br->constants.u32[0];
2469 emit_mir_instruction(ctx, ins);
2470
2471 ctx->current_block->epilogue = true;
2472 schedule_barrier(ctx);
2473 return ins.branch.target_block;
2474 }
2475
2476 static midgard_block *
2477 emit_block(compiler_context *ctx, nir_block *block)
2478 {
2479 midgard_block *this_block = ctx->after_block;
2480 ctx->after_block = NULL;
2481
2482 if (!this_block)
2483 this_block = create_empty_block(ctx);
2484
2485 list_addtail(&this_block->link, &ctx->blocks);
2486
2487 this_block->is_scheduled = false;
2488 ++ctx->block_count;
2489
2490 /* Set up current block */
2491 list_inithead(&this_block->instructions);
2492 ctx->current_block = this_block;
2493
2494 nir_foreach_instr(instr, block) {
2495 emit_instr(ctx, instr);
2496 ++ctx->instruction_count;
2497 }
2498
2499 return this_block;
2500 }
2501
2502 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2503
2504 static void
2505 emit_if(struct compiler_context *ctx, nir_if *nif)
2506 {
2507 midgard_block *before_block = ctx->current_block;
2508
2509 /* Speculatively emit the branch, but we can't fill it in until later */
2510 EMIT(branch, true, true);
2511 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2512 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2513
2514 /* Emit the two subblocks. */
2515 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2516 midgard_block *end_then_block = ctx->current_block;
2517
2518 /* Emit a jump from the end of the then block to the end of the else */
2519 EMIT(branch, false, false);
2520 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2521
2522 /* Emit second block, and check if it's empty */
2523
2524 int else_idx = ctx->block_count;
2525 int count_in = ctx->instruction_count;
2526 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2527 midgard_block *end_else_block = ctx->current_block;
2528 int after_else_idx = ctx->block_count;
2529
2530 /* Now that we have the subblocks emitted, fix up the branches */
2531
2532 assert(then_block);
2533 assert(else_block);
2534
2535 if (ctx->instruction_count == count_in) {
2536 /* The else block is empty, so don't emit an exit jump */
2537 mir_remove_instruction(then_exit);
2538 then_branch->branch.target_block = after_else_idx;
2539 } else {
2540 then_branch->branch.target_block = else_idx;
2541 then_exit->branch.target_block = after_else_idx;
2542 }
2543
2544 /* Wire up the successors */
2545
2546 ctx->after_block = create_empty_block(ctx);
2547
2548 midgard_block_add_successor(before_block, then_block);
2549 midgard_block_add_successor(before_block, else_block);
2550
2551 midgard_block_add_successor(end_then_block, ctx->after_block);
2552 midgard_block_add_successor(end_else_block, ctx->after_block);
2553 }
2554
2555 static void
2556 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2557 {
2558 /* Remember where we are */
2559 midgard_block *start_block = ctx->current_block;
2560
2561 /* Allocate a loop number, growing the current inner loop depth */
2562 int loop_idx = ++ctx->current_loop_depth;
2563
2564 /* Get index from before the body so we can loop back later */
2565 int start_idx = ctx->block_count;
2566
2567 /* Emit the body itself */
2568 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2569
2570 /* Branch back to loop back */
2571 struct midgard_instruction br_back = v_branch(false, false);
2572 br_back.branch.target_block = start_idx;
2573 emit_mir_instruction(ctx, br_back);
2574
2575 /* Mark down that branch in the graph. */
2576 midgard_block_add_successor(start_block, loop_block);
2577 midgard_block_add_successor(ctx->current_block, loop_block);
2578
2579 /* Find the index of the block about to follow us (note: we don't add
2580 * one; blocks are 0-indexed so we get a fencepost problem) */
2581 int break_block_idx = ctx->block_count;
2582
2583 /* Fix up the break statements we emitted to point to the right place,
2584 * now that we can allocate a block number for them */
2585 ctx->after_block = create_empty_block(ctx);
2586
2587 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2588 mir_foreach_instr_in_block(block, ins) {
2589 if (ins->type != TAG_ALU_4) continue;
2590 if (!ins->compact_branch) continue;
2591
2592 /* We found a branch -- check the type to see if we need to do anything */
2593 if (ins->branch.target_type != TARGET_BREAK) continue;
2594
2595 /* It's a break! Check if it's our break */
2596 if (ins->branch.target_break != loop_idx) continue;
2597
2598 /* Okay, cool, we're breaking out of this loop.
2599 * Rewrite from a break to a goto */
2600
2601 ins->branch.target_type = TARGET_GOTO;
2602 ins->branch.target_block = break_block_idx;
2603
2604 midgard_block_add_successor(block, ctx->after_block);
2605 }
2606 }
2607
2608 /* Now that we've finished emitting the loop, free up the depth again
2609 * so we play nice with recursion amid nested loops */
2610 --ctx->current_loop_depth;
2611
2612 /* Dump loop stats */
2613 ++ctx->loop_count;
2614 }
2615
2616 static midgard_block *
2617 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2618 {
2619 midgard_block *start_block = NULL;
2620
2621 foreach_list_typed(nir_cf_node, node, node, list) {
2622 switch (node->type) {
2623 case nir_cf_node_block: {
2624 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2625
2626 if (!start_block)
2627 start_block = block;
2628
2629 break;
2630 }
2631
2632 case nir_cf_node_if:
2633 emit_if(ctx, nir_cf_node_as_if(node));
2634 break;
2635
2636 case nir_cf_node_loop:
2637 emit_loop(ctx, nir_cf_node_as_loop(node));
2638 break;
2639
2640 case nir_cf_node_function:
2641 assert(0);
2642 break;
2643 }
2644 }
2645
2646 return start_block;
2647 }
2648
2649 /* Due to lookahead, we need to report the first tag executed in the command
2650 * stream and in branch targets. An initial block might be empty, so iterate
2651 * until we find one that 'works' */
2652
2653 static unsigned
2654 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2655 {
2656 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2657
2658 mir_foreach_block_from(ctx, initial_block, v) {
2659 if (v->quadword_count) {
2660 midgard_bundle *initial_bundle =
2661 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2662
2663 return initial_bundle->tag;
2664 }
2665 }
2666
2667 /* Default to a tag 1 which will break from the shader, in case we jump
2668 * to the exit block (i.e. `return` in a compute shader) */
2669
2670 return 1;
2671 }
2672
2673 static unsigned
2674 pan_format_from_nir_base(nir_alu_type base)
2675 {
2676 switch (base) {
2677 case nir_type_int:
2678 return MALI_FORMAT_SINT;
2679 case nir_type_uint:
2680 case nir_type_bool:
2681 return MALI_FORMAT_UINT;
2682 case nir_type_float:
2683 return MALI_CHANNEL_FLOAT;
2684 default:
2685 unreachable("Invalid base");
2686 }
2687 }
2688
2689 static unsigned
2690 pan_format_from_nir_size(nir_alu_type base, unsigned size)
2691 {
2692 if (base == nir_type_float) {
2693 switch (size) {
2694 case 16: return MALI_FORMAT_SINT;
2695 case 32: return MALI_FORMAT_UNORM;
2696 default:
2697 unreachable("Invalid float size for format");
2698 }
2699 } else {
2700 switch (size) {
2701 case 1:
2702 case 8: return MALI_CHANNEL_8;
2703 case 16: return MALI_CHANNEL_16;
2704 case 32: return MALI_CHANNEL_32;
2705 default:
2706 unreachable("Invalid int size for format");
2707 }
2708 }
2709 }
2710
2711 static enum mali_format
2712 pan_format_from_glsl(const struct glsl_type *type)
2713 {
2714 enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type));
2715 nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
2716
2717 unsigned base = nir_alu_type_get_base_type(t);
2718 unsigned size = nir_alu_type_get_type_size(t);
2719
2720 return pan_format_from_nir_base(base) |
2721 pan_format_from_nir_size(base, size) |
2722 MALI_NR_CHANNELS(4);
2723 }
2724
2725 /* For each fragment writeout instruction, generate a writeout loop to
2726 * associate with it */
2727
2728 static void
2729 mir_add_writeout_loops(compiler_context *ctx)
2730 {
2731 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2732 midgard_instruction *br = ctx->writeout_branch[rt];
2733 if (!br) continue;
2734
2735 unsigned popped = br->branch.target_block;
2736 midgard_block_add_successor(mir_get_block(ctx, popped - 1), ctx->current_block);
2737 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2738
2739 /* If we have more RTs, we'll need to restore back after our
2740 * loop terminates */
2741
2742 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2743 midgard_instruction uncond = v_branch(false, false);
2744 uncond.branch.target_block = popped;
2745 emit_mir_instruction(ctx, uncond);
2746 midgard_block_add_successor(ctx->current_block, mir_get_block(ctx, popped));
2747 schedule_barrier(ctx);
2748 } else {
2749 /* We're last, so we can terminate here */
2750 br->last_writeout = true;
2751 }
2752 }
2753 }
2754
2755 int
2756 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2757 {
2758 struct util_dynarray *compiled = &program->compiled;
2759
2760 midgard_debug = debug_get_option_midgard_debug();
2761
2762 /* TODO: Bound against what? */
2763 compiler_context *ctx = rzalloc(NULL, compiler_context);
2764
2765 ctx->nir = nir;
2766 ctx->stage = nir->info.stage;
2767 ctx->is_blend = is_blend;
2768 ctx->alpha_ref = program->alpha_ref;
2769 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2770 ctx->quirks = midgard_get_quirks(gpu_id);
2771
2772 /* Start off with a safe cutoff, allowing usage of all 16 work
2773 * registers. Later, we'll promote uniform reads to uniform registers
2774 * if we determine it is beneficial to do so */
2775 ctx->uniform_cutoff = 8;
2776
2777 /* Initialize at a global (not block) level hash tables */
2778
2779 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2780 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2781 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2782
2783 /* Record the varying mapping for the command stream's bookkeeping */
2784
2785 struct exec_list *varyings =
2786 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2787
2788 unsigned max_varying = 0;
2789 nir_foreach_variable(var, varyings) {
2790 unsigned loc = var->data.driver_location;
2791 unsigned sz = glsl_type_size(var->type, FALSE);
2792
2793 for (int c = 0; c < sz; ++c) {
2794 program->varyings[loc + c] = var->data.location + c;
2795 program->varying_type[loc + c] = pan_format_from_glsl(var->type);
2796 max_varying = MAX2(max_varying, loc + c);
2797 }
2798 }
2799
2800 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2801 * (so we don't accidentally duplicate the epilogue since mesa/st has
2802 * messed with our I/O quite a bit already) */
2803
2804 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2805
2806 if (ctx->stage == MESA_SHADER_VERTEX) {
2807 NIR_PASS_V(nir, nir_lower_viewport_transform);
2808 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2809 }
2810
2811 NIR_PASS_V(nir, nir_lower_var_copies);
2812 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2813 NIR_PASS_V(nir, nir_split_var_copies);
2814 NIR_PASS_V(nir, nir_lower_var_copies);
2815 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2816 NIR_PASS_V(nir, nir_lower_var_copies);
2817 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2818
2819 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2820 NIR_PASS_V(nir, nir_lower_ssbo);
2821 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2822
2823 /* Optimisation passes */
2824
2825 optimise_nir(nir, ctx->quirks);
2826
2827 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2828 nir_print_shader(nir, stdout);
2829 }
2830
2831 /* Assign sysvals and counts, now that we're sure
2832 * (post-optimisation) */
2833
2834 midgard_nir_assign_sysvals(ctx, nir);
2835
2836 program->uniform_count = nir->num_uniforms;
2837 program->sysval_count = ctx->sysval_count;
2838 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2839
2840 nir_foreach_function(func, nir) {
2841 if (!func->impl)
2842 continue;
2843
2844 list_inithead(&ctx->blocks);
2845 ctx->block_count = 0;
2846 ctx->func = func;
2847
2848 emit_cf_list(ctx, &func->impl->body);
2849 break; /* TODO: Multi-function shaders */
2850 }
2851
2852 util_dynarray_init(compiled, NULL);
2853
2854 /* Per-block lowering before opts */
2855
2856 mir_foreach_block(ctx, block) {
2857 inline_alu_constants(ctx, block);
2858 midgard_opt_promote_fmov(ctx, block);
2859 embedded_to_inline_constant(ctx, block);
2860 }
2861 /* MIR-level optimizations */
2862
2863 bool progress = false;
2864
2865 do {
2866 progress = false;
2867
2868 mir_foreach_block(ctx, block) {
2869 progress |= midgard_opt_pos_propagate(ctx, block);
2870 progress |= midgard_opt_copy_prop(ctx, block);
2871 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2872 progress |= midgard_opt_combine_projection(ctx, block);
2873 progress |= midgard_opt_varying_projection(ctx, block);
2874 progress |= midgard_opt_not_propagate(ctx, block);
2875 progress |= midgard_opt_fuse_src_invert(ctx, block);
2876 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2877 progress |= midgard_opt_csel_invert(ctx, block);
2878 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2879 progress |= midgard_opt_invert_branch(ctx, block);
2880 }
2881 } while (progress);
2882
2883 mir_foreach_block(ctx, block) {
2884 midgard_lower_invert(ctx, block);
2885 midgard_lower_derivatives(ctx, block);
2886 }
2887
2888 /* Nested control-flow can result in dead branches at the end of the
2889 * block. This messes with our analysis and is just dead code, so cull
2890 * them */
2891 mir_foreach_block(ctx, block) {
2892 midgard_opt_cull_dead_branch(ctx, block);
2893 }
2894
2895 /* Ensure we were lowered */
2896 mir_foreach_instr_global(ctx, ins) {
2897 assert(!ins->invert);
2898 }
2899
2900 if (ctx->stage == MESA_SHADER_FRAGMENT)
2901 mir_add_writeout_loops(ctx);
2902
2903 /* Schedule! */
2904 midgard_schedule_program(ctx);
2905 mir_ra(ctx);
2906
2907 /* Now that all the bundles are scheduled and we can calculate block
2908 * sizes, emit actual branch instructions rather than placeholders */
2909
2910 int br_block_idx = 0;
2911
2912 mir_foreach_block(ctx, block) {
2913 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2914 for (int c = 0; c < bundle->instruction_count; ++c) {
2915 midgard_instruction *ins = bundle->instructions[c];
2916
2917 if (!midgard_is_branch_unit(ins->unit)) continue;
2918
2919 /* Parse some basic branch info */
2920 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2921 bool is_conditional = ins->branch.conditional;
2922 bool is_inverted = ins->branch.invert_conditional;
2923 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2924 bool is_writeout = ins->writeout;
2925
2926 /* Determine the block we're jumping to */
2927 int target_number = ins->branch.target_block;
2928
2929 /* Report the destination tag */
2930 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2931
2932 /* Count up the number of quadwords we're
2933 * jumping over = number of quadwords until
2934 * (br_block_idx, target_number) */
2935
2936 int quadword_offset = 0;
2937
2938 if (is_discard) {
2939 /* Ignored */
2940 } else if (target_number > br_block_idx) {
2941 /* Jump forward */
2942
2943 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2944 midgard_block *blk = mir_get_block(ctx, idx);
2945 assert(blk);
2946
2947 quadword_offset += blk->quadword_count;
2948 }
2949 } else {
2950 /* Jump backwards */
2951
2952 for (int idx = br_block_idx; idx >= target_number; --idx) {
2953 midgard_block *blk = mir_get_block(ctx, idx);
2954 assert(blk);
2955
2956 quadword_offset -= blk->quadword_count;
2957 }
2958 }
2959
2960 /* Unconditional extended branches (far jumps)
2961 * have issues, so we always use a conditional
2962 * branch, setting the condition to always for
2963 * unconditional. For compact unconditional
2964 * branches, cond isn't used so it doesn't
2965 * matter what we pick. */
2966
2967 midgard_condition cond =
2968 !is_conditional ? midgard_condition_always :
2969 is_inverted ? midgard_condition_false :
2970 midgard_condition_true;
2971
2972 midgard_jmp_writeout_op op =
2973 is_discard ? midgard_jmp_writeout_op_discard :
2974 is_writeout ? midgard_jmp_writeout_op_writeout :
2975 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2976 midgard_jmp_writeout_op_branch_cond;
2977
2978 if (!is_compact) {
2979 midgard_branch_extended branch =
2980 midgard_create_branch_extended(
2981 cond, op,
2982 dest_tag,
2983 quadword_offset);
2984
2985 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2986 } else if (is_conditional || is_discard) {
2987 midgard_branch_cond branch = {
2988 .op = op,
2989 .dest_tag = dest_tag,
2990 .offset = quadword_offset,
2991 .cond = cond
2992 };
2993
2994 assert(branch.offset == quadword_offset);
2995
2996 memcpy(&ins->br_compact, &branch, sizeof(branch));
2997 } else {
2998 assert(op == midgard_jmp_writeout_op_branch_uncond);
2999
3000 midgard_branch_uncond branch = {
3001 .op = op,
3002 .dest_tag = dest_tag,
3003 .offset = quadword_offset,
3004 .unknown = 1
3005 };
3006
3007 assert(branch.offset == quadword_offset);
3008
3009 memcpy(&ins->br_compact, &branch, sizeof(branch));
3010 }
3011 }
3012 }
3013
3014 ++br_block_idx;
3015 }
3016
3017 /* Emit flat binary from the instruction arrays. Iterate each block in
3018 * sequence. Save instruction boundaries such that lookahead tags can
3019 * be assigned easily */
3020
3021 /* Cache _all_ bundles in source order for lookahead across failed branches */
3022
3023 int bundle_count = 0;
3024 mir_foreach_block(ctx, block) {
3025 bundle_count += block->bundles.size / sizeof(midgard_bundle);
3026 }
3027 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
3028 int bundle_idx = 0;
3029 mir_foreach_block(ctx, block) {
3030 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3031 source_order_bundles[bundle_idx++] = bundle;
3032 }
3033 }
3034
3035 int current_bundle = 0;
3036
3037 /* Midgard prefetches instruction types, so during emission we
3038 * need to lookahead. Unless this is the last instruction, in
3039 * which we return 1. */
3040
3041 mir_foreach_block(ctx, block) {
3042 mir_foreach_bundle_in_block(block, bundle) {
3043 int lookahead = 1;
3044
3045 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
3046 lookahead = source_order_bundles[current_bundle + 1]->tag;
3047
3048 emit_binary_bundle(ctx, bundle, compiled, lookahead);
3049 ++current_bundle;
3050 }
3051
3052 /* TODO: Free deeper */
3053 //util_dynarray_fini(&block->instructions);
3054 }
3055
3056 free(source_order_bundles);
3057
3058 /* Report the very first tag executed */
3059 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
3060
3061 /* Deal with off-by-one related to the fencepost problem */
3062 program->work_register_count = ctx->work_registers + 1;
3063 program->uniform_cutoff = ctx->uniform_cutoff;
3064
3065 program->blend_patch_offset = ctx->blend_constant_offset;
3066 program->tls_size = ctx->tls_size;
3067
3068 if (midgard_debug & MIDGARD_DBG_SHADERS)
3069 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
3070
3071 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
3072 unsigned nr_bundles = 0, nr_ins = 0;
3073
3074 /* Count instructions and bundles */
3075
3076 mir_foreach_block(ctx, block) {
3077 nr_bundles += util_dynarray_num_elements(
3078 &block->bundles, midgard_bundle);
3079
3080 mir_foreach_bundle_in_block(block, bun)
3081 nr_ins += bun->instruction_count;
3082 }
3083
3084 /* Calculate thread count. There are certain cutoffs by
3085 * register count for thread count */
3086
3087 unsigned nr_registers = program->work_register_count;
3088
3089 unsigned nr_threads =
3090 (nr_registers <= 4) ? 4 :
3091 (nr_registers <= 8) ? 2 :
3092 1;
3093
3094 /* Dump stats */
3095
3096 fprintf(stderr, "shader%d - %s shader: "
3097 "%u inst, %u bundles, %u quadwords, "
3098 "%u registers, %u threads, %u loops, "
3099 "%u:%u spills:fills\n",
3100 SHADER_DB_COUNT++,
3101 gl_shader_stage_name(ctx->stage),
3102 nr_ins, nr_bundles, ctx->quadword_count,
3103 nr_registers, nr_threads,
3104 ctx->loop_count,
3105 ctx->spills, ctx->fills);
3106 }
3107
3108 ralloc_free(ctx);
3109
3110 return 0;
3111 }