2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block
*
72 create_empty_block(compiler_context
*ctx
)
74 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
76 blk
->base
.predecessors
= _mesa_set_create(blk
,
78 _mesa_key_pointer_equal
);
80 blk
->base
.name
= ctx
->block_source_count
++;
86 schedule_barrier(compiler_context
*ctx
)
88 midgard_block
*temp
= ctx
->after_block
;
89 ctx
->after_block
= create_empty_block(ctx
);
91 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
92 list_inithead(&ctx
->after_block
->base
.instructions
);
93 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
94 ctx
->current_block
= ctx
->after_block
;
95 ctx
->after_block
= temp
;
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
112 .op = midgard_op_##name, \
119 i.src_types[0] = T; \
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
131 M_LOAD(ld_attr_32
, nir_type_uint32
);
132 M_LOAD(ld_vary_32
, nir_type_uint32
);
133 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
134 M_LOAD(ld_int4
, nir_type_uint32
);
135 M_STORE(st_int4
, nir_type_uint32
);
136 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
137 M_STORE(st_vary_32
, nir_type_uint32
);
138 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
139 M_LOAD(ld_compute_id
, nir_type_uint32
);
141 static midgard_instruction
142 v_branch(bool conditional
, bool invert
)
144 midgard_instruction ins
= {
146 .unit
= ALU_ENAB_BRANCH
,
147 .compact_branch
= true,
149 .conditional
= conditional
,
150 .invert_conditional
= invert
153 .src
= { ~0, ~0, ~0, ~0 },
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond
,
161 midgard_jmp_writeout_op op
,
163 signed quadword_offset
)
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
170 uint16_t duplicated_cond
=
180 midgard_branch_extended branch
= {
182 .dest_tag
= dest_tag
,
183 .offset
= quadword_offset
,
184 .cond
= duplicated_cond
191 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
193 ins
->has_constants
= true;
194 memcpy(&ins
->constants
, constants
, 16);
198 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
200 return glsl_count_attribute_slots(type
, false);
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
205 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
207 if (alu
->op
!= nir_op_fdot2
)
210 b
->cursor
= nir_before_instr(&alu
->instr
);
212 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
213 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
215 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
217 nir_ssa_def
*sum
= nir_fadd(b
,
218 nir_channel(b
, product
, 0),
219 nir_channel(b
, product
, 1));
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
226 midgard_nir_lower_fdot2(nir_shader
*shader
)
228 bool progress
= false;
230 nir_foreach_function(function
, shader
) {
231 if (!function
->impl
) continue;
234 nir_builder
*b
= &_b
;
235 nir_builder_init(b
, function
->impl
);
237 nir_foreach_block(block
, function
->impl
) {
238 nir_foreach_instr_safe(instr
, block
) {
239 if (instr
->type
!= nir_instr_type_alu
) continue;
241 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
242 midgard_nir_lower_fdot2_body(b
, alu
);
248 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
261 midgard_nir_lower_zs_store(nir_shader
*nir
)
263 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
266 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
268 nir_foreach_variable(var
, &nir
->outputs
) {
269 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
271 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
275 if (!z_var
&& !s_var
)
278 bool progress
= false;
280 nir_foreach_function(function
, nir
) {
281 if (!function
->impl
) continue;
283 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
, *last_store
= NULL
;
285 nir_foreach_block(block
, function
->impl
) {
286 nir_foreach_instr_safe(instr
, block
) {
287 if (instr
->type
!= nir_instr_type_intrinsic
)
290 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
291 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
294 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
300 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
308 if (!z_store
&& !s_store
) continue;
311 nir_builder_init(&b
, function
->impl
);
313 b
.cursor
= nir_before_instr(&last_store
->instr
);
315 nir_ssa_def
*zs_store_src
;
317 if (z_store
&& s_store
) {
318 nir_ssa_def
*srcs
[2] = {
319 nir_ssa_for_src(&b
, z_store
->src
[0], 1),
320 nir_ssa_for_src(&b
, s_store
->src
[0], 1),
323 zs_store_src
= nir_vec(&b
, srcs
, 2);
325 zs_store_src
= nir_ssa_for_src(&b
, last_store
->src
[0], 1);
328 nir_intrinsic_instr
*zs_store
;
330 zs_store
= nir_intrinsic_instr_create(b
.shader
,
331 nir_intrinsic_store_zs_output_pan
);
332 zs_store
->src
[0] = nir_src_for_ssa(zs_store_src
);
333 zs_store
->num_components
= z_store
&& s_store
? 2 : 1;
334 nir_intrinsic_set_component(zs_store
, z_store
? 0 : 1);
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b
, &zs_store
->instr
);
340 nir_instr_remove(&z_store
->instr
);
343 nir_instr_remove(&s_store
->instr
);
345 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
352 /* Flushes undefined values to zero */
355 optimise_nir(nir_shader
*nir
, unsigned quirks
, bool is_blend
)
358 unsigned lower_flrp
=
359 (nir
->options
->lower_flrp16
? 16 : 0) |
360 (nir
->options
->lower_flrp32
? 32 : 0) |
361 (nir
->options
->lower_flrp64
? 64 : 0);
363 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
364 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
366 nir_lower_tex_options lower_tex_options
= {
367 .lower_txs_lod
= true,
369 .lower_tex_without_implicit_lod
=
370 (quirks
& MIDGARD_EXPLICIT_LOD
),
372 /* TODO: we have native gradient.. */
376 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
381 /* T720 is broken. */
383 if (quirks
& MIDGARD_BROKEN_LOD
)
384 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
386 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_early
);
389 NIR_PASS(progress
, nir
, nir_fuse_io_16
);
394 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
395 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
397 NIR_PASS(progress
, nir
, nir_copy_prop
);
398 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
399 NIR_PASS(progress
, nir
, nir_opt_dce
);
400 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
401 NIR_PASS(progress
, nir
, nir_opt_cse
);
402 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
403 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
404 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
406 if (lower_flrp
!= 0) {
407 bool lower_flrp_progress
= false;
408 NIR_PASS(lower_flrp_progress
,
412 false /* always_precise */,
413 nir
->options
->lower_ffma
);
414 if (lower_flrp_progress
) {
415 NIR_PASS(progress
, nir
,
416 nir_opt_constant_folding
);
420 /* Nothing should rematerialize any flrps, so we only
421 * need to do this lowering once.
426 NIR_PASS(progress
, nir
, nir_opt_undef
);
427 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
429 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
432 nir_var_function_temp
);
434 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
437 /* Must be run at the end to prevent creation of fsin/fcos ops */
438 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
443 NIR_PASS(progress
, nir
, nir_opt_dce
);
444 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
445 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
446 NIR_PASS(progress
, nir
, nir_copy_prop
);
449 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
450 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
452 /* We implement booleans as 32-bit 0/~0 */
453 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
455 /* Now that booleans are lowered, we can run out late opts */
456 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
457 NIR_PASS(progress
, nir
, midgard_nir_cancel_inot
);
459 NIR_PASS(progress
, nir
, nir_copy_prop
);
460 NIR_PASS(progress
, nir
, nir_opt_dce
);
462 /* Take us out of SSA */
463 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
464 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
466 /* We are a vector architecture; write combine where possible */
467 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
468 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
470 NIR_PASS(progress
, nir
, nir_opt_dce
);
473 /* Do not actually emit a load; instead, cache the constant for inlining */
476 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
478 nir_ssa_def def
= instr
->def
;
480 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
482 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
484 #define RAW_CONST_COPY(bits) \
485 nir_const_value_to_array(consts->u##bits, instr->value, \
486 instr->def.num_components, u##bits)
488 switch (instr
->def
.bit_size
) {
502 unreachable("Invalid bit_size for load_const instruction\n");
505 /* Shifted for SSA, +1 for off-by-one */
506 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
509 /* Normally constants are embedded implicitly, but for I/O and such we have to
510 * explicitly emit a move with the constant source */
513 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
515 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
517 if (constant_value
) {
518 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
519 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
520 emit_mir_instruction(ctx
, ins
);
525 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
527 unsigned comp
= src
->swizzle
[0];
529 for (unsigned c
= 1; c
< nr_components
; ++c
) {
530 if (src
->swizzle
[c
] != comp
)
537 #define ALU_CASE(nir, _op) \
539 op = midgard_alu_op_##_op; \
540 assert(src_bitsize == dst_bitsize); \
543 #define ALU_CHECK_CMP(sext) \
544 assert(src_bitsize == 16 || src_bitsize == 32); \
545 assert(dst_bitsize == 16 || dst_bitsize == 32); \
547 #define ALU_CASE_BCAST(nir, _op, count) \
549 op = midgard_alu_op_##_op; \
550 broadcast_swizzle = count; \
551 ALU_CHECK_CMP(true); \
554 #define ALU_CASE_CMP(nir, _op, sext) \
556 op = midgard_alu_op_##_op; \
557 ALU_CHECK_CMP(sext); \
560 /* Analyze the sizes of the dest and inputs to determine reg mode. */
562 static midgard_reg_mode
563 reg_mode_for_nir(nir_alu_instr
*instr
)
565 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
566 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
567 unsigned max_bitsize
= MAX2(src_bitsize
, dst_bitsize
);
569 /* We don't have fp16 LUTs, so we'll want to emit code like:
571 * vlut.fsinr hr0, hr0
573 * where both input and output are 16-bit but the operation is carried
585 max_bitsize
= MAX2(max_bitsize
, 32);
588 /* These get lowered to moves */
589 case nir_op_pack_32_4x8
:
592 case nir_op_pack_32_2x16
:
600 switch (max_bitsize
) {
601 /* Use 16 pipe for 8 since we don't support vec16 yet */
604 return midgard_reg_mode_16
;
606 return midgard_reg_mode_32
;
608 return midgard_reg_mode_64
;
610 unreachable("Invalid bit size");
614 /* Compare mir_lower_invert */
616 nir_accepts_inot(nir_op op
, unsigned src
)
620 case nir_op_iand
: /* TODO: b2f16 */
624 /* Only the condition */
632 mir_accept_dest_mod(compiler_context
*ctx
, nir_dest
**dest
, nir_op op
)
634 if (pan_has_dest_mod(dest
, op
)) {
635 assert((*dest
)->is_ssa
);
636 BITSET_SET(ctx
->already_emitted
, (*dest
)->ssa
.index
);
644 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
, bool *abs
, bool *neg
, bool *not, bool is_int
, unsigned bcast_count
)
646 nir_alu_src src
= instr
->src
[i
];
649 if (pan_has_source_mod(&src
, nir_op_fneg
))
652 if (pan_has_source_mod(&src
, nir_op_fabs
))
656 if (nir_accepts_inot(instr
->op
, i
) && pan_has_source_mod(&src
, nir_op_inot
))
659 unsigned bits
= nir_src_bit_size(src
.src
);
661 ins
->src
[to
] = nir_src_index(NULL
, &src
.src
);
662 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
664 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
665 ins
->swizzle
[to
][c
] = src
.swizzle
[
666 (!bcast_count
|| c
< bcast_count
) ? c
:
671 /* Midgard features both fcsel and icsel, depending on whether you want int or
672 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
673 * we should emit an int or float csel depending on what modifiers could be
674 * placed. In the absense of modifiers, this is probably arbitrary. */
677 mir_is_bcsel_float(nir_alu_instr
*instr
)
680 nir_op_i2i8
, nir_op_i2i16
,
681 nir_op_i2i32
, nir_op_i2i64
684 nir_op floatmods
[] = {
685 nir_op_fabs
, nir_op_fneg
,
686 nir_op_f2f16
, nir_op_f2f32
,
690 nir_op floatdestmods
[] = {
691 nir_op_fsat
, nir_op_fsat_signed
, nir_op_fclamp_pos
,
692 nir_op_f2f16
, nir_op_f2f32
697 for (unsigned i
= 1; i
< 3; ++i
) {
698 nir_alu_src s
= instr
->src
[i
];
699 for (unsigned q
= 0; q
< ARRAY_SIZE(intmods
); ++q
) {
700 if (pan_has_source_mod(&s
, intmods
[q
]))
705 for (unsigned i
= 1; i
< 3; ++i
) {
706 nir_alu_src s
= instr
->src
[i
];
707 for (unsigned q
= 0; q
< ARRAY_SIZE(floatmods
); ++q
) {
708 if (pan_has_source_mod(&s
, floatmods
[q
]))
713 for (unsigned q
= 0; q
< ARRAY_SIZE(floatdestmods
); ++q
) {
714 nir_dest
*dest
= &instr
->dest
.dest
;
715 if (pan_has_dest_mod(&dest
, floatdestmods
[q
]))
723 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
725 nir_dest
*dest
= &instr
->dest
.dest
;
727 if (dest
->is_ssa
&& BITSET_TEST(ctx
->already_emitted
, dest
->ssa
.index
))
730 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
731 * is handled elsewhere */
733 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
734 midgard_emit_derivatives(ctx
, instr
);
738 bool is_ssa
= dest
->is_ssa
;
740 unsigned nr_components
= nir_dest_num_components(*dest
);
741 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
744 /* Number of components valid to check for the instruction (the rest
745 * will be forced to the last), or 0 to use as-is. Relevant as
746 * ball-type instructions have a channel count in NIR but are all vec4
749 unsigned broadcast_swizzle
= 0;
751 /* What register mode should we operate in? */
752 midgard_reg_mode reg_mode
=
753 reg_mode_for_nir(instr
);
755 /* Should we swap arguments? */
756 bool flip_src12
= false;
758 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
759 unsigned dst_bitsize
= nir_dest_bit_size(*dest
);
762 ALU_CASE(fadd
, fadd
);
763 ALU_CASE(fmul
, fmul
);
764 ALU_CASE(fmin
, fmin
);
765 ALU_CASE(fmax
, fmax
);
766 ALU_CASE(imin
, imin
);
767 ALU_CASE(imax
, imax
);
768 ALU_CASE(umin
, umin
);
769 ALU_CASE(umax
, umax
);
770 ALU_CASE(ffloor
, ffloor
);
771 ALU_CASE(fround_even
, froundeven
);
772 ALU_CASE(ftrunc
, ftrunc
);
773 ALU_CASE(fceil
, fceil
);
774 ALU_CASE(fdot3
, fdot3
);
775 ALU_CASE(fdot4
, fdot4
);
776 ALU_CASE(iadd
, iadd
);
777 ALU_CASE(isub
, isub
);
778 ALU_CASE(imul
, imul
);
780 /* Zero shoved as second-arg */
781 ALU_CASE(iabs
, iabsdiff
);
785 ALU_CASE_CMP(feq32
, feq
, false);
786 ALU_CASE_CMP(fne32
, fne
, false);
787 ALU_CASE_CMP(flt32
, flt
, false);
788 ALU_CASE_CMP(ieq32
, ieq
, true);
789 ALU_CASE_CMP(ine32
, ine
, true);
790 ALU_CASE_CMP(ilt32
, ilt
, true);
791 ALU_CASE_CMP(ult32
, ult
, false);
793 /* We don't have a native b2f32 instruction. Instead, like many
794 * GPUs, we exploit booleans as 0/~0 for false/true, and
795 * correspondingly AND
796 * by 1.0 to do the type conversion. For the moment, prime us
799 * iand [whatever], #0
801 * At the end of emit_alu (as MIR), we'll fix-up the constant
804 ALU_CASE_CMP(b2f32
, iand
, true);
805 ALU_CASE_CMP(b2f16
, iand
, true);
806 ALU_CASE_CMP(b2i32
, iand
, true);
808 /* Likewise, we don't have a dedicated f2b32 instruction, but
809 * we can do a "not equal to 0.0" test. */
811 ALU_CASE_CMP(f2b32
, fne
, false);
812 ALU_CASE_CMP(i2b32
, ine
, true);
814 ALU_CASE(frcp
, frcp
);
815 ALU_CASE(frsq
, frsqrt
);
816 ALU_CASE(fsqrt
, fsqrt
);
817 ALU_CASE(fexp2
, fexp2
);
818 ALU_CASE(flog2
, flog2
);
820 ALU_CASE(f2i64
, f2i_rtz
);
821 ALU_CASE(f2u64
, f2u_rtz
);
822 ALU_CASE(i2f64
, i2f_rtz
);
823 ALU_CASE(u2f64
, u2f_rtz
);
825 ALU_CASE(f2i32
, f2i_rtz
);
826 ALU_CASE(f2u32
, f2u_rtz
);
827 ALU_CASE(i2f32
, i2f_rtz
);
828 ALU_CASE(u2f32
, u2f_rtz
);
830 ALU_CASE(f2i16
, f2i_rtz
);
831 ALU_CASE(f2u16
, f2u_rtz
);
832 ALU_CASE(i2f16
, i2f_rtz
);
833 ALU_CASE(u2f16
, u2f_rtz
);
835 ALU_CASE(fsin
, fsin
);
836 ALU_CASE(fcos
, fcos
);
838 /* We'll get 0 in the second arg, so:
839 * ~a = ~(a | 0) = nor(a, 0) */
840 ALU_CASE(inot
, inor
);
841 ALU_CASE(iand
, iand
);
843 ALU_CASE(ixor
, ixor
);
844 ALU_CASE(ishl
, ishl
);
845 ALU_CASE(ishr
, iasr
);
846 ALU_CASE(ushr
, ilsr
);
848 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
849 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
850 ALU_CASE_CMP(b32all_fequal4
, fball_eq
, true);
852 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
853 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
854 ALU_CASE_CMP(b32any_fnequal4
, fbany_neq
, true);
856 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
857 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
858 ALU_CASE_CMP(b32all_iequal4
, iball_eq
, true);
860 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
861 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
862 ALU_CASE_CMP(b32any_inequal4
, ibany_neq
, true);
864 /* Source mods will be shoved in later */
865 ALU_CASE(fabs
, fmov
);
866 ALU_CASE(fneg
, fmov
);
867 ALU_CASE(fsat
, fmov
);
868 ALU_CASE(fsat_signed
, fmov
);
869 ALU_CASE(fclamp_pos
, fmov
);
871 /* For size conversion, we use a move. Ideally though we would squash
872 * these ops together; maybe that has to happen after in NIR as part of
873 * propagation...? An earlier algebraic pass ensured we step down by
874 * only / exactly one size. If stepping down, we use a dest override to
875 * reduce the size; if stepping up, we use a larger-sized move with a
876 * half source and a sign/zero-extension modifier */
889 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
890 instr
->op
== nir_op_f2f64
)
891 op
= midgard_alu_op_fmov
;
893 op
= midgard_alu_op_imov
;
898 /* For greater-or-equal, we lower to less-or-equal and flip the
906 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
907 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
908 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
909 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
913 ALU_CHECK_CMP(false);
917 case nir_op_b32csel
: {
918 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
919 bool is_float
= mir_is_bcsel_float(instr
);
921 (mixed
? midgard_alu_op_fcsel_v
: midgard_alu_op_fcsel
) :
922 (mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
);
927 case nir_op_unpack_32_2x16
:
928 case nir_op_unpack_32_4x8
:
929 case nir_op_pack_32_2x16
:
930 case nir_op_pack_32_4x8
: {
931 op
= midgard_alu_op_imov
;
936 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
941 /* Promote imov to fmov if it might help inline a constant */
942 if (op
== midgard_alu_op_imov
&& nir_src_is_const(instr
->src
[0].src
)
943 && nir_src_bit_size(instr
->src
[0].src
) == 32
944 && nir_is_same_comp_swizzle(instr
->src
[0].swizzle
,
945 nir_src_num_components(instr
->src
[0].src
))) {
946 op
= midgard_alu_op_fmov
;
949 /* Midgard can perform certain modifiers on output of an ALU op */
952 bool is_int
= midgard_is_integer_op(op
);
954 if (midgard_is_integer_out_op(op
)) {
955 outmod
= midgard_outmod_int_wrap
;
956 } else if (instr
->op
== nir_op_fsat
) {
957 outmod
= midgard_outmod_sat
;
958 } else if (instr
->op
== nir_op_fsat_signed
) {
959 outmod
= midgard_outmod_sat_signed
;
960 } else if (instr
->op
== nir_op_fclamp_pos
) {
961 outmod
= midgard_outmod_pos
;
964 /* Fetch unit, quirks, etc information */
965 unsigned opcode_props
= alu_opcode_props
[op
].props
;
966 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
968 /* Look for floating point mods. We have the mods fsat, fsat_signed,
969 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
971 * fsat_signed(fpos(x)) = fsat(x)
972 * fsat_signed(fsat(x)) = fsat(x)
973 * fpos(fsat_signed(x)) = fsat(x)
974 * fpos(fsat(x)) = fsat(x)
975 * fsat(fsat_signed(x)) = fsat(x)
976 * fsat(fpos(x)) = fsat(x)
978 * So by cases any composition of output modifiers is equivalent to
982 if (!is_int
&& !(opcode_props
& OP_TYPE_CONVERT
)) {
983 bool fpos
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fclamp_pos
);
984 bool fsat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat
);
985 bool ssat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat_signed
);
986 bool prior
= (outmod
!= midgard_outmod_none
);
987 int count
= (int) prior
+ (int) fpos
+ (int) ssat
+ (int) fsat
;
989 outmod
= ((count
> 1) || fsat
) ? midgard_outmod_sat
:
990 fpos
? midgard_outmod_pos
:
991 ssat
? midgard_outmod_sat_signed
:
995 midgard_instruction ins
= {
997 .dest
= nir_dest_index(dest
),
998 .dest_type
= nir_op_infos
[instr
->op
].output_type
999 | nir_dest_bit_size(*dest
),
1002 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
1005 if (quirk_flipped_r24
) {
1007 mir_copy_src(&ins
, instr
, 0, 1, &ins
.src_abs
[1], &ins
.src_neg
[1], &ins
.src_invert
[1], is_int
, broadcast_swizzle
);
1009 for (unsigned i
= 0; i
< nr_inputs
; ++i
) {
1012 if (instr
->op
== nir_op_b32csel
) {
1013 /* The condition is the first argument; move
1014 * the other arguments up one to be a binary
1015 * instruction for Midgard with the condition
1020 else if (flip_src12
)
1024 } else if (flip_src12
) {
1028 mir_copy_src(&ins
, instr
, i
, to
, &ins
.src_abs
[to
], &ins
.src_neg
[to
], &ins
.src_invert
[to
], is_int
, broadcast_swizzle
);
1030 /* (!c) ? a : b = c ? b : a */
1031 if (instr
->op
== nir_op_b32csel
&& ins
.src_invert
[2]) {
1032 ins
.src_invert
[2] = false;
1038 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1039 /* Lowered to move */
1040 if (instr
->op
== nir_op_fneg
)
1041 ins
.src_neg
[1] ^= true;
1043 if (instr
->op
== nir_op_fabs
)
1044 ins
.src_abs
[1] = true;
1047 ins
.mask
= mask_of(nr_components
);
1049 midgard_vector_alu alu
= {
1051 .reg_mode
= reg_mode
,
1055 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1056 * components that don't exist. Note modifier => SSA => !reg => no
1057 * writemask, so we don't have to worry about writemasks here.*/
1060 ins
.mask
&= instr
->dest
.write_mask
;
1064 /* Late fixup for emulated instructions */
1066 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1067 /* Presently, our second argument is an inline #0 constant.
1068 * Switch over to an embedded 1.0 constant (that can't fit
1069 * inline, since we're 32-bit, not 16-bit like the inline
1072 ins
.has_inline_constant
= false;
1073 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1074 ins
.src_types
[1] = nir_type_float32
;
1075 ins
.has_constants
= true;
1077 if (instr
->op
== nir_op_b2f32
)
1078 ins
.constants
.f32
[0] = 1.0f
;
1080 ins
.constants
.i32
[0] = 1;
1082 for (unsigned c
= 0; c
< 16; ++c
)
1083 ins
.swizzle
[1][c
] = 0;
1084 } else if (instr
->op
== nir_op_b2f16
) {
1085 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1086 ins
.src_types
[1] = nir_type_float16
;
1087 ins
.has_constants
= true;
1088 ins
.constants
.i16
[0] = _mesa_float_to_half(1.0);
1090 for (unsigned c
= 0; c
< 16; ++c
)
1091 ins
.swizzle
[1][c
] = 0;
1092 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1093 /* Lots of instructions need a 0 plonked in */
1094 ins
.has_inline_constant
= false;
1095 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1096 ins
.src_types
[1] = nir_type_uint32
;
1097 ins
.has_constants
= true;
1098 ins
.constants
.u32
[0] = 0;
1100 for (unsigned c
= 0; c
< 16; ++c
)
1101 ins
.swizzle
[1][c
] = 0;
1102 } else if (instr
->op
== nir_op_pack_32_2x16
) {
1103 ins
.dest_type
= nir_type_uint16
;
1104 ins
.mask
= mask_of(nr_components
* 2);
1106 } else if (instr
->op
== nir_op_pack_32_4x8
) {
1107 ins
.dest_type
= nir_type_uint8
;
1108 ins
.mask
= mask_of(nr_components
* 4);
1110 } else if (instr
->op
== nir_op_unpack_32_2x16
) {
1111 ins
.dest_type
= nir_type_uint32
;
1112 ins
.mask
= mask_of(nr_components
>> 1);
1114 } else if (instr
->op
== nir_op_unpack_32_4x8
) {
1115 ins
.dest_type
= nir_type_uint32
;
1116 ins
.mask
= mask_of(nr_components
>> 2);
1120 /* Arrange for creation of iandnot/iornot */
1121 if (ins
.src_invert
[0] && !ins
.src_invert
[1]) {
1123 ins
.src_invert
[0] = false;
1124 ins
.src_invert
[1] = true;
1127 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1128 /* To avoid duplicating the lookup tables (probably), true LUT
1129 * instructions can only operate as if they were scalars. Lower
1130 * them here by changing the component. */
1132 unsigned orig_mask
= ins
.mask
;
1134 unsigned swizzle_back
[MIR_VEC_COMPONENTS
];
1135 memcpy(&swizzle_back
, ins
.swizzle
[0], sizeof(swizzle_back
));
1137 for (int i
= 0; i
< nr_components
; ++i
) {
1138 /* Mask the associated component, dropping the
1139 * instruction if needed */
1142 ins
.mask
&= orig_mask
;
1147 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1148 ins
.swizzle
[0][j
] = swizzle_back
[i
]; /* Pull from the correct component */
1150 emit_mir_instruction(ctx
, ins
);
1153 emit_mir_instruction(ctx
, ins
);
1160 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1162 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1163 unsigned nir_mask
= 0;
1167 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1168 dsize
= nir_dest_bit_size(intr
->dest
);
1170 nir_mask
= nir_intrinsic_write_mask(intr
);
1174 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1175 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1176 mir_set_bytemask(ins
, bytemask
);
1177 ins
->dest_type
= nir_type_uint
| dsize
;
1180 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1181 * optimized) versions of UBO #0 */
1183 static midgard_instruction
*
1185 compiler_context
*ctx
,
1189 nir_src
*indirect_offset
,
1190 unsigned indirect_shift
,
1193 /* TODO: half-floats */
1195 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1196 ins
.constants
.u32
[0] = offset
;
1198 if (instr
->type
== nir_instr_type_intrinsic
)
1199 mir_set_intr_mask(instr
, &ins
, true);
1201 if (indirect_offset
) {
1202 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1203 ins
.src_types
[2] = nir_type_uint32
;
1204 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1206 ins
.load_store
.arg_2
= 0x1E;
1209 ins
.load_store
.arg_1
= index
;
1211 return emit_mir_instruction(ctx
, ins
);
1214 /* Globals are like UBOs if you squint. And shared memory is like globals if
1215 * you squint even harder */
1219 compiler_context
*ctx
,
1228 midgard_instruction ins
;
1231 ins
= m_ld_int4(srcdest
, 0);
1233 ins
= m_st_int4(srcdest
, 0);
1235 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1236 mir_set_intr_mask(instr
, &ins
, is_read
);
1238 emit_mir_instruction(ctx
, ins
);
1243 compiler_context
*ctx
,
1244 unsigned dest
, unsigned offset
,
1245 unsigned nr_comp
, unsigned component
,
1246 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1248 /* XXX: Half-floats? */
1249 /* TODO: swizzle, mask */
1251 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1252 ins
.mask
= mask_of(nr_comp
);
1254 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1255 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1257 midgard_varying_parameter p
= {
1259 .interpolation
= midgard_interp_default
,
1264 memcpy(&u
, &p
, sizeof(p
));
1265 ins
.load_store
.varying_parameters
= u
;
1267 if (indirect_offset
) {
1268 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1269 ins
.src_types
[2] = nir_type_uint32
;
1271 ins
.load_store
.arg_2
= 0x1E;
1273 ins
.load_store
.arg_1
= 0x9E;
1275 /* Use the type appropriate load */
1277 case nir_type_uint32
:
1278 case nir_type_bool32
:
1279 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1281 case nir_type_int32
:
1282 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1284 case nir_type_float32
:
1285 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1287 case nir_type_float16
:
1288 ins
.load_store
.op
= midgard_op_ld_vary_16
;
1291 unreachable("Attempted to load unknown type");
1295 emit_mir_instruction(ctx
, ins
);
1300 compiler_context
*ctx
,
1301 unsigned dest
, unsigned offset
,
1302 unsigned nr_comp
, nir_alu_type t
)
1304 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1305 ins
.load_store
.arg_1
= 0x1E;
1306 ins
.load_store
.arg_2
= 0x1E;
1307 ins
.mask
= mask_of(nr_comp
);
1309 /* Use the type appropriate load */
1313 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1316 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1318 case nir_type_float
:
1319 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1322 unreachable("Attempted to load unknown type");
1326 emit_mir_instruction(ctx
, ins
);
1330 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1331 unsigned nr_components
, unsigned offset
)
1335 /* Figure out which uniform this is */
1336 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1337 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1339 unsigned dest
= nir_dest_index(&nir_dest
);
1341 /* Sysvals are prefix uniforms */
1342 unsigned uniform
= ((uintptr_t) val
) - 1;
1344 /* Emit the read itself -- this is never indirect */
1345 midgard_instruction
*ins
=
1346 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1348 ins
->mask
= mask_of(nr_components
);
1352 compute_builtin_arg(nir_op op
)
1355 case nir_intrinsic_load_work_group_id
:
1357 case nir_intrinsic_load_local_invocation_id
:
1360 unreachable("Invalid compute paramater loaded");
1365 emit_fragment_store(compiler_context
*ctx
, unsigned src
, enum midgard_rt_id rt
)
1367 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1369 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1373 emit_explicit_constant(ctx
, src
, src
);
1375 struct midgard_instruction ins
=
1376 v_branch(false, false);
1378 ins
.writeout
= true;
1380 /* Add dependencies */
1382 ins
.src_types
[0] = nir_type_uint32
;
1383 ins
.constants
.u32
[0] = rt
== MIDGARD_ZS_RT
?
1384 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1386 /* Emit the branch */
1387 br
= emit_mir_instruction(ctx
, ins
);
1388 schedule_barrier(ctx
);
1389 ctx
->writeout_branch
[rt
] = br
;
1391 /* Push our current location = current block count - 1 = where we'll
1392 * jump to. Maybe a bit too clever for my own good */
1394 br
->branch
.target_block
= ctx
->block_count
- 1;
1398 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1400 unsigned reg
= nir_dest_index(&instr
->dest
);
1401 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1402 ins
.mask
= mask_of(3);
1403 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1404 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1405 emit_mir_instruction(ctx
, ins
);
1409 vertex_builtin_arg(nir_op op
)
1412 case nir_intrinsic_load_vertex_id
:
1413 return PAN_VERTEX_ID
;
1414 case nir_intrinsic_load_instance_id
:
1415 return PAN_INSTANCE_ID
;
1417 unreachable("Invalid vertex builtin");
1422 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1424 unsigned reg
= nir_dest_index(&instr
->dest
);
1425 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1429 emit_control_barrier(compiler_context
*ctx
)
1431 midgard_instruction ins
= {
1432 .type
= TAG_TEXTURE_4
,
1434 .src
= { ~0, ~0, ~0, ~0 },
1436 .op
= TEXTURE_OP_BARRIER
,
1438 /* TODO: optimize */
1439 .barrier_buffer
= 1,
1444 emit_mir_instruction(ctx
, ins
);
1447 static const nir_variable
*
1448 search_var(struct exec_list
*vars
, unsigned driver_loc
)
1450 nir_foreach_variable(var
, vars
) {
1451 if (var
->data
.driver_location
== driver_loc
)
1459 mir_get_branch_cond(nir_src
*src
, bool *invert
)
1461 /* Wrap it. No swizzle since it's a scalar */
1467 *invert
= pan_has_source_mod(&alu
, nir_op_inot
);
1468 return nir_src_index(NULL
, &alu
.src
);
1472 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1474 unsigned offset
= 0, reg
;
1476 switch (instr
->intrinsic
) {
1477 case nir_intrinsic_discard_if
:
1478 case nir_intrinsic_discard
: {
1479 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1480 struct midgard_instruction discard
= v_branch(conditional
, false);
1481 discard
.branch
.target_type
= TARGET_DISCARD
;
1484 discard
.src
[0] = mir_get_branch_cond(&instr
->src
[0],
1485 &discard
.branch
.invert_conditional
);
1486 discard
.src_types
[0] = nir_type_uint32
;
1489 emit_mir_instruction(ctx
, discard
);
1490 schedule_barrier(ctx
);
1495 case nir_intrinsic_load_uniform
:
1496 case nir_intrinsic_load_ubo
:
1497 case nir_intrinsic_load_global
:
1498 case nir_intrinsic_load_shared
:
1499 case nir_intrinsic_load_input
:
1500 case nir_intrinsic_load_interpolated_input
: {
1501 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1502 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1503 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1504 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1505 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1506 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1508 /* Get the base type of the intrinsic */
1509 /* TODO: Infer type? Does it matter? */
1511 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1512 (is_interp
) ? nir_type_float
:
1513 nir_intrinsic_type(instr
);
1515 t
= nir_alu_type_get_base_type(t
);
1517 if (!(is_ubo
|| is_global
)) {
1518 offset
= nir_intrinsic_base(instr
);
1521 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1523 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1525 bool direct
= nir_src_is_const(*src_offset
);
1526 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1529 offset
+= nir_src_as_uint(*src_offset
);
1531 /* We may need to apply a fractional offset */
1532 int component
= (is_flat
|| is_interp
) ?
1533 nir_intrinsic_component(instr
) : 0;
1534 reg
= nir_dest_index(&instr
->dest
);
1536 if (is_uniform
&& !ctx
->is_blend
) {
1537 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1538 } else if (is_ubo
) {
1539 nir_src index
= instr
->src
[0];
1541 /* TODO: Is indirect block number possible? */
1542 assert(nir_src_is_const(index
));
1544 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1545 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1546 } else if (is_global
|| is_shared
) {
1547 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1548 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1549 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
| nir_dest_bit_size(instr
->dest
), is_flat
);
1550 } else if (ctx
->is_blend
) {
1551 /* For blend shaders, load the input color, which is
1552 * preloaded to r0 */
1554 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1555 emit_mir_instruction(ctx
, move
);
1556 schedule_barrier(ctx
);
1557 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1558 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1560 DBG("Unknown load\n");
1567 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1568 case nir_intrinsic_load_barycentric_pixel
:
1569 case nir_intrinsic_load_barycentric_centroid
:
1572 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1574 case nir_intrinsic_load_raw_output_pan
:
1575 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1576 reg
= nir_dest_index(&instr
->dest
);
1577 assert(ctx
->is_blend
);
1579 /* T720 and below use different blend opcodes with slightly
1580 * different semantics than T760 and up */
1582 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1583 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1585 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1586 ld
.load_store
.op
= old_blend
?
1587 midgard_op_ld_color_buffer_as_fp16_old
:
1588 midgard_op_ld_color_buffer_as_fp16
;
1590 for (unsigned c
= 4; c
< 16; ++c
)
1591 ld
.swizzle
[0][c
] = 0;
1593 ld
.dest_type
= nir_type_float16
;
1596 ld
.load_store
.address
= 1;
1597 ld
.load_store
.arg_2
= 0x1E;
1599 } else if (old_blend
) {
1600 ld
.load_store
.op
= midgard_op_ld_color_buffer_32u_old
;
1601 ld
.load_store
.address
= 16;
1602 ld
.load_store
.arg_2
= 0x1E;
1605 emit_mir_instruction(ctx
, ld
);
1608 case nir_intrinsic_load_blend_const_color_rgba
: {
1609 assert(ctx
->is_blend
);
1610 reg
= nir_dest_index(&instr
->dest
);
1612 /* Blend constants are embedded directly in the shader and
1613 * patched in, so we use some magic routing */
1615 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1616 ins
.has_constants
= true;
1617 ins
.has_blend_constant
= true;
1618 emit_mir_instruction(ctx
, ins
);
1622 case nir_intrinsic_store_zs_output_pan
: {
1623 assert(ctx
->stage
== MESA_SHADER_FRAGMENT
);
1624 emit_fragment_store(ctx
, nir_src_index(ctx
, &instr
->src
[0]),
1627 midgard_instruction
*br
= ctx
->writeout_branch
[MIDGARD_ZS_RT
];
1629 if (!nir_intrinsic_component(instr
))
1630 br
->writeout_depth
= true;
1631 if (nir_intrinsic_component(instr
) ||
1632 instr
->num_components
)
1633 br
->writeout_stencil
= true;
1634 assert(br
->writeout_depth
| br
->writeout_stencil
);
1638 case nir_intrinsic_store_output
:
1639 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1641 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1643 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1645 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1646 const nir_variable
*var
;
1647 enum midgard_rt_id rt
;
1649 var
= search_var(&ctx
->nir
->outputs
,
1650 nir_intrinsic_base(instr
));
1652 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1653 rt
= MIDGARD_COLOR_RT0
;
1654 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1655 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1660 emit_fragment_store(ctx
, reg
, rt
);
1661 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1662 /* We should have been vectorized, though we don't
1663 * currently check that st_vary is emitted only once
1664 * per slot (this is relevant, since there's not a mask
1665 * parameter available on the store [set to 0 by the
1666 * blob]). We do respect the component by adjusting the
1667 * swizzle. If this is a constant source, we'll need to
1668 * emit that explicitly. */
1670 emit_explicit_constant(ctx
, reg
, reg
);
1672 unsigned dst_component
= nir_intrinsic_component(instr
);
1673 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1675 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1676 st
.load_store
.arg_1
= 0x9E;
1677 st
.load_store
.arg_2
= 0x1E;
1679 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1682 st
.load_store
.op
= midgard_op_st_vary_32u
;
1685 st
.load_store
.op
= midgard_op_st_vary_32i
;
1687 case nir_type_float
:
1688 st
.load_store
.op
= midgard_op_st_vary_32
;
1691 unreachable("Attempted to store unknown type");
1695 /* nir_intrinsic_component(store_intr) encodes the
1696 * destination component start. Source component offset
1697 * adjustment is taken care of in
1698 * install_registers_instr(), when offset_swizzle() is
1701 unsigned src_component
= COMPONENT_X
;
1703 assert(nr_comp
> 0);
1704 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1705 st
.swizzle
[0][i
] = src_component
;
1706 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1710 emit_mir_instruction(ctx
, st
);
1712 DBG("Unknown store\n");
1718 /* Special case of store_output for lowered blend shaders */
1719 case nir_intrinsic_store_raw_output_pan
:
1720 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1721 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1723 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1724 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1725 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1728 * imov r0.xyzw, r0.xxxx
1731 unsigned expanded
= make_compiler_temp(ctx
);
1733 midgard_instruction splatter
= v_mov(reg
, expanded
);
1735 for (unsigned c
= 0; c
< 16; ++c
)
1736 splatter
.swizzle
[1][c
] = 0;
1738 emit_mir_instruction(ctx
, splatter
);
1739 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1741 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1745 case nir_intrinsic_store_global
:
1746 case nir_intrinsic_store_shared
:
1747 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1748 emit_explicit_constant(ctx
, reg
, reg
);
1750 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1753 case nir_intrinsic_load_ssbo_address
:
1754 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1757 case nir_intrinsic_get_buffer_size
:
1758 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1761 case nir_intrinsic_load_viewport_scale
:
1762 case nir_intrinsic_load_viewport_offset
:
1763 case nir_intrinsic_load_num_work_groups
:
1764 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1765 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1768 case nir_intrinsic_load_work_group_id
:
1769 case nir_intrinsic_load_local_invocation_id
:
1770 emit_compute_builtin(ctx
, instr
);
1773 case nir_intrinsic_load_vertex_id
:
1774 case nir_intrinsic_load_instance_id
:
1775 emit_vertex_builtin(ctx
, instr
);
1778 case nir_intrinsic_memory_barrier_buffer
:
1779 case nir_intrinsic_memory_barrier_shared
:
1782 case nir_intrinsic_control_barrier
:
1783 schedule_barrier(ctx
);
1784 emit_control_barrier(ctx
);
1785 schedule_barrier(ctx
);
1789 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1796 midgard_tex_format(enum glsl_sampler_dim dim
)
1799 case GLSL_SAMPLER_DIM_1D
:
1800 case GLSL_SAMPLER_DIM_BUF
:
1803 case GLSL_SAMPLER_DIM_2D
:
1804 case GLSL_SAMPLER_DIM_EXTERNAL
:
1805 case GLSL_SAMPLER_DIM_RECT
:
1808 case GLSL_SAMPLER_DIM_3D
:
1811 case GLSL_SAMPLER_DIM_CUBE
:
1812 return MALI_TEX_CUBE
;
1815 DBG("Unknown sampler dim type\n");
1821 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1825 pan_attach_constant_bias(
1826 compiler_context
*ctx
,
1828 midgard_texture_word
*word
)
1830 /* To attach as constant, it has to *be* constant */
1832 if (!nir_src_is_const(lod
))
1835 float f
= nir_src_as_float(lod
);
1837 /* Break into fixed-point */
1839 float lod_frac
= f
- lod_int
;
1841 /* Carry over negative fractions */
1842 if (lod_frac
< 0.0) {
1848 word
->bias
= float_to_ubyte(lod_frac
);
1849 word
->bias_int
= lod_int
;
1855 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1856 unsigned midgard_texop
)
1859 //assert (!instr->sampler);
1861 int texture_index
= instr
->texture_index
;
1862 int sampler_index
= texture_index
;
1864 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
1865 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(instr
->dest
);
1867 midgard_instruction ins
= {
1868 .type
= TAG_TEXTURE_4
,
1870 .dest
= nir_dest_index(&instr
->dest
),
1871 .src
= { ~0, ~0, ~0, ~0 },
1872 .dest_type
= dest_type
,
1873 .swizzle
= SWIZZLE_IDENTITY_4
,
1875 .op
= midgard_texop
,
1876 .format
= midgard_tex_format(instr
->sampler_dim
),
1877 .texture_handle
= texture_index
,
1878 .sampler_handle
= sampler_index
,
1879 .shadow
= instr
->is_shadow
,
1883 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
1884 for (int i
= 0; i
< 4; ++i
)
1885 ins
.swizzle
[0][i
] = COMPONENT_X
;
1887 /* We may need a temporary for the coordinate */
1889 bool needs_temp_coord
=
1890 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1891 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
1894 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1896 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1897 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1898 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1899 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
1900 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
1902 switch (instr
->src
[i
].src_type
) {
1903 case nir_tex_src_coord
: {
1904 emit_explicit_constant(ctx
, index
, index
);
1906 unsigned coord_mask
= mask_of(instr
->coord_components
);
1908 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
1911 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
1913 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1914 /* texelFetch is undefined on samplerCube */
1915 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1917 /* For cubemaps, we use a special ld/st op to
1918 * select the face and copy the xy into the
1919 * texture register */
1921 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
1923 ld
.src_types
[1] = T
;
1924 ld
.mask
= 0x3; /* xy */
1925 ld
.load_store
.arg_1
= 0x20;
1926 ld
.swizzle
[1][3] = COMPONENT_X
;
1927 emit_mir_instruction(ctx
, ld
);
1930 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1931 ins
.swizzle
[1][3] = COMPONENT_X
;
1932 } else if (needs_temp_coord
) {
1933 /* mov coord_temp, coords */
1934 midgard_instruction mov
= v_mov(index
, coords
);
1935 mov
.mask
= coord_mask
;
1938 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
1940 emit_mir_instruction(ctx
, mov
);
1945 ins
.src
[1] = coords
;
1946 ins
.src_types
[1] = T
;
1948 /* Texelfetch coordinates uses all four elements
1949 * (xyz/index) regardless of texture dimensionality,
1950 * which means it's necessary to zero the unused
1951 * components to keep everything happy */
1953 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1954 /* mov index.zw, #0, or generalized */
1955 midgard_instruction mov
=
1956 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1957 mov
.has_constants
= true;
1958 mov
.mask
= coord_mask
^ 0xF;
1959 emit_mir_instruction(ctx
, mov
);
1962 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1963 /* Array component in w but NIR wants it in z,
1964 * but if we have a temp coord we already fixed
1967 if (nr_components
== 3) {
1968 ins
.swizzle
[1][2] = COMPONENT_Z
;
1969 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
1970 } else if (nr_components
== 2) {
1972 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1973 ins
.swizzle
[1][3] = COMPONENT_X
;
1975 unreachable("Invalid texture 2D components");
1978 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1980 ins
.swizzle
[1][2] = COMPONENT_Z
;
1981 ins
.swizzle
[1][3] = COMPONENT_W
;
1987 case nir_tex_src_bias
:
1988 case nir_tex_src_lod
: {
1989 /* Try as a constant if we can */
1991 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1992 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1995 ins
.texture
.lod_register
= true;
1997 ins
.src_types
[2] = T
;
1999 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2000 ins
.swizzle
[2][c
] = COMPONENT_X
;
2002 emit_explicit_constant(ctx
, index
, index
);
2007 case nir_tex_src_offset
: {
2008 ins
.texture
.offset_register
= true;
2010 ins
.src_types
[3] = T
;
2012 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2013 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
2015 emit_explicit_constant(ctx
, index
, index
);
2019 case nir_tex_src_comparator
: {
2020 unsigned comp
= COMPONENT_Z
;
2022 /* mov coord_temp.foo, coords */
2023 midgard_instruction mov
= v_mov(index
, coords
);
2024 mov
.mask
= 1 << comp
;
2026 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2027 mov
.swizzle
[1][i
] = COMPONENT_X
;
2029 emit_mir_instruction(ctx
, mov
);
2034 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2040 emit_mir_instruction(ctx
, ins
);
2044 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2046 switch (instr
->op
) {
2049 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2052 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2055 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2058 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
2061 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
2068 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2070 switch (instr
->type
) {
2071 case nir_jump_break
: {
2072 /* Emit a branch out of the loop */
2073 struct midgard_instruction br
= v_branch(false, false);
2074 br
.branch
.target_type
= TARGET_BREAK
;
2075 br
.branch
.target_break
= ctx
->current_loop_depth
;
2076 emit_mir_instruction(ctx
, br
);
2081 DBG("Unknown jump type %d\n", instr
->type
);
2087 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2089 switch (instr
->type
) {
2090 case nir_instr_type_load_const
:
2091 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2094 case nir_instr_type_intrinsic
:
2095 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2098 case nir_instr_type_alu
:
2099 emit_alu(ctx
, nir_instr_as_alu(instr
));
2102 case nir_instr_type_tex
:
2103 emit_tex(ctx
, nir_instr_as_tex(instr
));
2106 case nir_instr_type_jump
:
2107 emit_jump(ctx
, nir_instr_as_jump(instr
));
2110 case nir_instr_type_ssa_undef
:
2115 DBG("Unhandled instruction type\n");
2121 /* ALU instructions can inline or embed constants, which decreases register
2122 * pressure and saves space. */
2124 #define CONDITIONAL_ATTACH(idx) { \
2125 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2128 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2129 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2134 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2136 mir_foreach_instr_in_block(block
, alu
) {
2137 /* Other instructions cannot inline constants */
2138 if (alu
->type
!= TAG_ALU_4
) continue;
2139 if (alu
->compact_branch
) continue;
2141 /* If there is already a constant here, we can do nothing */
2142 if (alu
->has_constants
) continue;
2144 CONDITIONAL_ATTACH(0);
2146 if (!alu
->has_constants
) {
2147 CONDITIONAL_ATTACH(1)
2148 } else if (!alu
->inline_constant
) {
2149 /* Corner case: _two_ vec4 constants, for instance with a
2150 * csel. For this case, we can only use a constant
2151 * register for one, we'll have to emit a move for the
2154 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2155 unsigned scratch
= make_compiler_temp(ctx
);
2158 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2159 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2161 /* Set the source */
2162 alu
->src
[1] = scratch
;
2164 /* Inject us -before- the last instruction which set r31 */
2165 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2171 /* Midgard supports two types of constants, embedded constants (128-bit) and
2172 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2173 * constants can be demoted to inline constants, for space savings and
2174 * sometimes a performance boost */
2177 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2179 mir_foreach_instr_in_block(block
, ins
) {
2180 if (!ins
->has_constants
) continue;
2181 if (ins
->has_inline_constant
) continue;
2183 /* Blend constants must not be inlined by definition */
2184 if (ins
->has_blend_constant
) continue;
2186 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2187 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2188 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2190 if (!(is_16
|| is_32
))
2193 /* src1 cannot be an inline constant due to encoding
2194 * restrictions. So, if possible we try to flip the arguments
2197 int op
= ins
->alu
.op
;
2199 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2200 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2204 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2205 /* Component is from the swizzle. Take a nonzero component */
2207 unsigned first_comp
= ffs(ins
->mask
) - 1;
2208 unsigned component
= ins
->swizzle
[1][first_comp
];
2210 /* Scale constant appropriately, if we can legally */
2211 uint16_t scaled_constant
= 0;
2214 scaled_constant
= ins
->constants
.u16
[component
];
2215 } else if (midgard_is_integer_op(op
)) {
2216 scaled_constant
= ins
->constants
.u32
[component
];
2218 /* Constant overflow after resize */
2219 if (scaled_constant
!= ins
->constants
.u32
[component
])
2222 float original
= ins
->constants
.f32
[component
];
2223 scaled_constant
= _mesa_float_to_half(original
);
2225 /* Check for loss of precision. If this is
2226 * mediump, we don't care, but for a highp
2227 * shader, we need to pay attention. NIR
2228 * doesn't yet tell us which mode we're in!
2229 * Practically this prevents most constants
2230 * from being inlined, sadly. */
2232 float fp32
= _mesa_half_to_float(scaled_constant
);
2234 if (fp32
!= original
)
2238 /* Should've been const folded */
2239 if (ins
->src_abs
[1] || ins
->src_neg
[1])
2242 /* Make sure that the constant is not itself a vector
2243 * by checking if all accessed values are the same. */
2245 const midgard_constants
*cons
= &ins
->constants
;
2246 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2248 bool is_vector
= false;
2249 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2251 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2252 /* We only care if this component is actually used */
2253 if (!(mask
& (1 << c
)))
2256 uint32_t test
= is_16
?
2257 cons
->u16
[ins
->swizzle
[1][c
]] :
2258 cons
->u32
[ins
->swizzle
[1][c
]];
2260 if (test
!= value
) {
2269 /* Get rid of the embedded constant */
2270 ins
->has_constants
= false;
2272 ins
->has_inline_constant
= true;
2273 ins
->inline_constant
= scaled_constant
;
2278 /* Dead code elimination for branches at the end of a block - only one branch
2279 * per block is legal semantically */
2282 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2284 bool branched
= false;
2286 mir_foreach_instr_in_block_safe(block
, ins
) {
2287 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2290 mir_remove_instruction(ins
);
2297 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2299 /* Loop to ourselves */
2300 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2301 struct midgard_instruction ins
= v_branch(false, false);
2302 ins
.writeout
= true;
2303 ins
.writeout_depth
= br
->writeout_depth
;
2304 ins
.writeout_stencil
= br
->writeout_stencil
;
2305 ins
.branch
.target_block
= ctx
->block_count
- 1;
2306 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2307 emit_mir_instruction(ctx
, ins
);
2309 ctx
->current_block
->epilogue
= true;
2310 schedule_barrier(ctx
);
2311 return ins
.branch
.target_block
;
2314 static midgard_block
*
2315 emit_block(compiler_context
*ctx
, nir_block
*block
)
2317 midgard_block
*this_block
= ctx
->after_block
;
2318 ctx
->after_block
= NULL
;
2321 this_block
= create_empty_block(ctx
);
2323 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2325 this_block
->scheduled
= false;
2328 /* Set up current block */
2329 list_inithead(&this_block
->base
.instructions
);
2330 ctx
->current_block
= this_block
;
2332 nir_foreach_instr(instr
, block
) {
2333 emit_instr(ctx
, instr
);
2334 ++ctx
->instruction_count
;
2340 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2343 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2345 midgard_block
*before_block
= ctx
->current_block
;
2347 /* Speculatively emit the branch, but we can't fill it in until later */
2349 EMIT(branch
, true, true);
2350 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2351 then_branch
->src
[0] = mir_get_branch_cond(&nif
->condition
, &inv
);
2352 then_branch
->src_types
[0] = nir_type_uint32
;
2353 then_branch
->branch
.invert_conditional
= !inv
;
2355 /* Emit the two subblocks. */
2356 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2357 midgard_block
*end_then_block
= ctx
->current_block
;
2359 /* Emit a jump from the end of the then block to the end of the else */
2360 EMIT(branch
, false, false);
2361 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2363 /* Emit second block, and check if it's empty */
2365 int else_idx
= ctx
->block_count
;
2366 int count_in
= ctx
->instruction_count
;
2367 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2368 midgard_block
*end_else_block
= ctx
->current_block
;
2369 int after_else_idx
= ctx
->block_count
;
2371 /* Now that we have the subblocks emitted, fix up the branches */
2376 if (ctx
->instruction_count
== count_in
) {
2377 /* The else block is empty, so don't emit an exit jump */
2378 mir_remove_instruction(then_exit
);
2379 then_branch
->branch
.target_block
= after_else_idx
;
2381 then_branch
->branch
.target_block
= else_idx
;
2382 then_exit
->branch
.target_block
= after_else_idx
;
2385 /* Wire up the successors */
2387 ctx
->after_block
= create_empty_block(ctx
);
2389 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2390 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2392 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2393 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2397 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2399 /* Remember where we are */
2400 midgard_block
*start_block
= ctx
->current_block
;
2402 /* Allocate a loop number, growing the current inner loop depth */
2403 int loop_idx
= ++ctx
->current_loop_depth
;
2405 /* Get index from before the body so we can loop back later */
2406 int start_idx
= ctx
->block_count
;
2408 /* Emit the body itself */
2409 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2411 /* Branch back to loop back */
2412 struct midgard_instruction br_back
= v_branch(false, false);
2413 br_back
.branch
.target_block
= start_idx
;
2414 emit_mir_instruction(ctx
, br_back
);
2416 /* Mark down that branch in the graph. */
2417 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2418 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2420 /* Find the index of the block about to follow us (note: we don't add
2421 * one; blocks are 0-indexed so we get a fencepost problem) */
2422 int break_block_idx
= ctx
->block_count
;
2424 /* Fix up the break statements we emitted to point to the right place,
2425 * now that we can allocate a block number for them */
2426 ctx
->after_block
= create_empty_block(ctx
);
2428 mir_foreach_block_from(ctx
, start_block
, _block
) {
2429 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2430 if (ins
->type
!= TAG_ALU_4
) continue;
2431 if (!ins
->compact_branch
) continue;
2433 /* We found a branch -- check the type to see if we need to do anything */
2434 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2436 /* It's a break! Check if it's our break */
2437 if (ins
->branch
.target_break
!= loop_idx
) continue;
2439 /* Okay, cool, we're breaking out of this loop.
2440 * Rewrite from a break to a goto */
2442 ins
->branch
.target_type
= TARGET_GOTO
;
2443 ins
->branch
.target_block
= break_block_idx
;
2445 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2449 /* Now that we've finished emitting the loop, free up the depth again
2450 * so we play nice with recursion amid nested loops */
2451 --ctx
->current_loop_depth
;
2453 /* Dump loop stats */
2457 static midgard_block
*
2458 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2460 midgard_block
*start_block
= NULL
;
2462 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2463 switch (node
->type
) {
2464 case nir_cf_node_block
: {
2465 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2468 start_block
= block
;
2473 case nir_cf_node_if
:
2474 emit_if(ctx
, nir_cf_node_as_if(node
));
2477 case nir_cf_node_loop
:
2478 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2481 case nir_cf_node_function
:
2490 /* Due to lookahead, we need to report the first tag executed in the command
2491 * stream and in branch targets. An initial block might be empty, so iterate
2492 * until we find one that 'works' */
2495 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2497 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2499 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2500 midgard_block
*v
= (midgard_block
*) _v
;
2501 if (v
->quadword_count
) {
2502 midgard_bundle
*initial_bundle
=
2503 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2505 return initial_bundle
->tag
;
2509 /* Default to a tag 1 which will break from the shader, in case we jump
2510 * to the exit block (i.e. `return` in a compute shader) */
2515 /* For each fragment writeout instruction, generate a writeout loop to
2516 * associate with it */
2519 mir_add_writeout_loops(compiler_context
*ctx
)
2521 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2522 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2525 unsigned popped
= br
->branch
.target_block
;
2526 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2527 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2528 br
->branch
.target_type
= TARGET_GOTO
;
2530 /* If we have more RTs, we'll need to restore back after our
2531 * loop terminates */
2533 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2534 midgard_instruction uncond
= v_branch(false, false);
2535 uncond
.branch
.target_block
= popped
;
2536 uncond
.branch
.target_type
= TARGET_GOTO
;
2537 emit_mir_instruction(ctx
, uncond
);
2538 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2539 schedule_barrier(ctx
);
2541 /* We're last, so we can terminate here */
2542 br
->last_writeout
= true;
2548 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2550 struct util_dynarray
*compiled
= &program
->compiled
;
2552 midgard_debug
= debug_get_option_midgard_debug();
2554 /* TODO: Bound against what? */
2555 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2558 ctx
->stage
= nir
->info
.stage
;
2559 ctx
->is_blend
= is_blend
;
2560 ctx
->alpha_ref
= program
->alpha_ref
;
2561 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2562 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2564 /* Start off with a safe cutoff, allowing usage of all 16 work
2565 * registers. Later, we'll promote uniform reads to uniform registers
2566 * if we determine it is beneficial to do so */
2567 ctx
->uniform_cutoff
= 8;
2569 /* Initialize at a global (not block) level hash tables */
2571 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2572 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2574 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2575 * (so we don't accidentally duplicate the epilogue since mesa/st has
2576 * messed with our I/O quite a bit already) */
2578 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2580 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2581 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2582 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2585 NIR_PASS_V(nir
, nir_lower_var_copies
);
2586 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2587 NIR_PASS_V(nir
, nir_split_var_copies
);
2588 NIR_PASS_V(nir
, nir_lower_var_copies
);
2589 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2590 NIR_PASS_V(nir
, nir_lower_var_copies
);
2591 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2593 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2594 NIR_PASS_V(nir
, nir_lower_ssbo
);
2595 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2597 /* Optimisation passes */
2599 optimise_nir(nir
, ctx
->quirks
, is_blend
);
2601 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2602 nir_print_shader(nir
, stdout
);
2605 /* Assign sysvals and counts, now that we're sure
2606 * (post-optimisation) */
2608 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2609 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2610 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2612 nir_foreach_function(func
, nir
) {
2616 list_inithead(&ctx
->blocks
);
2617 ctx
->block_count
= 0;
2619 ctx
->already_emitted
= calloc(BITSET_WORDS(func
->impl
->ssa_alloc
), sizeof(BITSET_WORD
));
2621 emit_cf_list(ctx
, &func
->impl
->body
);
2622 free(ctx
->already_emitted
);
2623 break; /* TODO: Multi-function shaders */
2626 util_dynarray_init(compiled
, NULL
);
2628 /* Per-block lowering before opts */
2630 mir_foreach_block(ctx
, _block
) {
2631 midgard_block
*block
= (midgard_block
*) _block
;
2632 inline_alu_constants(ctx
, block
);
2633 embedded_to_inline_constant(ctx
, block
);
2635 /* MIR-level optimizations */
2637 bool progress
= false;
2641 progress
|= midgard_opt_dead_code_eliminate(ctx
);
2643 mir_foreach_block(ctx
, _block
) {
2644 midgard_block
*block
= (midgard_block
*) _block
;
2645 progress
|= midgard_opt_copy_prop(ctx
, block
);
2646 progress
|= midgard_opt_combine_projection(ctx
, block
);
2647 progress
|= midgard_opt_varying_projection(ctx
, block
);
2651 mir_foreach_block(ctx
, _block
) {
2652 midgard_block
*block
= (midgard_block
*) _block
;
2653 midgard_lower_derivatives(ctx
, block
);
2654 midgard_cull_dead_branch(ctx
, block
);
2657 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2658 mir_add_writeout_loops(ctx
);
2660 /* Analyze now that the code is known but before scheduling creates
2661 * pipeline registers which are harder to track */
2662 mir_analyze_helper_terminate(ctx
);
2663 mir_analyze_helper_requirements(ctx
);
2666 midgard_schedule_program(ctx
);
2669 /* Now that all the bundles are scheduled and we can calculate block
2670 * sizes, emit actual branch instructions rather than placeholders */
2672 int br_block_idx
= 0;
2674 mir_foreach_block(ctx
, _block
) {
2675 midgard_block
*block
= (midgard_block
*) _block
;
2676 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2677 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2678 midgard_instruction
*ins
= bundle
->instructions
[c
];
2680 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2682 /* Parse some basic branch info */
2683 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2684 bool is_conditional
= ins
->branch
.conditional
;
2685 bool is_inverted
= ins
->branch
.invert_conditional
;
2686 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2687 bool is_writeout
= ins
->writeout
;
2689 /* Determine the block we're jumping to */
2690 int target_number
= ins
->branch
.target_block
;
2692 /* Report the destination tag */
2693 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2695 /* Count up the number of quadwords we're
2696 * jumping over = number of quadwords until
2697 * (br_block_idx, target_number) */
2699 int quadword_offset
= 0;
2703 } else if (target_number
> br_block_idx
) {
2706 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2707 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2710 quadword_offset
+= blk
->quadword_count
;
2713 /* Jump backwards */
2715 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2716 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2719 quadword_offset
-= blk
->quadword_count
;
2723 /* Unconditional extended branches (far jumps)
2724 * have issues, so we always use a conditional
2725 * branch, setting the condition to always for
2726 * unconditional. For compact unconditional
2727 * branches, cond isn't used so it doesn't
2728 * matter what we pick. */
2730 midgard_condition cond
=
2731 !is_conditional
? midgard_condition_always
:
2732 is_inverted
? midgard_condition_false
:
2733 midgard_condition_true
;
2735 midgard_jmp_writeout_op op
=
2736 is_discard
? midgard_jmp_writeout_op_discard
:
2737 is_writeout
? midgard_jmp_writeout_op_writeout
:
2738 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2739 midgard_jmp_writeout_op_branch_cond
;
2742 midgard_branch_extended branch
=
2743 midgard_create_branch_extended(
2748 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2749 } else if (is_conditional
|| is_discard
) {
2750 midgard_branch_cond branch
= {
2752 .dest_tag
= dest_tag
,
2753 .offset
= quadword_offset
,
2757 assert(branch
.offset
== quadword_offset
);
2759 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2761 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2763 midgard_branch_uncond branch
= {
2765 .dest_tag
= dest_tag
,
2766 .offset
= quadword_offset
,
2770 assert(branch
.offset
== quadword_offset
);
2772 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2780 /* Emit flat binary from the instruction arrays. Iterate each block in
2781 * sequence. Save instruction boundaries such that lookahead tags can
2782 * be assigned easily */
2784 /* Cache _all_ bundles in source order for lookahead across failed branches */
2786 int bundle_count
= 0;
2787 mir_foreach_block(ctx
, _block
) {
2788 midgard_block
*block
= (midgard_block
*) _block
;
2789 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2791 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2793 mir_foreach_block(ctx
, _block
) {
2794 midgard_block
*block
= (midgard_block
*) _block
;
2795 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2796 source_order_bundles
[bundle_idx
++] = bundle
;
2800 int current_bundle
= 0;
2802 /* Midgard prefetches instruction types, so during emission we
2803 * need to lookahead. Unless this is the last instruction, in
2804 * which we return 1. */
2806 mir_foreach_block(ctx
, _block
) {
2807 midgard_block
*block
= (midgard_block
*) _block
;
2808 mir_foreach_bundle_in_block(block
, bundle
) {
2811 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
2812 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
2814 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2818 /* TODO: Free deeper */
2819 //util_dynarray_fini(&block->instructions);
2822 free(source_order_bundles
);
2824 /* Report the very first tag executed */
2825 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2827 /* Deal with off-by-one related to the fencepost problem */
2828 program
->work_register_count
= ctx
->work_registers
+ 1;
2829 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2831 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2832 program
->tls_size
= ctx
->tls_size
;
2834 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2835 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2837 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2838 unsigned nr_bundles
= 0, nr_ins
= 0;
2840 /* Count instructions and bundles */
2842 mir_foreach_block(ctx
, _block
) {
2843 midgard_block
*block
= (midgard_block
*) _block
;
2844 nr_bundles
+= util_dynarray_num_elements(
2845 &block
->bundles
, midgard_bundle
);
2847 mir_foreach_bundle_in_block(block
, bun
)
2848 nr_ins
+= bun
->instruction_count
;
2851 /* Calculate thread count. There are certain cutoffs by
2852 * register count for thread count */
2854 unsigned nr_registers
= program
->work_register_count
;
2856 unsigned nr_threads
=
2857 (nr_registers
<= 4) ? 4 :
2858 (nr_registers
<= 8) ? 2 :
2863 fprintf(stderr
, "shader%d - %s shader: "
2864 "%u inst, %u bundles, %u quadwords, "
2865 "%u registers, %u threads, %u loops, "
2866 "%u:%u spills:fills\n",
2868 gl_shader_stage_name(ctx
->stage
),
2869 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2870 nr_registers
, nr_threads
,
2872 ctx
->spills
, ctx
->fills
);