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pan/midgard: Sync midgard_block field names with Bifrost
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
44
45 #include "midgard.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
49 #include "helpers.h"
50 #include "compiler.h"
51 #include "midgard_quirks.h"
52
53 #include "disassemble.h"
54
55 static const struct debug_named_value debug_options[] = {
56 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
59 DEBUG_NAMED_VALUE_END
60 };
61
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
63
64 unsigned SHADER_DB_COUNT = 0;
65
66 int midgard_debug = 0;
67
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72 static midgard_block *
73 create_empty_block(compiler_context *ctx)
74 {
75 midgard_block *blk = rzalloc(ctx, midgard_block);
76
77 blk->predecessors = _mesa_set_create(blk,
78 _mesa_hash_pointer,
79 _mesa_key_pointer_equal);
80
81 blk->name = ctx->block_source_count++;
82
83 return blk;
84 }
85
86 static void
87 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
88 {
89 assert(block);
90 assert(successor);
91
92 /* Deduplicate */
93 for (unsigned i = 0; i < block->nr_successors; ++i) {
94 if (block->successors[i] == successor)
95 return;
96 }
97
98 block->successors[block->nr_successors++] = successor;
99 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
100
101 /* Note the predecessor in the other direction */
102 _mesa_set_add(successor->predecessors, block);
103 }
104
105 static void
106 schedule_barrier(compiler_context *ctx)
107 {
108 midgard_block *temp = ctx->after_block;
109 ctx->after_block = create_empty_block(ctx);
110 ctx->block_count++;
111 list_addtail(&ctx->after_block->link, &ctx->blocks);
112 list_inithead(&ctx->after_block->instructions);
113 midgard_block_add_successor(ctx->current_block, ctx->after_block);
114 ctx->current_block = ctx->after_block;
115 ctx->after_block = temp;
116 }
117
118 /* Helpers to generate midgard_instruction's using macro magic, since every
119 * driver seems to do it that way */
120
121 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
122
123 #define M_LOAD_STORE(name, store) \
124 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
125 midgard_instruction i = { \
126 .type = TAG_LOAD_STORE_4, \
127 .mask = 0xF, \
128 .dest = ~0, \
129 .src = { ~0, ~0, ~0, ~0 }, \
130 .swizzle = SWIZZLE_IDENTITY_4, \
131 .load_store = { \
132 .op = midgard_op_##name, \
133 .address = address \
134 } \
135 }; \
136 \
137 if (store) \
138 i.src[0] = ssa; \
139 else \
140 i.dest = ssa; \
141 \
142 return i; \
143 }
144
145 #define M_LOAD(name) M_LOAD_STORE(name, false)
146 #define M_STORE(name) M_LOAD_STORE(name, true)
147
148 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
149 * the corresponding Midgard source */
150
151 static midgard_vector_alu_src
152 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
153 bool half, bool sext)
154 {
155 /* Figure out how many components there are so we can adjust.
156 * Specifically we want to broadcast the last channel so things like
157 * ball2/3 work.
158 */
159
160 if (broadcast_count && src) {
161 uint8_t last_component = src->swizzle[broadcast_count - 1];
162
163 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
164 src->swizzle[c] = last_component;
165 }
166 }
167
168 midgard_vector_alu_src alu_src = {
169 .rep_low = 0,
170 .rep_high = 0,
171 .half = half
172 };
173
174 if (is_int) {
175 alu_src.mod = midgard_int_normal;
176
177 /* Sign/zero-extend if needed */
178
179 if (half) {
180 alu_src.mod = sext ?
181 midgard_int_sign_extend
182 : midgard_int_zero_extend;
183 }
184
185 /* These should have been lowered away */
186 if (src)
187 assert(!(src->abs || src->negate));
188 } else {
189 if (src)
190 alu_src.mod = (src->abs << 0) | (src->negate << 1);
191 }
192
193 return alu_src;
194 }
195
196 /* load/store instructions have both 32-bit and 16-bit variants, depending on
197 * whether we are using vectors composed of highp or mediump. At the moment, we
198 * don't support half-floats -- this requires changes in other parts of the
199 * compiler -- therefore the 16-bit versions are commented out. */
200
201 //M_LOAD(ld_attr_16);
202 M_LOAD(ld_attr_32);
203 //M_LOAD(ld_vary_16);
204 M_LOAD(ld_vary_32);
205 M_LOAD(ld_ubo_int4);
206 M_LOAD(ld_int4);
207 M_STORE(st_int4);
208 M_LOAD(ld_color_buffer_32u);
209 //M_STORE(st_vary_16);
210 M_STORE(st_vary_32);
211 M_LOAD(ld_cubemap_coords);
212 M_LOAD(ld_compute_id);
213
214 static midgard_instruction
215 v_branch(bool conditional, bool invert)
216 {
217 midgard_instruction ins = {
218 .type = TAG_ALU_4,
219 .unit = ALU_ENAB_BRANCH,
220 .compact_branch = true,
221 .branch = {
222 .conditional = conditional,
223 .invert_conditional = invert
224 },
225 .dest = ~0,
226 .src = { ~0, ~0, ~0, ~0 },
227 };
228
229 return ins;
230 }
231
232 static midgard_branch_extended
233 midgard_create_branch_extended( midgard_condition cond,
234 midgard_jmp_writeout_op op,
235 unsigned dest_tag,
236 signed quadword_offset)
237 {
238 /* The condition code is actually a LUT describing a function to
239 * combine multiple condition codes. However, we only support a single
240 * condition code at the moment, so we just duplicate over a bunch of
241 * times. */
242
243 uint16_t duplicated_cond =
244 (cond << 14) |
245 (cond << 12) |
246 (cond << 10) |
247 (cond << 8) |
248 (cond << 6) |
249 (cond << 4) |
250 (cond << 2) |
251 (cond << 0);
252
253 midgard_branch_extended branch = {
254 .op = op,
255 .dest_tag = dest_tag,
256 .offset = quadword_offset,
257 .cond = duplicated_cond
258 };
259
260 return branch;
261 }
262
263 static void
264 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
265 {
266 ins->has_constants = true;
267 memcpy(&ins->constants, constants, 16);
268 }
269
270 static int
271 glsl_type_size(const struct glsl_type *type, bool bindless)
272 {
273 return glsl_count_attribute_slots(type, false);
274 }
275
276 /* Lower fdot2 to a vector multiplication followed by channel addition */
277 static void
278 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
279 {
280 if (alu->op != nir_op_fdot2)
281 return;
282
283 b->cursor = nir_before_instr(&alu->instr);
284
285 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
286 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
287
288 nir_ssa_def *product = nir_fmul(b, src0, src1);
289
290 nir_ssa_def *sum = nir_fadd(b,
291 nir_channel(b, product, 0),
292 nir_channel(b, product, 1));
293
294 /* Replace the fdot2 with this sum */
295 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
296 }
297
298 static bool
299 midgard_nir_lower_fdot2(nir_shader *shader)
300 {
301 bool progress = false;
302
303 nir_foreach_function(function, shader) {
304 if (!function->impl) continue;
305
306 nir_builder _b;
307 nir_builder *b = &_b;
308 nir_builder_init(b, function->impl);
309
310 nir_foreach_block(block, function->impl) {
311 nir_foreach_instr_safe(instr, block) {
312 if (instr->type != nir_instr_type_alu) continue;
313
314 nir_alu_instr *alu = nir_instr_as_alu(instr);
315 midgard_nir_lower_fdot2_body(b, alu);
316
317 progress |= true;
318 }
319 }
320
321 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
322
323 }
324
325 return progress;
326 }
327
328 /* Midgard can't write depth and stencil separately. It has to happen in a
329 * single store operation containing both. Let's add a panfrost specific
330 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
331 * one.
332 */
333 static bool
334 midgard_nir_lower_zs_store(nir_shader *nir)
335 {
336 if (nir->info.stage != MESA_SHADER_FRAGMENT)
337 return false;
338
339 nir_variable *z_var = NULL, *s_var = NULL;
340
341 nir_foreach_variable(var, &nir->outputs) {
342 if (var->data.location == FRAG_RESULT_DEPTH)
343 z_var = var;
344 else if (var->data.location == FRAG_RESULT_STENCIL)
345 s_var = var;
346 }
347
348 if (!z_var && !s_var)
349 return false;
350
351 bool progress = false;
352
353 nir_foreach_function(function, nir) {
354 if (!function->impl) continue;
355
356 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
357
358 nir_foreach_block(block, function->impl) {
359 nir_foreach_instr_safe(instr, block) {
360 if (instr->type != nir_instr_type_intrinsic)
361 continue;
362
363 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
364 if (intr->intrinsic != nir_intrinsic_store_output)
365 continue;
366
367 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
368 assert(!z_store);
369 z_store = intr;
370 last_store = intr;
371 }
372
373 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
374 assert(!s_store);
375 s_store = intr;
376 last_store = intr;
377 }
378 }
379 }
380
381 if (!z_store && !s_store) continue;
382
383 nir_builder b;
384 nir_builder_init(&b, function->impl);
385
386 b.cursor = nir_before_instr(&last_store->instr);
387
388 nir_ssa_def *zs_store_src;
389
390 if (z_store && s_store) {
391 nir_ssa_def *srcs[2] = {
392 nir_ssa_for_src(&b, z_store->src[0], 1),
393 nir_ssa_for_src(&b, s_store->src[0], 1),
394 };
395
396 zs_store_src = nir_vec(&b, srcs, 2);
397 } else {
398 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
399 }
400
401 nir_intrinsic_instr *zs_store;
402
403 zs_store = nir_intrinsic_instr_create(b.shader,
404 nir_intrinsic_store_zs_output_pan);
405 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
406 zs_store->num_components = z_store && s_store ? 2 : 1;
407 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
408
409 /* Replace the Z and S store by a ZS store */
410 nir_builder_instr_insert(&b, &zs_store->instr);
411
412 if (z_store)
413 nir_instr_remove(&z_store->instr);
414
415 if (s_store)
416 nir_instr_remove(&s_store->instr);
417
418 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
419 progress = true;
420 }
421
422 return progress;
423 }
424
425 /* Flushes undefined values to zero */
426
427 static void
428 optimise_nir(nir_shader *nir, unsigned quirks)
429 {
430 bool progress;
431 unsigned lower_flrp =
432 (nir->options->lower_flrp16 ? 16 : 0) |
433 (nir->options->lower_flrp32 ? 32 : 0) |
434 (nir->options->lower_flrp64 ? 64 : 0);
435
436 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
437 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
438
439 nir_lower_tex_options lower_tex_options = {
440 .lower_txs_lod = true,
441 .lower_txp = ~0,
442 .lower_tex_without_implicit_lod =
443 (quirks & MIDGARD_EXPLICIT_LOD),
444
445 /* TODO: we have native gradient.. */
446 .lower_txd = true,
447 };
448
449 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
450
451 /* Must lower fdot2 after tex is lowered */
452 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
453
454 /* T720 is broken. */
455
456 if (quirks & MIDGARD_BROKEN_LOD)
457 NIR_PASS_V(nir, midgard_nir_lod_errata);
458
459 do {
460 progress = false;
461
462 NIR_PASS(progress, nir, nir_lower_var_copies);
463 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
464
465 NIR_PASS(progress, nir, nir_copy_prop);
466 NIR_PASS(progress, nir, nir_opt_remove_phis);
467 NIR_PASS(progress, nir, nir_opt_dce);
468 NIR_PASS(progress, nir, nir_opt_dead_cf);
469 NIR_PASS(progress, nir, nir_opt_cse);
470 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
471 NIR_PASS(progress, nir, nir_opt_algebraic);
472 NIR_PASS(progress, nir, nir_opt_constant_folding);
473
474 if (lower_flrp != 0) {
475 bool lower_flrp_progress = false;
476 NIR_PASS(lower_flrp_progress,
477 nir,
478 nir_lower_flrp,
479 lower_flrp,
480 false /* always_precise */,
481 nir->options->lower_ffma);
482 if (lower_flrp_progress) {
483 NIR_PASS(progress, nir,
484 nir_opt_constant_folding);
485 progress = true;
486 }
487
488 /* Nothing should rematerialize any flrps, so we only
489 * need to do this lowering once.
490 */
491 lower_flrp = 0;
492 }
493
494 NIR_PASS(progress, nir, nir_opt_undef);
495 NIR_PASS(progress, nir, nir_undef_to_zero);
496
497 NIR_PASS(progress, nir, nir_opt_loop_unroll,
498 nir_var_shader_in |
499 nir_var_shader_out |
500 nir_var_function_temp);
501
502 NIR_PASS(progress, nir, nir_opt_vectorize);
503 } while (progress);
504
505 /* Must be run at the end to prevent creation of fsin/fcos ops */
506 NIR_PASS(progress, nir, midgard_nir_scale_trig);
507
508 do {
509 progress = false;
510
511 NIR_PASS(progress, nir, nir_opt_dce);
512 NIR_PASS(progress, nir, nir_opt_algebraic);
513 NIR_PASS(progress, nir, nir_opt_constant_folding);
514 NIR_PASS(progress, nir, nir_copy_prop);
515 } while (progress);
516
517 NIR_PASS(progress, nir, nir_opt_algebraic_late);
518
519 /* We implement booleans as 32-bit 0/~0 */
520 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
521
522 /* Now that booleans are lowered, we can run out late opts */
523 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
524
525 /* Lower mods for float ops only. Integer ops don't support modifiers
526 * (saturate doesn't make sense on integers, neg/abs require dedicated
527 * instructions) */
528
529 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
530 NIR_PASS(progress, nir, nir_copy_prop);
531 NIR_PASS(progress, nir, nir_opt_dce);
532
533 /* Take us out of SSA */
534 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
535 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
536
537 /* We are a vector architecture; write combine where possible */
538 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
539 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
540
541 NIR_PASS(progress, nir, nir_opt_dce);
542 }
543
544 /* Do not actually emit a load; instead, cache the constant for inlining */
545
546 static void
547 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
548 {
549 nir_ssa_def def = instr->def;
550
551 midgard_constants *consts = rzalloc(NULL, midgard_constants);
552
553 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
554
555 #define RAW_CONST_COPY(bits) \
556 nir_const_value_to_array(consts->u##bits, instr->value, \
557 instr->def.num_components, u##bits)
558
559 switch (instr->def.bit_size) {
560 case 64:
561 RAW_CONST_COPY(64);
562 break;
563 case 32:
564 RAW_CONST_COPY(32);
565 break;
566 case 16:
567 RAW_CONST_COPY(16);
568 break;
569 case 8:
570 RAW_CONST_COPY(8);
571 break;
572 default:
573 unreachable("Invalid bit_size for load_const instruction\n");
574 }
575
576 /* Shifted for SSA, +1 for off-by-one */
577 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
578 }
579
580 /* Normally constants are embedded implicitly, but for I/O and such we have to
581 * explicitly emit a move with the constant source */
582
583 static void
584 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
585 {
586 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
587
588 if (constant_value) {
589 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
590 attach_constants(ctx, &ins, constant_value, node + 1);
591 emit_mir_instruction(ctx, ins);
592 }
593 }
594
595 static bool
596 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
597 {
598 unsigned comp = src->swizzle[0];
599
600 for (unsigned c = 1; c < nr_components; ++c) {
601 if (src->swizzle[c] != comp)
602 return true;
603 }
604
605 return false;
606 }
607
608 #define ALU_CASE(nir, _op) \
609 case nir_op_##nir: \
610 op = midgard_alu_op_##_op; \
611 assert(src_bitsize == dst_bitsize); \
612 break;
613
614 #define ALU_CASE_BCAST(nir, _op, count) \
615 case nir_op_##nir: \
616 op = midgard_alu_op_##_op; \
617 broadcast_swizzle = count; \
618 assert(src_bitsize == dst_bitsize); \
619 break;
620 static bool
621 nir_is_fzero_constant(nir_src src)
622 {
623 if (!nir_src_is_const(src))
624 return false;
625
626 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
627 if (nir_src_comp_as_float(src, c) != 0.0)
628 return false;
629 }
630
631 return true;
632 }
633
634 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
635 * special treatment override this anyway. */
636
637 static midgard_reg_mode
638 reg_mode_for_nir(nir_alu_instr *instr)
639 {
640 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
641
642 switch (src_bitsize) {
643 case 8:
644 return midgard_reg_mode_8;
645 case 16:
646 return midgard_reg_mode_16;
647 case 32:
648 return midgard_reg_mode_32;
649 case 64:
650 return midgard_reg_mode_64;
651 default:
652 unreachable("Invalid bit size");
653 }
654 }
655
656 static void
657 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
658 {
659 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
660 * is handled elsewhere */
661
662 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
663 midgard_emit_derivatives(ctx, instr);
664 return;
665 }
666
667 bool is_ssa = instr->dest.dest.is_ssa;
668
669 unsigned dest = nir_dest_index(&instr->dest.dest);
670 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
671 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
672
673 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
674 * supported. A few do not and are commented for now. Also, there are a
675 * number of NIR ops which Midgard does not support and need to be
676 * lowered, also TODO. This switch block emits the opcode and calling
677 * convention of the Midgard instruction; actual packing is done in
678 * emit_alu below */
679
680 unsigned op;
681
682 /* Number of components valid to check for the instruction (the rest
683 * will be forced to the last), or 0 to use as-is. Relevant as
684 * ball-type instructions have a channel count in NIR but are all vec4
685 * in Midgard */
686
687 unsigned broadcast_swizzle = 0;
688
689 /* What register mode should we operate in? */
690 midgard_reg_mode reg_mode =
691 reg_mode_for_nir(instr);
692
693 /* Do we need a destination override? Used for inline
694 * type conversion */
695
696 midgard_dest_override dest_override =
697 midgard_dest_override_none;
698
699 /* Should we use a smaller respective source and sign-extend? */
700
701 bool half_1 = false, sext_1 = false;
702 bool half_2 = false, sext_2 = false;
703
704 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
705 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
706
707 switch (instr->op) {
708 ALU_CASE(fadd, fadd);
709 ALU_CASE(fmul, fmul);
710 ALU_CASE(fmin, fmin);
711 ALU_CASE(fmax, fmax);
712 ALU_CASE(imin, imin);
713 ALU_CASE(imax, imax);
714 ALU_CASE(umin, umin);
715 ALU_CASE(umax, umax);
716 ALU_CASE(ffloor, ffloor);
717 ALU_CASE(fround_even, froundeven);
718 ALU_CASE(ftrunc, ftrunc);
719 ALU_CASE(fceil, fceil);
720 ALU_CASE(fdot3, fdot3);
721 ALU_CASE(fdot4, fdot4);
722 ALU_CASE(iadd, iadd);
723 ALU_CASE(isub, isub);
724 ALU_CASE(imul, imul);
725
726 /* Zero shoved as second-arg */
727 ALU_CASE(iabs, iabsdiff);
728
729 ALU_CASE(mov, imov);
730
731 ALU_CASE(feq32, feq);
732 ALU_CASE(fne32, fne);
733 ALU_CASE(flt32, flt);
734 ALU_CASE(ieq32, ieq);
735 ALU_CASE(ine32, ine);
736 ALU_CASE(ilt32, ilt);
737 ALU_CASE(ult32, ult);
738
739 /* We don't have a native b2f32 instruction. Instead, like many
740 * GPUs, we exploit booleans as 0/~0 for false/true, and
741 * correspondingly AND
742 * by 1.0 to do the type conversion. For the moment, prime us
743 * to emit:
744 *
745 * iand [whatever], #0
746 *
747 * At the end of emit_alu (as MIR), we'll fix-up the constant
748 */
749
750 ALU_CASE(b2f32, iand);
751 ALU_CASE(b2i32, iand);
752
753 /* Likewise, we don't have a dedicated f2b32 instruction, but
754 * we can do a "not equal to 0.0" test. */
755
756 ALU_CASE(f2b32, fne);
757 ALU_CASE(i2b32, ine);
758
759 ALU_CASE(frcp, frcp);
760 ALU_CASE(frsq, frsqrt);
761 ALU_CASE(fsqrt, fsqrt);
762 ALU_CASE(fexp2, fexp2);
763 ALU_CASE(flog2, flog2);
764
765 ALU_CASE(f2i64, f2i_rtz);
766 ALU_CASE(f2u64, f2u_rtz);
767 ALU_CASE(i2f64, i2f_rtz);
768 ALU_CASE(u2f64, u2f_rtz);
769
770 ALU_CASE(f2i32, f2i_rtz);
771 ALU_CASE(f2u32, f2u_rtz);
772 ALU_CASE(i2f32, i2f_rtz);
773 ALU_CASE(u2f32, u2f_rtz);
774
775 ALU_CASE(f2i16, f2i_rtz);
776 ALU_CASE(f2u16, f2u_rtz);
777 ALU_CASE(i2f16, i2f_rtz);
778 ALU_CASE(u2f16, u2f_rtz);
779
780 ALU_CASE(fsin, fsin);
781 ALU_CASE(fcos, fcos);
782
783 /* We'll set invert */
784 ALU_CASE(inot, imov);
785 ALU_CASE(iand, iand);
786 ALU_CASE(ior, ior);
787 ALU_CASE(ixor, ixor);
788 ALU_CASE(ishl, ishl);
789 ALU_CASE(ishr, iasr);
790 ALU_CASE(ushr, ilsr);
791
792 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
793 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
794 ALU_CASE(b32all_fequal4, fball_eq);
795
796 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
797 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
798 ALU_CASE(b32any_fnequal4, fbany_neq);
799
800 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
801 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
802 ALU_CASE(b32all_iequal4, iball_eq);
803
804 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
805 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
806 ALU_CASE(b32any_inequal4, ibany_neq);
807
808 /* Source mods will be shoved in later */
809 ALU_CASE(fabs, fmov);
810 ALU_CASE(fneg, fmov);
811 ALU_CASE(fsat, fmov);
812
813 /* For size conversion, we use a move. Ideally though we would squash
814 * these ops together; maybe that has to happen after in NIR as part of
815 * propagation...? An earlier algebraic pass ensured we step down by
816 * only / exactly one size. If stepping down, we use a dest override to
817 * reduce the size; if stepping up, we use a larger-sized move with a
818 * half source and a sign/zero-extension modifier */
819
820 case nir_op_i2i8:
821 case nir_op_i2i16:
822 case nir_op_i2i32:
823 case nir_op_i2i64:
824 /* If we end up upscale, we'll need a sign-extend on the
825 * operand (the second argument) */
826
827 sext_2 = true;
828 /* fallthrough */
829 case nir_op_u2u8:
830 case nir_op_u2u16:
831 case nir_op_u2u32:
832 case nir_op_u2u64:
833 case nir_op_f2f16:
834 case nir_op_f2f32:
835 case nir_op_f2f64: {
836 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
837 instr->op == nir_op_f2f64)
838 op = midgard_alu_op_fmov;
839 else
840 op = midgard_alu_op_imov;
841
842 if (dst_bitsize == (src_bitsize * 2)) {
843 /* Converting up */
844 half_2 = true;
845
846 /* Use a greater register mode */
847 reg_mode++;
848 } else if (src_bitsize == (dst_bitsize * 2)) {
849 /* Converting down */
850 dest_override = midgard_dest_override_lower;
851 }
852
853 break;
854 }
855
856 /* For greater-or-equal, we lower to less-or-equal and flip the
857 * arguments */
858
859 case nir_op_fge:
860 case nir_op_fge32:
861 case nir_op_ige32:
862 case nir_op_uge32: {
863 op =
864 instr->op == nir_op_fge ? midgard_alu_op_fle :
865 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
866 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
867 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
868 0;
869
870 /* Swap via temporary */
871 nir_alu_src temp = instr->src[1];
872 instr->src[1] = instr->src[0];
873 instr->src[0] = temp;
874
875 break;
876 }
877
878 case nir_op_b32csel: {
879 /* Midgard features both fcsel and icsel, depending on
880 * the type of the arguments/output. However, as long
881 * as we're careful we can _always_ use icsel and
882 * _never_ need fcsel, since the latter does additional
883 * floating-point-specific processing whereas the
884 * former just moves bits on the wire. It's not obvious
885 * why these are separate opcodes, save for the ability
886 * to do things like sat/pos/abs/neg for free */
887
888 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
889 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
890
891 /* The condition is the first argument; move the other
892 * arguments up one to be a binary instruction for
893 * Midgard with the condition last */
894
895 nir_alu_src temp = instr->src[2];
896
897 instr->src[2] = instr->src[0];
898 instr->src[0] = instr->src[1];
899 instr->src[1] = temp;
900
901 break;
902 }
903
904 default:
905 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
906 assert(0);
907 return;
908 }
909
910 /* Midgard can perform certain modifiers on output of an ALU op */
911 unsigned outmod;
912
913 if (midgard_is_integer_out_op(op)) {
914 outmod = midgard_outmod_int_wrap;
915 } else {
916 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
917 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
918 }
919
920 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
921
922 if (instr->op == nir_op_fmax) {
923 if (nir_is_fzero_constant(instr->src[0].src)) {
924 op = midgard_alu_op_fmov;
925 nr_inputs = 1;
926 outmod = midgard_outmod_pos;
927 instr->src[0] = instr->src[1];
928 } else if (nir_is_fzero_constant(instr->src[1].src)) {
929 op = midgard_alu_op_fmov;
930 nr_inputs = 1;
931 outmod = midgard_outmod_pos;
932 }
933 }
934
935 /* Fetch unit, quirks, etc information */
936 unsigned opcode_props = alu_opcode_props[op].props;
937 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
938
939 /* src0 will always exist afaik, but src1 will not for 1-argument
940 * instructions. The latter can only be fetched if the instruction
941 * needs it, or else we may segfault. */
942
943 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
944 unsigned src1 = nr_inputs >= 2 ? nir_alu_src_index(ctx, &instr->src[1]) : ~0;
945 unsigned src2 = nr_inputs == 3 ? nir_alu_src_index(ctx, &instr->src[2]) : ~0;
946 assert(nr_inputs <= 3);
947
948 /* Rather than use the instruction generation helpers, we do it
949 * ourselves here to avoid the mess */
950
951 midgard_instruction ins = {
952 .type = TAG_ALU_4,
953 .src = {
954 quirk_flipped_r24 ? ~0 : src0,
955 quirk_flipped_r24 ? src0 : src1,
956 src2,
957 ~0
958 },
959 .dest = dest,
960 };
961
962 nir_alu_src *nirmods[3] = { NULL };
963
964 if (nr_inputs >= 2) {
965 nirmods[0] = &instr->src[0];
966 nirmods[1] = &instr->src[1];
967 } else if (nr_inputs == 1) {
968 nirmods[quirk_flipped_r24] = &instr->src[0];
969 } else {
970 assert(0);
971 }
972
973 if (nr_inputs == 3)
974 nirmods[2] = &instr->src[2];
975
976 /* These were lowered to a move, so apply the corresponding mod */
977
978 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
979 nir_alu_src *s = nirmods[quirk_flipped_r24];
980
981 if (instr->op == nir_op_fneg)
982 s->negate = !s->negate;
983
984 if (instr->op == nir_op_fabs)
985 s->abs = !s->abs;
986 }
987
988 bool is_int = midgard_is_integer_op(op);
989
990 ins.mask = mask_of(nr_components);
991
992 midgard_vector_alu alu = {
993 .op = op,
994 .reg_mode = reg_mode,
995 .dest_override = dest_override,
996 .outmod = outmod,
997
998 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
999 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
1000 };
1001
1002 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1003
1004 if (!is_ssa)
1005 ins.mask &= instr->dest.write_mask;
1006
1007 for (unsigned m = 0; m < 3; ++m) {
1008 if (!nirmods[m])
1009 continue;
1010
1011 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
1012 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
1013
1014 /* Replicate. TODO: remove when vec16 lands */
1015 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
1016 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
1017 }
1018
1019 if (nr_inputs == 3) {
1020 /* Conditions can't have mods */
1021 assert(!nirmods[2]->abs);
1022 assert(!nirmods[2]->negate);
1023 }
1024
1025 ins.alu = alu;
1026
1027 /* Late fixup for emulated instructions */
1028
1029 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1030 /* Presently, our second argument is an inline #0 constant.
1031 * Switch over to an embedded 1.0 constant (that can't fit
1032 * inline, since we're 32-bit, not 16-bit like the inline
1033 * constants) */
1034
1035 ins.has_inline_constant = false;
1036 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1037 ins.has_constants = true;
1038
1039 if (instr->op == nir_op_b2f32)
1040 ins.constants.f32[0] = 1.0f;
1041 else
1042 ins.constants.i32[0] = 1;
1043
1044 for (unsigned c = 0; c < 16; ++c)
1045 ins.swizzle[1][c] = 0;
1046 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1047 /* Lots of instructions need a 0 plonked in */
1048 ins.has_inline_constant = false;
1049 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1050 ins.has_constants = true;
1051 ins.constants.u32[0] = 0;
1052
1053 for (unsigned c = 0; c < 16; ++c)
1054 ins.swizzle[1][c] = 0;
1055 } else if (instr->op == nir_op_inot) {
1056 ins.invert = true;
1057 }
1058
1059 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1060 /* To avoid duplicating the lookup tables (probably), true LUT
1061 * instructions can only operate as if they were scalars. Lower
1062 * them here by changing the component. */
1063
1064 unsigned orig_mask = ins.mask;
1065
1066 for (int i = 0; i < nr_components; ++i) {
1067 /* Mask the associated component, dropping the
1068 * instruction if needed */
1069
1070 ins.mask = 1 << i;
1071 ins.mask &= orig_mask;
1072
1073 if (!ins.mask)
1074 continue;
1075
1076 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1077 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1078
1079 emit_mir_instruction(ctx, ins);
1080 }
1081 } else {
1082 emit_mir_instruction(ctx, ins);
1083 }
1084 }
1085
1086 #undef ALU_CASE
1087
1088 static void
1089 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1090 {
1091 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1092 unsigned nir_mask = 0;
1093 unsigned dsize = 0;
1094
1095 if (is_read) {
1096 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1097 dsize = nir_dest_bit_size(intr->dest);
1098 } else {
1099 nir_mask = nir_intrinsic_write_mask(intr);
1100 dsize = 32;
1101 }
1102
1103 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1104 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1105 mir_set_bytemask(ins, bytemask);
1106
1107 if (dsize == 64)
1108 ins->load_64 = true;
1109 }
1110
1111 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1112 * optimized) versions of UBO #0 */
1113
1114 static midgard_instruction *
1115 emit_ubo_read(
1116 compiler_context *ctx,
1117 nir_instr *instr,
1118 unsigned dest,
1119 unsigned offset,
1120 nir_src *indirect_offset,
1121 unsigned indirect_shift,
1122 unsigned index)
1123 {
1124 /* TODO: half-floats */
1125
1126 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1127 ins.constants.u32[0] = offset;
1128
1129 if (instr->type == nir_instr_type_intrinsic)
1130 mir_set_intr_mask(instr, &ins, true);
1131
1132 if (indirect_offset) {
1133 ins.src[2] = nir_src_index(ctx, indirect_offset);
1134 ins.load_store.arg_2 = (indirect_shift << 5);
1135 } else {
1136 ins.load_store.arg_2 = 0x1E;
1137 }
1138
1139 ins.load_store.arg_1 = index;
1140
1141 return emit_mir_instruction(ctx, ins);
1142 }
1143
1144 /* Globals are like UBOs if you squint. And shared memory is like globals if
1145 * you squint even harder */
1146
1147 static void
1148 emit_global(
1149 compiler_context *ctx,
1150 nir_instr *instr,
1151 bool is_read,
1152 unsigned srcdest,
1153 nir_src *offset,
1154 bool is_shared)
1155 {
1156 /* TODO: types */
1157
1158 midgard_instruction ins;
1159
1160 if (is_read)
1161 ins = m_ld_int4(srcdest, 0);
1162 else
1163 ins = m_st_int4(srcdest, 0);
1164
1165 mir_set_offset(ctx, &ins, offset, is_shared);
1166 mir_set_intr_mask(instr, &ins, is_read);
1167
1168 emit_mir_instruction(ctx, ins);
1169 }
1170
1171 static void
1172 emit_varying_read(
1173 compiler_context *ctx,
1174 unsigned dest, unsigned offset,
1175 unsigned nr_comp, unsigned component,
1176 nir_src *indirect_offset, nir_alu_type type, bool flat)
1177 {
1178 /* XXX: Half-floats? */
1179 /* TODO: swizzle, mask */
1180
1181 midgard_instruction ins = m_ld_vary_32(dest, offset);
1182 ins.mask = mask_of(nr_comp);
1183
1184 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1185 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1186
1187 midgard_varying_parameter p = {
1188 .is_varying = 1,
1189 .interpolation = midgard_interp_default,
1190 .flat = flat,
1191 };
1192
1193 unsigned u;
1194 memcpy(&u, &p, sizeof(p));
1195 ins.load_store.varying_parameters = u;
1196
1197 if (indirect_offset)
1198 ins.src[2] = nir_src_index(ctx, indirect_offset);
1199 else
1200 ins.load_store.arg_2 = 0x1E;
1201
1202 ins.load_store.arg_1 = 0x9E;
1203
1204 /* Use the type appropriate load */
1205 switch (type) {
1206 case nir_type_uint:
1207 case nir_type_bool:
1208 ins.load_store.op = midgard_op_ld_vary_32u;
1209 break;
1210 case nir_type_int:
1211 ins.load_store.op = midgard_op_ld_vary_32i;
1212 break;
1213 case nir_type_float:
1214 ins.load_store.op = midgard_op_ld_vary_32;
1215 break;
1216 default:
1217 unreachable("Attempted to load unknown type");
1218 break;
1219 }
1220
1221 emit_mir_instruction(ctx, ins);
1222 }
1223
1224 static void
1225 emit_attr_read(
1226 compiler_context *ctx,
1227 unsigned dest, unsigned offset,
1228 unsigned nr_comp, nir_alu_type t)
1229 {
1230 midgard_instruction ins = m_ld_attr_32(dest, offset);
1231 ins.load_store.arg_1 = 0x1E;
1232 ins.load_store.arg_2 = 0x1E;
1233 ins.mask = mask_of(nr_comp);
1234
1235 /* Use the type appropriate load */
1236 switch (t) {
1237 case nir_type_uint:
1238 case nir_type_bool:
1239 ins.load_store.op = midgard_op_ld_attr_32u;
1240 break;
1241 case nir_type_int:
1242 ins.load_store.op = midgard_op_ld_attr_32i;
1243 break;
1244 case nir_type_float:
1245 ins.load_store.op = midgard_op_ld_attr_32;
1246 break;
1247 default:
1248 unreachable("Attempted to load unknown type");
1249 break;
1250 }
1251
1252 emit_mir_instruction(ctx, ins);
1253 }
1254
1255 static void
1256 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1257 unsigned nr_components, unsigned offset)
1258 {
1259 nir_dest nir_dest;
1260
1261 /* Figure out which uniform this is */
1262 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1263 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1264
1265 unsigned dest = nir_dest_index(&nir_dest);
1266
1267 /* Sysvals are prefix uniforms */
1268 unsigned uniform = ((uintptr_t) val) - 1;
1269
1270 /* Emit the read itself -- this is never indirect */
1271 midgard_instruction *ins =
1272 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1273
1274 ins->mask = mask_of(nr_components);
1275 }
1276
1277 static unsigned
1278 compute_builtin_arg(nir_op op)
1279 {
1280 switch (op) {
1281 case nir_intrinsic_load_work_group_id:
1282 return 0x14;
1283 case nir_intrinsic_load_local_invocation_id:
1284 return 0x10;
1285 default:
1286 unreachable("Invalid compute paramater loaded");
1287 }
1288 }
1289
1290 static void
1291 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1292 {
1293 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1294
1295 midgard_instruction *br = ctx->writeout_branch[rt];
1296
1297 assert(!br);
1298
1299 emit_explicit_constant(ctx, src, src);
1300
1301 struct midgard_instruction ins =
1302 v_branch(false, false);
1303
1304 ins.writeout = true;
1305
1306 /* Add dependencies */
1307 ins.src[0] = src;
1308 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1309 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1310
1311 /* Emit the branch */
1312 br = emit_mir_instruction(ctx, ins);
1313 schedule_barrier(ctx);
1314 ctx->writeout_branch[rt] = br;
1315
1316 /* Push our current location = current block count - 1 = where we'll
1317 * jump to. Maybe a bit too clever for my own good */
1318
1319 br->branch.target_block = ctx->block_count - 1;
1320 }
1321
1322 static void
1323 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1324 {
1325 unsigned reg = nir_dest_index(&instr->dest);
1326 midgard_instruction ins = m_ld_compute_id(reg, 0);
1327 ins.mask = mask_of(3);
1328 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1329 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1330 emit_mir_instruction(ctx, ins);
1331 }
1332
1333 static unsigned
1334 vertex_builtin_arg(nir_op op)
1335 {
1336 switch (op) {
1337 case nir_intrinsic_load_vertex_id:
1338 return PAN_VERTEX_ID;
1339 case nir_intrinsic_load_instance_id:
1340 return PAN_INSTANCE_ID;
1341 default:
1342 unreachable("Invalid vertex builtin");
1343 }
1344 }
1345
1346 static void
1347 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1348 {
1349 unsigned reg = nir_dest_index(&instr->dest);
1350 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1351 }
1352
1353 static void
1354 emit_control_barrier(compiler_context *ctx)
1355 {
1356 midgard_instruction ins = {
1357 .type = TAG_TEXTURE_4,
1358 .src = { ~0, ~0, ~0, ~0 },
1359 .texture = {
1360 .op = TEXTURE_OP_BARRIER,
1361
1362 /* TODO: optimize */
1363 .barrier_buffer = 1,
1364 .barrier_shared = 1
1365 }
1366 };
1367
1368 emit_mir_instruction(ctx, ins);
1369 }
1370
1371 static const nir_variable *
1372 search_var(struct exec_list *vars, unsigned driver_loc)
1373 {
1374 nir_foreach_variable(var, vars) {
1375 if (var->data.driver_location == driver_loc)
1376 return var;
1377 }
1378
1379 return NULL;
1380 }
1381
1382 static void
1383 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1384 {
1385 unsigned offset = 0, reg;
1386
1387 switch (instr->intrinsic) {
1388 case nir_intrinsic_discard_if:
1389 case nir_intrinsic_discard: {
1390 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1391 struct midgard_instruction discard = v_branch(conditional, false);
1392 discard.branch.target_type = TARGET_DISCARD;
1393
1394 if (conditional)
1395 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1396
1397 emit_mir_instruction(ctx, discard);
1398 schedule_barrier(ctx);
1399
1400 break;
1401 }
1402
1403 case nir_intrinsic_load_uniform:
1404 case nir_intrinsic_load_ubo:
1405 case nir_intrinsic_load_global:
1406 case nir_intrinsic_load_shared:
1407 case nir_intrinsic_load_input:
1408 case nir_intrinsic_load_interpolated_input: {
1409 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1410 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1411 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1412 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1413 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1414 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1415
1416 /* Get the base type of the intrinsic */
1417 /* TODO: Infer type? Does it matter? */
1418 nir_alu_type t =
1419 (is_ubo || is_global || is_shared) ? nir_type_uint :
1420 (is_interp) ? nir_type_float :
1421 nir_intrinsic_type(instr);
1422
1423 t = nir_alu_type_get_base_type(t);
1424
1425 if (!(is_ubo || is_global)) {
1426 offset = nir_intrinsic_base(instr);
1427 }
1428
1429 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1430
1431 nir_src *src_offset = nir_get_io_offset_src(instr);
1432
1433 bool direct = nir_src_is_const(*src_offset);
1434 nir_src *indirect_offset = direct ? NULL : src_offset;
1435
1436 if (direct)
1437 offset += nir_src_as_uint(*src_offset);
1438
1439 /* We may need to apply a fractional offset */
1440 int component = (is_flat || is_interp) ?
1441 nir_intrinsic_component(instr) : 0;
1442 reg = nir_dest_index(&instr->dest);
1443
1444 if (is_uniform && !ctx->is_blend) {
1445 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1446 } else if (is_ubo) {
1447 nir_src index = instr->src[0];
1448
1449 /* TODO: Is indirect block number possible? */
1450 assert(nir_src_is_const(index));
1451
1452 uint32_t uindex = nir_src_as_uint(index) + 1;
1453 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1454 } else if (is_global || is_shared) {
1455 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1456 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1457 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1458 } else if (ctx->is_blend) {
1459 /* For blend shaders, load the input color, which is
1460 * preloaded to r0 */
1461
1462 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1463 emit_mir_instruction(ctx, move);
1464 schedule_barrier(ctx);
1465 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1466 emit_attr_read(ctx, reg, offset, nr_comp, t);
1467 } else {
1468 DBG("Unknown load\n");
1469 assert(0);
1470 }
1471
1472 break;
1473 }
1474
1475 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1476 case nir_intrinsic_load_barycentric_pixel:
1477 case nir_intrinsic_load_barycentric_centroid:
1478 break;
1479
1480 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1481
1482 case nir_intrinsic_load_raw_output_pan:
1483 case nir_intrinsic_load_output_u8_as_fp16_pan:
1484 reg = nir_dest_index(&instr->dest);
1485 assert(ctx->is_blend);
1486
1487 /* T720 and below use different blend opcodes with slightly
1488 * different semantics than T760 and up */
1489
1490 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1491 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1492
1493 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1494 ld.load_store.op = old_blend ?
1495 midgard_op_ld_color_buffer_u8_as_fp16_old :
1496 midgard_op_ld_color_buffer_u8_as_fp16;
1497
1498 if (old_blend) {
1499 ld.load_store.address = 1;
1500 ld.load_store.arg_2 = 0x1E;
1501 }
1502
1503 for (unsigned c = 2; c < 16; ++c)
1504 ld.swizzle[0][c] = 0;
1505 }
1506
1507 emit_mir_instruction(ctx, ld);
1508 break;
1509
1510 case nir_intrinsic_load_blend_const_color_rgba: {
1511 assert(ctx->is_blend);
1512 reg = nir_dest_index(&instr->dest);
1513
1514 /* Blend constants are embedded directly in the shader and
1515 * patched in, so we use some magic routing */
1516
1517 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1518 ins.has_constants = true;
1519 ins.has_blend_constant = true;
1520 emit_mir_instruction(ctx, ins);
1521 break;
1522 }
1523
1524 case nir_intrinsic_store_zs_output_pan: {
1525 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1526 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1527 MIDGARD_ZS_RT);
1528
1529 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1530
1531 if (!nir_intrinsic_component(instr))
1532 br->writeout_depth = true;
1533 if (nir_intrinsic_component(instr) ||
1534 instr->num_components)
1535 br->writeout_stencil = true;
1536 assert(br->writeout_depth | br->writeout_stencil);
1537 break;
1538 }
1539
1540 case nir_intrinsic_store_output:
1541 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1542
1543 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1544
1545 reg = nir_src_index(ctx, &instr->src[0]);
1546
1547 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1548 const nir_variable *var;
1549 enum midgard_rt_id rt;
1550
1551 var = search_var(&ctx->nir->outputs,
1552 nir_intrinsic_base(instr));
1553 assert(var);
1554 if (var->data.location == FRAG_RESULT_COLOR)
1555 rt = MIDGARD_COLOR_RT0;
1556 else if (var->data.location >= FRAG_RESULT_DATA0)
1557 rt = MIDGARD_COLOR_RT0 + var->data.location -
1558 FRAG_RESULT_DATA0;
1559 else
1560 assert(0);
1561
1562 emit_fragment_store(ctx, reg, rt);
1563 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1564 /* We should have been vectorized, though we don't
1565 * currently check that st_vary is emitted only once
1566 * per slot (this is relevant, since there's not a mask
1567 * parameter available on the store [set to 0 by the
1568 * blob]). We do respect the component by adjusting the
1569 * swizzle. If this is a constant source, we'll need to
1570 * emit that explicitly. */
1571
1572 emit_explicit_constant(ctx, reg, reg);
1573
1574 unsigned dst_component = nir_intrinsic_component(instr);
1575 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1576
1577 midgard_instruction st = m_st_vary_32(reg, offset);
1578 st.load_store.arg_1 = 0x9E;
1579 st.load_store.arg_2 = 0x1E;
1580
1581 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1582 case nir_type_uint:
1583 case nir_type_bool:
1584 st.load_store.op = midgard_op_st_vary_32u;
1585 break;
1586 case nir_type_int:
1587 st.load_store.op = midgard_op_st_vary_32i;
1588 break;
1589 case nir_type_float:
1590 st.load_store.op = midgard_op_st_vary_32;
1591 break;
1592 default:
1593 unreachable("Attempted to store unknown type");
1594 break;
1595 }
1596
1597 /* nir_intrinsic_component(store_intr) encodes the
1598 * destination component start. Source component offset
1599 * adjustment is taken care of in
1600 * install_registers_instr(), when offset_swizzle() is
1601 * called.
1602 */
1603 unsigned src_component = COMPONENT_X;
1604
1605 assert(nr_comp > 0);
1606 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1607 st.swizzle[0][i] = src_component;
1608 if (i >= dst_component && i < dst_component + nr_comp - 1)
1609 src_component++;
1610 }
1611
1612 emit_mir_instruction(ctx, st);
1613 } else {
1614 DBG("Unknown store\n");
1615 assert(0);
1616 }
1617
1618 break;
1619
1620 /* Special case of store_output for lowered blend shaders */
1621 case nir_intrinsic_store_raw_output_pan:
1622 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1623 reg = nir_src_index(ctx, &instr->src[0]);
1624
1625 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1626 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1627 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1628 * of:
1629 *
1630 * imov r0.xyzw, r0.xxxx
1631 */
1632
1633 unsigned expanded = make_compiler_temp(ctx);
1634
1635 midgard_instruction splatter = v_mov(reg, expanded);
1636
1637 for (unsigned c = 0; c < 16; ++c)
1638 splatter.swizzle[1][c] = 0;
1639
1640 emit_mir_instruction(ctx, splatter);
1641 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1642 } else
1643 emit_fragment_store(ctx, reg, ctx->blend_rt);
1644
1645 break;
1646
1647 case nir_intrinsic_store_global:
1648 case nir_intrinsic_store_shared:
1649 reg = nir_src_index(ctx, &instr->src[0]);
1650 emit_explicit_constant(ctx, reg, reg);
1651
1652 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1653 break;
1654
1655 case nir_intrinsic_load_ssbo_address:
1656 emit_sysval_read(ctx, &instr->instr, 1, 0);
1657 break;
1658
1659 case nir_intrinsic_get_buffer_size:
1660 emit_sysval_read(ctx, &instr->instr, 1, 8);
1661 break;
1662
1663 case nir_intrinsic_load_viewport_scale:
1664 case nir_intrinsic_load_viewport_offset:
1665 case nir_intrinsic_load_num_work_groups:
1666 case nir_intrinsic_load_sampler_lod_parameters_pan:
1667 emit_sysval_read(ctx, &instr->instr, 3, 0);
1668 break;
1669
1670 case nir_intrinsic_load_work_group_id:
1671 case nir_intrinsic_load_local_invocation_id:
1672 emit_compute_builtin(ctx, instr);
1673 break;
1674
1675 case nir_intrinsic_load_vertex_id:
1676 case nir_intrinsic_load_instance_id:
1677 emit_vertex_builtin(ctx, instr);
1678 break;
1679
1680 case nir_intrinsic_memory_barrier_buffer:
1681 case nir_intrinsic_memory_barrier_shared:
1682 break;
1683
1684 case nir_intrinsic_control_barrier:
1685 schedule_barrier(ctx);
1686 emit_control_barrier(ctx);
1687 schedule_barrier(ctx);
1688 break;
1689
1690 default:
1691 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1692 assert(0);
1693 break;
1694 }
1695 }
1696
1697 static unsigned
1698 midgard_tex_format(enum glsl_sampler_dim dim)
1699 {
1700 switch (dim) {
1701 case GLSL_SAMPLER_DIM_1D:
1702 case GLSL_SAMPLER_DIM_BUF:
1703 return MALI_TEX_1D;
1704
1705 case GLSL_SAMPLER_DIM_2D:
1706 case GLSL_SAMPLER_DIM_EXTERNAL:
1707 case GLSL_SAMPLER_DIM_RECT:
1708 return MALI_TEX_2D;
1709
1710 case GLSL_SAMPLER_DIM_3D:
1711 return MALI_TEX_3D;
1712
1713 case GLSL_SAMPLER_DIM_CUBE:
1714 return MALI_TEX_CUBE;
1715
1716 default:
1717 DBG("Unknown sampler dim type\n");
1718 assert(0);
1719 return 0;
1720 }
1721 }
1722
1723 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1724 * was successful */
1725
1726 static bool
1727 pan_attach_constant_bias(
1728 compiler_context *ctx,
1729 nir_src lod,
1730 midgard_texture_word *word)
1731 {
1732 /* To attach as constant, it has to *be* constant */
1733
1734 if (!nir_src_is_const(lod))
1735 return false;
1736
1737 float f = nir_src_as_float(lod);
1738
1739 /* Break into fixed-point */
1740 signed lod_int = f;
1741 float lod_frac = f - lod_int;
1742
1743 /* Carry over negative fractions */
1744 if (lod_frac < 0.0) {
1745 lod_int--;
1746 lod_frac += 1.0;
1747 }
1748
1749 /* Encode */
1750 word->bias = float_to_ubyte(lod_frac);
1751 word->bias_int = lod_int;
1752
1753 return true;
1754 }
1755
1756 static enum mali_sampler_type
1757 midgard_sampler_type(nir_alu_type t) {
1758 switch (nir_alu_type_get_base_type(t))
1759 {
1760 case nir_type_float:
1761 return MALI_SAMPLER_FLOAT;
1762 case nir_type_int:
1763 return MALI_SAMPLER_SIGNED;
1764 case nir_type_uint:
1765 return MALI_SAMPLER_UNSIGNED;
1766 default:
1767 unreachable("Unknown sampler type");
1768 }
1769 }
1770
1771 static void
1772 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1773 unsigned midgard_texop)
1774 {
1775 /* TODO */
1776 //assert (!instr->sampler);
1777
1778 int texture_index = instr->texture_index;
1779 int sampler_index = texture_index;
1780
1781 /* No helper to build texture words -- we do it all here */
1782 midgard_instruction ins = {
1783 .type = TAG_TEXTURE_4,
1784 .mask = 0xF,
1785 .dest = nir_dest_index(&instr->dest),
1786 .src = { ~0, ~0, ~0, ~0 },
1787 .swizzle = SWIZZLE_IDENTITY_4,
1788 .texture = {
1789 .op = midgard_texop,
1790 .format = midgard_tex_format(instr->sampler_dim),
1791 .texture_handle = texture_index,
1792 .sampler_handle = sampler_index,
1793
1794 /* TODO: half */
1795 .in_reg_full = 1,
1796 .out_full = 1,
1797
1798 .sampler_type = midgard_sampler_type(instr->dest_type),
1799 .shadow = instr->is_shadow,
1800 }
1801 };
1802
1803 /* We may need a temporary for the coordinate */
1804
1805 bool needs_temp_coord =
1806 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1807 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1808 (instr->is_shadow);
1809
1810 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1811
1812 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1813 int index = nir_src_index(ctx, &instr->src[i].src);
1814 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1815
1816 switch (instr->src[i].src_type) {
1817 case nir_tex_src_coord: {
1818 emit_explicit_constant(ctx, index, index);
1819
1820 unsigned coord_mask = mask_of(instr->coord_components);
1821
1822 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1823
1824 if (flip_zw)
1825 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1826
1827 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1828 /* texelFetch is undefined on samplerCube */
1829 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1830
1831 /* For cubemaps, we use a special ld/st op to
1832 * select the face and copy the xy into the
1833 * texture register */
1834
1835 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1836 ld.src[1] = index;
1837 ld.mask = 0x3; /* xy */
1838 ld.load_store.arg_1 = 0x20;
1839 ld.swizzle[1][3] = COMPONENT_X;
1840 emit_mir_instruction(ctx, ld);
1841
1842 /* xyzw -> xyxx */
1843 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1844 ins.swizzle[1][3] = COMPONENT_X;
1845 } else if (needs_temp_coord) {
1846 /* mov coord_temp, coords */
1847 midgard_instruction mov = v_mov(index, coords);
1848 mov.mask = coord_mask;
1849
1850 if (flip_zw)
1851 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1852
1853 emit_mir_instruction(ctx, mov);
1854 } else {
1855 coords = index;
1856 }
1857
1858 ins.src[1] = coords;
1859
1860 /* Texelfetch coordinates uses all four elements
1861 * (xyz/index) regardless of texture dimensionality,
1862 * which means it's necessary to zero the unused
1863 * components to keep everything happy */
1864
1865 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1866 /* mov index.zw, #0, or generalized */
1867 midgard_instruction mov =
1868 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1869 mov.has_constants = true;
1870 mov.mask = coord_mask ^ 0xF;
1871 emit_mir_instruction(ctx, mov);
1872 }
1873
1874 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1875 /* Array component in w but NIR wants it in z,
1876 * but if we have a temp coord we already fixed
1877 * that up */
1878
1879 if (nr_components == 3) {
1880 ins.swizzle[1][2] = COMPONENT_Z;
1881 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1882 } else if (nr_components == 2) {
1883 ins.swizzle[1][2] =
1884 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1885 ins.swizzle[1][3] = COMPONENT_X;
1886 } else
1887 unreachable("Invalid texture 2D components");
1888 }
1889
1890 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1891 /* We zeroed */
1892 ins.swizzle[1][2] = COMPONENT_Z;
1893 ins.swizzle[1][3] = COMPONENT_W;
1894 }
1895
1896 break;
1897 }
1898
1899 case nir_tex_src_bias:
1900 case nir_tex_src_lod: {
1901 /* Try as a constant if we can */
1902
1903 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1904 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1905 break;
1906
1907 ins.texture.lod_register = true;
1908 ins.src[2] = index;
1909
1910 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1911 ins.swizzle[2][c] = COMPONENT_X;
1912
1913 emit_explicit_constant(ctx, index, index);
1914
1915 break;
1916 };
1917
1918 case nir_tex_src_offset: {
1919 ins.texture.offset_register = true;
1920 ins.src[3] = index;
1921
1922 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1923 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1924
1925 emit_explicit_constant(ctx, index, index);
1926 break;
1927 };
1928
1929 case nir_tex_src_comparator: {
1930 unsigned comp = COMPONENT_Z;
1931
1932 /* mov coord_temp.foo, coords */
1933 midgard_instruction mov = v_mov(index, coords);
1934 mov.mask = 1 << comp;
1935
1936 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1937 mov.swizzle[1][i] = COMPONENT_X;
1938
1939 emit_mir_instruction(ctx, mov);
1940 break;
1941 }
1942
1943 default: {
1944 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1945 assert(0);
1946 }
1947 }
1948 }
1949
1950 emit_mir_instruction(ctx, ins);
1951
1952 /* Used for .cont and .last hinting */
1953 ctx->texture_op_count++;
1954 }
1955
1956 static void
1957 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1958 {
1959 switch (instr->op) {
1960 case nir_texop_tex:
1961 case nir_texop_txb:
1962 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1963 break;
1964 case nir_texop_txl:
1965 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1966 break;
1967 case nir_texop_txf:
1968 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1969 break;
1970 case nir_texop_txs:
1971 emit_sysval_read(ctx, &instr->instr, 4, 0);
1972 break;
1973 default: {
1974 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1975 assert(0);
1976 }
1977 }
1978 }
1979
1980 static void
1981 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1982 {
1983 switch (instr->type) {
1984 case nir_jump_break: {
1985 /* Emit a branch out of the loop */
1986 struct midgard_instruction br = v_branch(false, false);
1987 br.branch.target_type = TARGET_BREAK;
1988 br.branch.target_break = ctx->current_loop_depth;
1989 emit_mir_instruction(ctx, br);
1990 break;
1991 }
1992
1993 default:
1994 DBG("Unknown jump type %d\n", instr->type);
1995 break;
1996 }
1997 }
1998
1999 static void
2000 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2001 {
2002 switch (instr->type) {
2003 case nir_instr_type_load_const:
2004 emit_load_const(ctx, nir_instr_as_load_const(instr));
2005 break;
2006
2007 case nir_instr_type_intrinsic:
2008 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2009 break;
2010
2011 case nir_instr_type_alu:
2012 emit_alu(ctx, nir_instr_as_alu(instr));
2013 break;
2014
2015 case nir_instr_type_tex:
2016 emit_tex(ctx, nir_instr_as_tex(instr));
2017 break;
2018
2019 case nir_instr_type_jump:
2020 emit_jump(ctx, nir_instr_as_jump(instr));
2021 break;
2022
2023 case nir_instr_type_ssa_undef:
2024 /* Spurious */
2025 break;
2026
2027 default:
2028 DBG("Unhandled instruction type\n");
2029 break;
2030 }
2031 }
2032
2033
2034 /* ALU instructions can inline or embed constants, which decreases register
2035 * pressure and saves space. */
2036
2037 #define CONDITIONAL_ATTACH(idx) { \
2038 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2039 \
2040 if (entry) { \
2041 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2042 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2043 } \
2044 }
2045
2046 static void
2047 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2048 {
2049 mir_foreach_instr_in_block(block, alu) {
2050 /* Other instructions cannot inline constants */
2051 if (alu->type != TAG_ALU_4) continue;
2052 if (alu->compact_branch) continue;
2053
2054 /* If there is already a constant here, we can do nothing */
2055 if (alu->has_constants) continue;
2056
2057 CONDITIONAL_ATTACH(0);
2058
2059 if (!alu->has_constants) {
2060 CONDITIONAL_ATTACH(1)
2061 } else if (!alu->inline_constant) {
2062 /* Corner case: _two_ vec4 constants, for instance with a
2063 * csel. For this case, we can only use a constant
2064 * register for one, we'll have to emit a move for the
2065 * other. Note, if both arguments are constants, then
2066 * necessarily neither argument depends on the value of
2067 * any particular register. As the destination register
2068 * will be wiped, that means we can spill the constant
2069 * to the destination register.
2070 */
2071
2072 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2073 unsigned scratch = alu->dest;
2074
2075 if (entry) {
2076 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2077 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2078
2079 /* Set the source */
2080 alu->src[1] = scratch;
2081
2082 /* Inject us -before- the last instruction which set r31 */
2083 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2084 }
2085 }
2086 }
2087 }
2088
2089 /* Being a little silly with the names, but returns the op that is the bitwise
2090 * inverse of the op with the argument switched. I.e. (f and g are
2091 * contrapositives):
2092 *
2093 * f(a, b) = ~g(b, a)
2094 *
2095 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2096 *
2097 * f(a, b) = ~g(b, a)
2098 * ~f(a, b) = g(b, a)
2099 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2100 * f(a, b) = h(a, b)
2101 *
2102 * Thus we define this function in pairs.
2103 */
2104
2105 static inline midgard_alu_op
2106 mir_contrapositive(midgard_alu_op op)
2107 {
2108 switch (op) {
2109 case midgard_alu_op_flt:
2110 return midgard_alu_op_fle;
2111 case midgard_alu_op_fle:
2112 return midgard_alu_op_flt;
2113
2114 case midgard_alu_op_ilt:
2115 return midgard_alu_op_ile;
2116 case midgard_alu_op_ile:
2117 return midgard_alu_op_ilt;
2118
2119 default:
2120 unreachable("No known contrapositive");
2121 }
2122 }
2123
2124 /* Midgard supports two types of constants, embedded constants (128-bit) and
2125 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2126 * constants can be demoted to inline constants, for space savings and
2127 * sometimes a performance boost */
2128
2129 static void
2130 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2131 {
2132 mir_foreach_instr_in_block(block, ins) {
2133 if (!ins->has_constants) continue;
2134 if (ins->has_inline_constant) continue;
2135
2136 /* Blend constants must not be inlined by definition */
2137 if (ins->has_blend_constant) continue;
2138
2139 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2140 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2141 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2142
2143 if (!(is_16 || is_32))
2144 continue;
2145
2146 /* src1 cannot be an inline constant due to encoding
2147 * restrictions. So, if possible we try to flip the arguments
2148 * in that case */
2149
2150 int op = ins->alu.op;
2151
2152 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2153 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2154
2155 switch (op) {
2156 /* Conditionals can be inverted */
2157 case midgard_alu_op_flt:
2158 case midgard_alu_op_ilt:
2159 case midgard_alu_op_fle:
2160 case midgard_alu_op_ile:
2161 ins->alu.op = mir_contrapositive(ins->alu.op);
2162 ins->invert = true;
2163 flip = true;
2164 break;
2165
2166 case midgard_alu_op_fcsel:
2167 case midgard_alu_op_icsel:
2168 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2169 default:
2170 break;
2171 }
2172
2173 if (flip)
2174 mir_flip(ins);
2175 }
2176
2177 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2178 /* Extract the source information */
2179
2180 midgard_vector_alu_src *src;
2181 int q = ins->alu.src2;
2182 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2183 src = m;
2184
2185 /* Component is from the swizzle. Take a nonzero component */
2186 assert(ins->mask);
2187 unsigned first_comp = ffs(ins->mask) - 1;
2188 unsigned component = ins->swizzle[1][first_comp];
2189
2190 /* Scale constant appropriately, if we can legally */
2191 uint16_t scaled_constant = 0;
2192
2193 if (is_16) {
2194 scaled_constant = ins->constants.u16[component];
2195 } else if (midgard_is_integer_op(op)) {
2196 scaled_constant = ins->constants.u32[component];
2197
2198 /* Constant overflow after resize */
2199 if (scaled_constant != ins->constants.u32[component])
2200 continue;
2201 } else {
2202 float original = ins->constants.f32[component];
2203 scaled_constant = _mesa_float_to_half(original);
2204
2205 /* Check for loss of precision. If this is
2206 * mediump, we don't care, but for a highp
2207 * shader, we need to pay attention. NIR
2208 * doesn't yet tell us which mode we're in!
2209 * Practically this prevents most constants
2210 * from being inlined, sadly. */
2211
2212 float fp32 = _mesa_half_to_float(scaled_constant);
2213
2214 if (fp32 != original)
2215 continue;
2216 }
2217
2218 /* We don't know how to handle these with a constant */
2219
2220 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2221 DBG("Bailing inline constant...\n");
2222 continue;
2223 }
2224
2225 /* Make sure that the constant is not itself a vector
2226 * by checking if all accessed values are the same. */
2227
2228 const midgard_constants *cons = &ins->constants;
2229 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2230
2231 bool is_vector = false;
2232 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2233
2234 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2235 /* We only care if this component is actually used */
2236 if (!(mask & (1 << c)))
2237 continue;
2238
2239 uint32_t test = is_16 ?
2240 cons->u16[ins->swizzle[1][c]] :
2241 cons->u32[ins->swizzle[1][c]];
2242
2243 if (test != value) {
2244 is_vector = true;
2245 break;
2246 }
2247 }
2248
2249 if (is_vector)
2250 continue;
2251
2252 /* Get rid of the embedded constant */
2253 ins->has_constants = false;
2254 ins->src[1] = ~0;
2255 ins->has_inline_constant = true;
2256 ins->inline_constant = scaled_constant;
2257 }
2258 }
2259 }
2260
2261 /* Dead code elimination for branches at the end of a block - only one branch
2262 * per block is legal semantically */
2263
2264 static void
2265 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2266 {
2267 bool branched = false;
2268
2269 mir_foreach_instr_in_block_safe(block, ins) {
2270 if (!midgard_is_branch_unit(ins->unit)) continue;
2271
2272 if (branched)
2273 mir_remove_instruction(ins);
2274
2275 branched = true;
2276 }
2277 }
2278
2279 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2280 * the move can be propagated away entirely */
2281
2282 static bool
2283 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2284 {
2285 /* Nothing to do */
2286 if (comp == midgard_outmod_none)
2287 return true;
2288
2289 if (*outmod == midgard_outmod_none) {
2290 *outmod = comp;
2291 return true;
2292 }
2293
2294 /* TODO: Compose rules */
2295 return false;
2296 }
2297
2298 static bool
2299 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2300 {
2301 bool progress = false;
2302
2303 mir_foreach_instr_in_block_safe(block, ins) {
2304 if (ins->type != TAG_ALU_4) continue;
2305 if (ins->alu.op != midgard_alu_op_fmov) continue;
2306 if (ins->alu.outmod != midgard_outmod_pos) continue;
2307
2308 /* TODO: Registers? */
2309 unsigned src = ins->src[1];
2310 if (src & IS_REG) continue;
2311
2312 /* There might be a source modifier, too */
2313 if (mir_nontrivial_source2_mod(ins)) continue;
2314
2315 /* Backpropagate the modifier */
2316 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2317 if (v->type != TAG_ALU_4) continue;
2318 if (v->dest != src) continue;
2319
2320 /* Can we even take a float outmod? */
2321 if (midgard_is_integer_out_op(v->alu.op)) continue;
2322
2323 midgard_outmod_float temp = v->alu.outmod;
2324 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2325
2326 /* Throw in the towel.. */
2327 if (!progress) break;
2328
2329 /* Otherwise, transfer the modifier */
2330 v->alu.outmod = temp;
2331 ins->alu.outmod = midgard_outmod_none;
2332
2333 break;
2334 }
2335 }
2336
2337 return progress;
2338 }
2339
2340 static unsigned
2341 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2342 {
2343 /* Loop to ourselves */
2344 midgard_instruction *br = ctx->writeout_branch[rt];
2345 struct midgard_instruction ins = v_branch(false, false);
2346 ins.writeout = true;
2347 ins.writeout_depth = br->writeout_depth;
2348 ins.writeout_stencil = br->writeout_stencil;
2349 ins.branch.target_block = ctx->block_count - 1;
2350 ins.constants.u32[0] = br->constants.u32[0];
2351 emit_mir_instruction(ctx, ins);
2352
2353 ctx->current_block->epilogue = true;
2354 schedule_barrier(ctx);
2355 return ins.branch.target_block;
2356 }
2357
2358 static midgard_block *
2359 emit_block(compiler_context *ctx, nir_block *block)
2360 {
2361 midgard_block *this_block = ctx->after_block;
2362 ctx->after_block = NULL;
2363
2364 if (!this_block)
2365 this_block = create_empty_block(ctx);
2366
2367 list_addtail(&this_block->link, &ctx->blocks);
2368
2369 this_block->scheduled = false;
2370 ++ctx->block_count;
2371
2372 /* Set up current block */
2373 list_inithead(&this_block->instructions);
2374 ctx->current_block = this_block;
2375
2376 nir_foreach_instr(instr, block) {
2377 emit_instr(ctx, instr);
2378 ++ctx->instruction_count;
2379 }
2380
2381 return this_block;
2382 }
2383
2384 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2385
2386 static void
2387 emit_if(struct compiler_context *ctx, nir_if *nif)
2388 {
2389 midgard_block *before_block = ctx->current_block;
2390
2391 /* Speculatively emit the branch, but we can't fill it in until later */
2392 EMIT(branch, true, true);
2393 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2394 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2395
2396 /* Emit the two subblocks. */
2397 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2398 midgard_block *end_then_block = ctx->current_block;
2399
2400 /* Emit a jump from the end of the then block to the end of the else */
2401 EMIT(branch, false, false);
2402 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2403
2404 /* Emit second block, and check if it's empty */
2405
2406 int else_idx = ctx->block_count;
2407 int count_in = ctx->instruction_count;
2408 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2409 midgard_block *end_else_block = ctx->current_block;
2410 int after_else_idx = ctx->block_count;
2411
2412 /* Now that we have the subblocks emitted, fix up the branches */
2413
2414 assert(then_block);
2415 assert(else_block);
2416
2417 if (ctx->instruction_count == count_in) {
2418 /* The else block is empty, so don't emit an exit jump */
2419 mir_remove_instruction(then_exit);
2420 then_branch->branch.target_block = after_else_idx;
2421 } else {
2422 then_branch->branch.target_block = else_idx;
2423 then_exit->branch.target_block = after_else_idx;
2424 }
2425
2426 /* Wire up the successors */
2427
2428 ctx->after_block = create_empty_block(ctx);
2429
2430 midgard_block_add_successor(before_block, then_block);
2431 midgard_block_add_successor(before_block, else_block);
2432
2433 midgard_block_add_successor(end_then_block, ctx->after_block);
2434 midgard_block_add_successor(end_else_block, ctx->after_block);
2435 }
2436
2437 static void
2438 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2439 {
2440 /* Remember where we are */
2441 midgard_block *start_block = ctx->current_block;
2442
2443 /* Allocate a loop number, growing the current inner loop depth */
2444 int loop_idx = ++ctx->current_loop_depth;
2445
2446 /* Get index from before the body so we can loop back later */
2447 int start_idx = ctx->block_count;
2448
2449 /* Emit the body itself */
2450 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2451
2452 /* Branch back to loop back */
2453 struct midgard_instruction br_back = v_branch(false, false);
2454 br_back.branch.target_block = start_idx;
2455 emit_mir_instruction(ctx, br_back);
2456
2457 /* Mark down that branch in the graph. */
2458 midgard_block_add_successor(start_block, loop_block);
2459 midgard_block_add_successor(ctx->current_block, loop_block);
2460
2461 /* Find the index of the block about to follow us (note: we don't add
2462 * one; blocks are 0-indexed so we get a fencepost problem) */
2463 int break_block_idx = ctx->block_count;
2464
2465 /* Fix up the break statements we emitted to point to the right place,
2466 * now that we can allocate a block number for them */
2467 ctx->after_block = create_empty_block(ctx);
2468
2469 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2470 mir_foreach_instr_in_block(block, ins) {
2471 if (ins->type != TAG_ALU_4) continue;
2472 if (!ins->compact_branch) continue;
2473
2474 /* We found a branch -- check the type to see if we need to do anything */
2475 if (ins->branch.target_type != TARGET_BREAK) continue;
2476
2477 /* It's a break! Check if it's our break */
2478 if (ins->branch.target_break != loop_idx) continue;
2479
2480 /* Okay, cool, we're breaking out of this loop.
2481 * Rewrite from a break to a goto */
2482
2483 ins->branch.target_type = TARGET_GOTO;
2484 ins->branch.target_block = break_block_idx;
2485
2486 midgard_block_add_successor(block, ctx->after_block);
2487 }
2488 }
2489
2490 /* Now that we've finished emitting the loop, free up the depth again
2491 * so we play nice with recursion amid nested loops */
2492 --ctx->current_loop_depth;
2493
2494 /* Dump loop stats */
2495 ++ctx->loop_count;
2496 }
2497
2498 static midgard_block *
2499 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2500 {
2501 midgard_block *start_block = NULL;
2502
2503 foreach_list_typed(nir_cf_node, node, node, list) {
2504 switch (node->type) {
2505 case nir_cf_node_block: {
2506 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2507
2508 if (!start_block)
2509 start_block = block;
2510
2511 break;
2512 }
2513
2514 case nir_cf_node_if:
2515 emit_if(ctx, nir_cf_node_as_if(node));
2516 break;
2517
2518 case nir_cf_node_loop:
2519 emit_loop(ctx, nir_cf_node_as_loop(node));
2520 break;
2521
2522 case nir_cf_node_function:
2523 assert(0);
2524 break;
2525 }
2526 }
2527
2528 return start_block;
2529 }
2530
2531 /* Due to lookahead, we need to report the first tag executed in the command
2532 * stream and in branch targets. An initial block might be empty, so iterate
2533 * until we find one that 'works' */
2534
2535 static unsigned
2536 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2537 {
2538 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2539
2540 mir_foreach_block_from(ctx, initial_block, v) {
2541 if (v->quadword_count) {
2542 midgard_bundle *initial_bundle =
2543 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2544
2545 return initial_bundle->tag;
2546 }
2547 }
2548
2549 /* Default to a tag 1 which will break from the shader, in case we jump
2550 * to the exit block (i.e. `return` in a compute shader) */
2551
2552 return 1;
2553 }
2554
2555 static unsigned
2556 pan_format_from_nir_base(nir_alu_type base)
2557 {
2558 switch (base) {
2559 case nir_type_int:
2560 return MALI_FORMAT_SINT;
2561 case nir_type_uint:
2562 case nir_type_bool:
2563 return MALI_FORMAT_UINT;
2564 case nir_type_float:
2565 return MALI_CHANNEL_FLOAT;
2566 default:
2567 unreachable("Invalid base");
2568 }
2569 }
2570
2571 static unsigned
2572 pan_format_from_nir_size(nir_alu_type base, unsigned size)
2573 {
2574 if (base == nir_type_float) {
2575 switch (size) {
2576 case 16: return MALI_FORMAT_SINT;
2577 case 32: return MALI_FORMAT_UNORM;
2578 default:
2579 unreachable("Invalid float size for format");
2580 }
2581 } else {
2582 switch (size) {
2583 case 1:
2584 case 8: return MALI_CHANNEL_8;
2585 case 16: return MALI_CHANNEL_16;
2586 case 32: return MALI_CHANNEL_32;
2587 default:
2588 unreachable("Invalid int size for format");
2589 }
2590 }
2591 }
2592
2593 static enum mali_format
2594 pan_format_from_glsl(const struct glsl_type *type)
2595 {
2596 enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type));
2597 nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
2598
2599 unsigned base = nir_alu_type_get_base_type(t);
2600 unsigned size = nir_alu_type_get_type_size(t);
2601
2602 return pan_format_from_nir_base(base) |
2603 pan_format_from_nir_size(base, size) |
2604 MALI_NR_CHANNELS(4);
2605 }
2606
2607 /* For each fragment writeout instruction, generate a writeout loop to
2608 * associate with it */
2609
2610 static void
2611 mir_add_writeout_loops(compiler_context *ctx)
2612 {
2613 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2614 midgard_instruction *br = ctx->writeout_branch[rt];
2615 if (!br) continue;
2616
2617 unsigned popped = br->branch.target_block;
2618 midgard_block_add_successor(mir_get_block(ctx, popped - 1), ctx->current_block);
2619 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2620
2621 /* If we have more RTs, we'll need to restore back after our
2622 * loop terminates */
2623
2624 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2625 midgard_instruction uncond = v_branch(false, false);
2626 uncond.branch.target_block = popped;
2627 emit_mir_instruction(ctx, uncond);
2628 midgard_block_add_successor(ctx->current_block, mir_get_block(ctx, popped));
2629 schedule_barrier(ctx);
2630 } else {
2631 /* We're last, so we can terminate here */
2632 br->last_writeout = true;
2633 }
2634 }
2635 }
2636
2637 int
2638 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2639 {
2640 struct util_dynarray *compiled = &program->compiled;
2641
2642 midgard_debug = debug_get_option_midgard_debug();
2643
2644 /* TODO: Bound against what? */
2645 compiler_context *ctx = rzalloc(NULL, compiler_context);
2646
2647 ctx->nir = nir;
2648 ctx->stage = nir->info.stage;
2649 ctx->is_blend = is_blend;
2650 ctx->alpha_ref = program->alpha_ref;
2651 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2652 ctx->quirks = midgard_get_quirks(gpu_id);
2653
2654 /* Start off with a safe cutoff, allowing usage of all 16 work
2655 * registers. Later, we'll promote uniform reads to uniform registers
2656 * if we determine it is beneficial to do so */
2657 ctx->uniform_cutoff = 8;
2658
2659 /* Initialize at a global (not block) level hash tables */
2660
2661 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2662 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2663
2664 /* Record the varying mapping for the command stream's bookkeeping */
2665
2666 struct exec_list *varyings =
2667 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2668
2669 unsigned max_varying = 0;
2670 nir_foreach_variable(var, varyings) {
2671 unsigned loc = var->data.driver_location;
2672 unsigned sz = glsl_type_size(var->type, FALSE);
2673
2674 for (int c = 0; c < sz; ++c) {
2675 program->varyings[loc + c] = var->data.location + c;
2676 program->varying_type[loc + c] = pan_format_from_glsl(var->type);
2677 max_varying = MAX2(max_varying, loc + c);
2678 }
2679 }
2680
2681 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2682 * (so we don't accidentally duplicate the epilogue since mesa/st has
2683 * messed with our I/O quite a bit already) */
2684
2685 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2686
2687 if (ctx->stage == MESA_SHADER_VERTEX) {
2688 NIR_PASS_V(nir, nir_lower_viewport_transform);
2689 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2690 }
2691
2692 NIR_PASS_V(nir, nir_lower_var_copies);
2693 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2694 NIR_PASS_V(nir, nir_split_var_copies);
2695 NIR_PASS_V(nir, nir_lower_var_copies);
2696 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2697 NIR_PASS_V(nir, nir_lower_var_copies);
2698 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2699
2700 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2701 NIR_PASS_V(nir, nir_lower_ssbo);
2702 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2703
2704 /* Optimisation passes */
2705
2706 optimise_nir(nir, ctx->quirks);
2707
2708 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2709 nir_print_shader(nir, stdout);
2710 }
2711
2712 /* Assign sysvals and counts, now that we're sure
2713 * (post-optimisation) */
2714
2715 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2716
2717 program->uniform_count = nir->num_uniforms;
2718 program->sysval_count = ctx->sysvals.sysval_count;
2719 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2720
2721 nir_foreach_function(func, nir) {
2722 if (!func->impl)
2723 continue;
2724
2725 list_inithead(&ctx->blocks);
2726 ctx->block_count = 0;
2727 ctx->func = func;
2728
2729 emit_cf_list(ctx, &func->impl->body);
2730 break; /* TODO: Multi-function shaders */
2731 }
2732
2733 util_dynarray_init(compiled, NULL);
2734
2735 /* Per-block lowering before opts */
2736
2737 mir_foreach_block(ctx, block) {
2738 inline_alu_constants(ctx, block);
2739 midgard_opt_promote_fmov(ctx, block);
2740 embedded_to_inline_constant(ctx, block);
2741 }
2742 /* MIR-level optimizations */
2743
2744 bool progress = false;
2745
2746 do {
2747 progress = false;
2748
2749 mir_foreach_block(ctx, block) {
2750 progress |= midgard_opt_pos_propagate(ctx, block);
2751 progress |= midgard_opt_copy_prop(ctx, block);
2752 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2753 progress |= midgard_opt_combine_projection(ctx, block);
2754 progress |= midgard_opt_varying_projection(ctx, block);
2755 progress |= midgard_opt_not_propagate(ctx, block);
2756 progress |= midgard_opt_fuse_src_invert(ctx, block);
2757 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2758 progress |= midgard_opt_csel_invert(ctx, block);
2759 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2760 progress |= midgard_opt_invert_branch(ctx, block);
2761 }
2762 } while (progress);
2763
2764 mir_foreach_block(ctx, block) {
2765 midgard_lower_invert(ctx, block);
2766 midgard_lower_derivatives(ctx, block);
2767 }
2768
2769 /* Nested control-flow can result in dead branches at the end of the
2770 * block. This messes with our analysis and is just dead code, so cull
2771 * them */
2772 mir_foreach_block(ctx, block) {
2773 midgard_opt_cull_dead_branch(ctx, block);
2774 }
2775
2776 /* Ensure we were lowered */
2777 mir_foreach_instr_global(ctx, ins) {
2778 assert(!ins->invert);
2779 }
2780
2781 if (ctx->stage == MESA_SHADER_FRAGMENT)
2782 mir_add_writeout_loops(ctx);
2783
2784 /* Schedule! */
2785 midgard_schedule_program(ctx);
2786 mir_ra(ctx);
2787
2788 /* Now that all the bundles are scheduled and we can calculate block
2789 * sizes, emit actual branch instructions rather than placeholders */
2790
2791 int br_block_idx = 0;
2792
2793 mir_foreach_block(ctx, block) {
2794 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2795 for (int c = 0; c < bundle->instruction_count; ++c) {
2796 midgard_instruction *ins = bundle->instructions[c];
2797
2798 if (!midgard_is_branch_unit(ins->unit)) continue;
2799
2800 /* Parse some basic branch info */
2801 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2802 bool is_conditional = ins->branch.conditional;
2803 bool is_inverted = ins->branch.invert_conditional;
2804 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2805 bool is_writeout = ins->writeout;
2806
2807 /* Determine the block we're jumping to */
2808 int target_number = ins->branch.target_block;
2809
2810 /* Report the destination tag */
2811 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2812
2813 /* Count up the number of quadwords we're
2814 * jumping over = number of quadwords until
2815 * (br_block_idx, target_number) */
2816
2817 int quadword_offset = 0;
2818
2819 if (is_discard) {
2820 /* Ignored */
2821 } else if (target_number > br_block_idx) {
2822 /* Jump forward */
2823
2824 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2825 midgard_block *blk = mir_get_block(ctx, idx);
2826 assert(blk);
2827
2828 quadword_offset += blk->quadword_count;
2829 }
2830 } else {
2831 /* Jump backwards */
2832
2833 for (int idx = br_block_idx; idx >= target_number; --idx) {
2834 midgard_block *blk = mir_get_block(ctx, idx);
2835 assert(blk);
2836
2837 quadword_offset -= blk->quadword_count;
2838 }
2839 }
2840
2841 /* Unconditional extended branches (far jumps)
2842 * have issues, so we always use a conditional
2843 * branch, setting the condition to always for
2844 * unconditional. For compact unconditional
2845 * branches, cond isn't used so it doesn't
2846 * matter what we pick. */
2847
2848 midgard_condition cond =
2849 !is_conditional ? midgard_condition_always :
2850 is_inverted ? midgard_condition_false :
2851 midgard_condition_true;
2852
2853 midgard_jmp_writeout_op op =
2854 is_discard ? midgard_jmp_writeout_op_discard :
2855 is_writeout ? midgard_jmp_writeout_op_writeout :
2856 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2857 midgard_jmp_writeout_op_branch_cond;
2858
2859 if (!is_compact) {
2860 midgard_branch_extended branch =
2861 midgard_create_branch_extended(
2862 cond, op,
2863 dest_tag,
2864 quadword_offset);
2865
2866 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2867 } else if (is_conditional || is_discard) {
2868 midgard_branch_cond branch = {
2869 .op = op,
2870 .dest_tag = dest_tag,
2871 .offset = quadword_offset,
2872 .cond = cond
2873 };
2874
2875 assert(branch.offset == quadword_offset);
2876
2877 memcpy(&ins->br_compact, &branch, sizeof(branch));
2878 } else {
2879 assert(op == midgard_jmp_writeout_op_branch_uncond);
2880
2881 midgard_branch_uncond branch = {
2882 .op = op,
2883 .dest_tag = dest_tag,
2884 .offset = quadword_offset,
2885 .unknown = 1
2886 };
2887
2888 assert(branch.offset == quadword_offset);
2889
2890 memcpy(&ins->br_compact, &branch, sizeof(branch));
2891 }
2892 }
2893 }
2894
2895 ++br_block_idx;
2896 }
2897
2898 /* Emit flat binary from the instruction arrays. Iterate each block in
2899 * sequence. Save instruction boundaries such that lookahead tags can
2900 * be assigned easily */
2901
2902 /* Cache _all_ bundles in source order for lookahead across failed branches */
2903
2904 int bundle_count = 0;
2905 mir_foreach_block(ctx, block) {
2906 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2907 }
2908 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2909 int bundle_idx = 0;
2910 mir_foreach_block(ctx, block) {
2911 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2912 source_order_bundles[bundle_idx++] = bundle;
2913 }
2914 }
2915
2916 int current_bundle = 0;
2917
2918 /* Midgard prefetches instruction types, so during emission we
2919 * need to lookahead. Unless this is the last instruction, in
2920 * which we return 1. */
2921
2922 mir_foreach_block(ctx, block) {
2923 mir_foreach_bundle_in_block(block, bundle) {
2924 int lookahead = 1;
2925
2926 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2927 lookahead = source_order_bundles[current_bundle + 1]->tag;
2928
2929 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2930 ++current_bundle;
2931 }
2932
2933 /* TODO: Free deeper */
2934 //util_dynarray_fini(&block->instructions);
2935 }
2936
2937 free(source_order_bundles);
2938
2939 /* Report the very first tag executed */
2940 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2941
2942 /* Deal with off-by-one related to the fencepost problem */
2943 program->work_register_count = ctx->work_registers + 1;
2944 program->uniform_cutoff = ctx->uniform_cutoff;
2945
2946 program->blend_patch_offset = ctx->blend_constant_offset;
2947 program->tls_size = ctx->tls_size;
2948
2949 if (midgard_debug & MIDGARD_DBG_SHADERS)
2950 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2951
2952 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2953 unsigned nr_bundles = 0, nr_ins = 0;
2954
2955 /* Count instructions and bundles */
2956
2957 mir_foreach_block(ctx, block) {
2958 nr_bundles += util_dynarray_num_elements(
2959 &block->bundles, midgard_bundle);
2960
2961 mir_foreach_bundle_in_block(block, bun)
2962 nr_ins += bun->instruction_count;
2963 }
2964
2965 /* Calculate thread count. There are certain cutoffs by
2966 * register count for thread count */
2967
2968 unsigned nr_registers = program->work_register_count;
2969
2970 unsigned nr_threads =
2971 (nr_registers <= 4) ? 4 :
2972 (nr_registers <= 8) ? 2 :
2973 1;
2974
2975 /* Dump stats */
2976
2977 fprintf(stderr, "shader%d - %s shader: "
2978 "%u inst, %u bundles, %u quadwords, "
2979 "%u registers, %u threads, %u loops, "
2980 "%u:%u spills:fills\n",
2981 SHADER_DB_COUNT++,
2982 gl_shader_stage_name(ctx->stage),
2983 nr_ins, nr_bundles, ctx->quadword_count,
2984 nr_registers, nr_threads,
2985 ctx->loop_count,
2986 ctx->spills, ctx->fills);
2987 }
2988
2989 ralloc_free(ctx);
2990
2991 return 0;
2992 }