src/panfrost/midgard/midgard_emit.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
  28  * use scalar ALU instructions, for functional or performance reasons. To do
  29  * this, we just demote vector ALU payloads to scalar. */
  30
  31 static int
  32 component_from_mask(unsigned mask)
  33 {
  34         for (int c = 0; c < 8; ++c) {
  35                 if (mask & (1 << c))
  36                         return c;
  37         }
  38
  39         assert(0);
  40         return 0;
  41 }
  42
  43 static unsigned
  44 vector_to_scalar_source(unsigned u, bool is_int, bool is_full,
  45                 unsigned masked_component)
  46 {
  47         midgard_vector_alu_src v;
  48         memcpy(&v, &u, sizeof(v));
  49
  50         /* TODO: Integers */
  51
  52         unsigned component = (v.swizzle >> (2*masked_component)) & 3;
  53
  54         midgard_scalar_alu_src s = { 0 };
  55
  56         if (is_full) {
  57                 /* For a 32-bit op, just check the source half flag */
  58                 s.full = !v.half;
  59         } else if (!v.half) {
  60                 /* For a 16-bit op that's not subdivided, never full */
  61                 s.full = false;
  62         } else {
  63                 /* We can't do 8-bit scalar, abort! */
  64                 assert(0);
  65         }
  66
  67         /* Component indexing takes size into account */
  68
  69         if (s.full)
  70                 s.component = component << 1;
  71         else {
  72                 bool upper = false; /* TODO */
  73                 s.component = component + (upper << 2);
  74         }
  75
  76         if (is_int) {
  77                 /* TODO */
  78         } else {
  79                 s.abs = v.mod & MIDGARD_FLOAT_MOD_ABS;
  80                 s.negate = v.mod & MIDGARD_FLOAT_MOD_NEG;
  81         }
  82
  83         unsigned o;
  84         memcpy(&o, &s, sizeof(s));
  85
  86         return o & ((1 << 6) - 1);
  87 }
  88
  89 static midgard_scalar_alu
  90 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
  91 {
  92         bool is_int = midgard_is_integer_op(v.op);
  93         bool is_full = v.reg_mode == midgard_reg_mode_32;
  94         bool is_inline_constant = ins->has_inline_constant;
  95
  96         unsigned comp = component_from_mask(ins->mask);
  97
  98         /* The output component is from the mask */
  99         midgard_scalar_alu s = {
 100                 .op = v.op,
 101                 .src1 = vector_to_scalar_source(v.src1, is_int, is_full, comp),
 102                 .src2 = !is_inline_constant ? vector_to_scalar_source(v.src2, is_int, is_full, comp) : 0,
 103                 .unknown = 0,
 104                 .outmod = v.outmod,
 105                 .output_full = is_full,
 106                 .output_component = comp
 107         };
 108
 109         /* Full components are physically spaced out */
 110         if (is_full) {
 111                 assert(s.output_component < 4);
 112                 s.output_component <<= 1;
 113         }
 114
 115         /* Inline constant is passed along rather than trying to extract it
 116          * from v */
 117
 118         if (ins->has_inline_constant) {
 119                 uint16_t imm = 0;
 120                 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 121                 imm |= (lower_11 >> 9) & 3;
 122                 imm |= (lower_11 >> 6) & 4;
 123                 imm |= (lower_11 >> 2) & 0x38;
 124                 imm |= (lower_11 & 63) << 6;
 125
 126                 s.src2 = imm;
 127         }
 128
 129         return s;
 130 }
 131
 132 static void
 133 emit_alu_bundle(compiler_context *ctx,
 134                 midgard_bundle *bundle,
 135                 struct util_dynarray *emission,
 136                 unsigned lookahead)
 137 {
 138         /* Emit the control word */
 139         util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
 140
 141         /* Next up, emit register words */
 142         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 143                 midgard_instruction *ins = bundle->instructions[i];
 144
 145                 /* Check if this instruction has registers */
 146                 if (ins->compact_branch || ins->prepacked_branch) continue;
 147
 148                 /* Otherwise, just emit the registers */
 149                 uint16_t reg_word = 0;
 150                 memcpy(&reg_word, &ins->registers, sizeof(uint16_t));
 151                 util_dynarray_append(emission, uint16_t, reg_word);
 152         }
 153
 154         /* Now, we emit the body itself */
 155         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 156                 midgard_instruction *ins = bundle->instructions[i];
 157
 158                 /* Where is this body */
 159                 unsigned size = 0;
 160                 void *source = NULL;
 161
 162                 /* In case we demote to a scalar */
 163                 midgard_scalar_alu scalarized;
 164
 165                 if (ins->unit & UNITS_ANY_VECTOR) {
 166                         if (ins->alu.reg_mode == midgard_reg_mode_32)
 167                                 ins->alu.mask = expand_writemask_32(ins->mask);
 168                         else
 169                                 ins->alu.mask = ins->mask;
 170
 171                         size = sizeof(midgard_vector_alu);
 172                         source = &ins->alu;
 173                 } else if (ins->unit == ALU_ENAB_BR_COMPACT) {
 174                         size = sizeof(midgard_branch_cond);
 175                         source = &ins->br_compact;
 176                 } else if (ins->compact_branch) { /* misnomer */
 177                         size = sizeof(midgard_branch_extended);
 178                         source = &ins->branch_extended;
 179                 } else {
 180                         size = sizeof(midgard_scalar_alu);
 181                         scalarized = vector_to_scalar_alu(ins->alu, ins);
 182                         source = &scalarized;
 183                 }
 184
 185                 memcpy(util_dynarray_grow_bytes(emission, 1, size), source, size);
 186         }
 187
 188         /* Emit padding (all zero) */
 189         memset(util_dynarray_grow_bytes(emission, 1, bundle->padding), 0, bundle->padding);
 190
 191         /* Tack on constants */
 192
 193         if (bundle->has_embedded_constants) {
 194                 util_dynarray_append(emission, float, bundle->constants[0]);
 195                 util_dynarray_append(emission, float, bundle->constants[1]);
 196                 util_dynarray_append(emission, float, bundle->constants[2]);
 197                 util_dynarray_append(emission, float, bundle->constants[3]);
 198         }
 199 }
 200
 201 /* After everything is scheduled, emit whole bundles at a time */
 202
 203 void
 204 emit_binary_bundle(compiler_context *ctx,
 205                    midgard_bundle *bundle,
 206                    struct util_dynarray *emission,
 207                    int next_tag)
 208 {
 209         int lookahead = next_tag << 4;
 210
 211         switch (bundle->tag) {
 212         case TAG_ALU_4:
 213         case TAG_ALU_8:
 214         case TAG_ALU_12:
 215         case TAG_ALU_16:
 216                 emit_alu_bundle(ctx, bundle, emission, lookahead);
 217                 break;
 218
 219         case TAG_LOAD_STORE_4: {
 220                 /* One or two composing instructions */
 221
 222                 uint64_t current64, next64 = LDST_NOP;
 223
 224                 /* Copy masks */
 225
 226                 for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 227                         bundle->instructions[i]->load_store.mask =
 228                                 bundle->instructions[i]->mask;
 229                 }
 230
 231                 memcpy(&current64, &bundle->instructions[0]->load_store, sizeof(current64));
 232
 233                 if (bundle->instruction_count == 2)
 234                         memcpy(&next64, &bundle->instructions[1]->load_store, sizeof(next64));
 235
 236                 midgard_load_store instruction = {
 237                         .type = bundle->tag,
 238                         .next_type = next_tag,
 239                         .word1 = current64,
 240                         .word2 = next64
 241                 };
 242
 243                 util_dynarray_append(emission, midgard_load_store, instruction);
 244
 245                 break;
 246         }
 247
 248         case TAG_TEXTURE_4:
 249         case TAG_TEXTURE_4_VTX: {
 250                 /* Texture instructions are easy, since there is no pipelining
 251                  * nor VLIW to worry about. We may need to set .cont/.last
 252                  * flags. */
 253
 254                 midgard_instruction *ins = bundle->instructions[0];
 255
 256                 ins->texture.type = bundle->tag;
 257                 ins->texture.next_type = next_tag;
 258                 ins->texture.mask = ins->mask;
 259
 260                 ctx->texture_op_count--;
 261
 262                 if (mir_op_computes_derivatives(ins->texture.op)) {
 263                         bool continues = ctx->texture_op_count > 0;
 264
 265                         /* Control flow complicates helper invocation
 266                          * lifespans, so for now just keep helper threads
 267                          * around indefinitely with loops. TODO: Proper
 268                          * analysis */
 269                         continues |= ctx->loop_count > 0;
 270
 271                         ins->texture.cont = continues;
 272                         ins->texture.last = !continues;
 273                 } else {
 274                         ins->texture.cont = ins->texture.last = 1;
 275                 }
 276
 277                 util_dynarray_append(emission, midgard_texture_word, ins->texture);
 278                 break;
 279         }
 280
 281         default:
 282                 unreachable("Unknown midgard instruction type\n");
 283         }
 284 }