src/panfrost/midgard/midgard_emit.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 static midgard_int_mod
  28 mir_get_imod(bool shift, nir_alu_type T, bool half, bool scalar)
  29 {
  30         if (!half) {
  31                 assert(!shift);
  32                 /* Sign-extension, really... */
  33                 return scalar ? 0 : midgard_int_normal;
  34         }
  35
  36         if (shift)
  37                 return midgard_int_shift;
  38
  39         if (nir_alu_type_get_base_type(T) == nir_type_int)
  40                 return midgard_int_sign_extend;
  41         else
  42                 return midgard_int_zero_extend;
  43 }
  44
  45 static unsigned
  46 mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
  47 {
  48         bool integer = midgard_is_integer_op(ins->alu.op);
  49         unsigned base_size = (8 << ins->alu.reg_mode);
  50         unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
  51         bool half = (sz == (base_size >> 1));
  52
  53         return integer ?
  54                 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) :
  55                 ((ins->src_abs[i] << 0) |
  56                  ((ins->src_neg[i] << 1)));
  57 }
  58
  59 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
  60  * use scalar ALU instructions, for functional or performance reasons. To do
  61  * this, we just demote vector ALU payloads to scalar. */
  62
  63 static int
  64 component_from_mask(unsigned mask)
  65 {
  66         for (int c = 0; c < 8; ++c) {
  67                 if (mask & (1 << c))
  68                         return c;
  69         }
  70
  71         assert(0);
  72         return 0;
  73 }
  74
  75 static unsigned
  76 mir_pack_scalar_source(unsigned mod, bool is_full, unsigned component)
  77 {
  78         midgard_scalar_alu_src s = {
  79                 .mod = mod,
  80                 .full = is_full,
  81                 .component = component << (is_full ? 1 : 0)
  82         };
  83
  84         unsigned o;
  85         memcpy(&o, &s, sizeof(s));
  86
  87         return o & ((1 << 6) - 1);
  88 }
  89
  90 static midgard_scalar_alu
  91 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
  92 {
  93         bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32;
  94
  95         bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16;
  96         bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16;
  97         unsigned comp = component_from_mask(ins->mask);
  98
  99         unsigned packed_src[2] = {
 100                 mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]),
 101                 mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp])
 102         };
 103
 104         /* The output component is from the mask */
 105         midgard_scalar_alu s = {
 106                 .op = v.op,
 107                 .src1 = packed_src[0],
 108                 .src2 = packed_src[1],
 109                 .unknown = 0,
 110                 .outmod = v.outmod,
 111                 .output_full = is_full,
 112                 .output_component = comp
 113         };
 114
 115         /* Full components are physically spaced out */
 116         if (is_full) {
 117                 assert(s.output_component < 4);
 118                 s.output_component <<= 1;
 119         }
 120
 121         /* Inline constant is passed along rather than trying to extract it
 122          * from v */
 123
 124         if (ins->has_inline_constant) {
 125                 uint16_t imm = 0;
 126                 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 127                 imm |= (lower_11 >> 9) & 3;
 128                 imm |= (lower_11 >> 6) & 4;
 129                 imm |= (lower_11 >> 2) & 0x38;
 130                 imm |= (lower_11 & 63) << 6;
 131
 132                 s.src2 = imm;
 133         }
 134
 135         return s;
 136 }
 137
 138 /* 64-bit swizzles are super easy since there are 2 components of 2 components
 139  * in an 8-bit field ... lots of duplication to go around!
 140  *
 141  * Swizzles of 32-bit vectors accessed from 64-bit instructions are a little
 142  * funny -- pack them *as if* they were native 64-bit, using rep_* flags to
 143  * flag upper. For instance, xy would become 64-bit XY but that's just xyzw
 144  * native. Likewise, zz would become 64-bit XX with rep* so it would be xyxy
 145  * with rep. Pretty nifty, huh? */
 146
 147 static unsigned
 148 mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
 149 {
 150         unsigned packed = 0;
 151
 152         for (unsigned i = 0; i < 2; ++i) {
 153                 assert(swizzle[i] <= max_component);
 154
 155                 unsigned a = (swizzle[i] & 1) ?
 156                         (COMPONENT_W << 2) | COMPONENT_Z :
 157                         (COMPONENT_Y << 2) | COMPONENT_X;
 158
 159                 packed |= a << (i * 4);
 160         }
 161
 162         return packed;
 163 }
 164
 165 static void
 166 mir_pack_mask_alu(midgard_instruction *ins)
 167 {
 168         unsigned effective = ins->mask;
 169
 170         /* If we have a destination override, we need to figure out whether to
 171          * override to the lower or upper half, shifting the effective mask in
 172          * the latter, so AAAA.... becomes AAAA */
 173
 174         unsigned upper_shift = mir_upper_override(ins);
 175
 176         if (upper_shift) {
 177                 effective >>= upper_shift;
 178                 ins->alu.dest_override = midgard_dest_override_upper;
 179         }
 180
 181         if (ins->alu.reg_mode == midgard_reg_mode_32)
 182                 ins->alu.mask = expand_writemask(effective, 4);
 183         else if (ins->alu.reg_mode == midgard_reg_mode_64)
 184                 ins->alu.mask = expand_writemask(effective, 2);
 185         else
 186                 ins->alu.mask = effective;
 187 }
 188
 189 static unsigned
 190 mir_pack_swizzle(unsigned mask, unsigned *swizzle,
 191                 nir_alu_type T, midgard_reg_mode reg_mode,
 192                 bool op_channeled, bool *rep_low, bool *rep_high)
 193 {
 194         unsigned packed = 0;
 195         unsigned sz = nir_alu_type_get_type_size(T);
 196
 197         if (reg_mode == midgard_reg_mode_64) {
 198                 unsigned components = 64 / sz;
 199
 200                 packed = mir_pack_swizzle_64(swizzle, components);
 201
 202                 if (sz == 32) {
 203                         bool lo = swizzle[0] >= COMPONENT_Z;
 204                         bool hi = swizzle[1] >= COMPONENT_Z;
 205
 206                         if (mask & 0x1) {
 207                                 /* We can't mix halves... */
 208                                 if (mask & 2)
 209                                         assert(lo == hi);
 210
 211                                 *rep_low = lo;
 212                         } else {
 213                                 *rep_low = hi;
 214                         }
 215                 } else if (sz < 32) {
 216                         unreachable("Cannot encode 8/16 swizzle in 64-bit");
 217                 }
 218         } else {
 219                 /* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
 220                  * the strategy is to check whether the nibble we're on is
 221                  * upper or lower. We need all components to be on the same
 222                  * "side"; that much is enforced by the ISA and should have
 223                  * been lowered. TODO: 8-bit packing. TODO: vec8 */
 224
 225                 unsigned first = mask ? ffs(mask) - 1 : 0;
 226                 bool upper = swizzle[first] > 3;
 227
 228                 if (upper && mask)
 229                         assert(sz <= 16);
 230
 231                 bool dest_up = !op_channeled && (first >= 4);
 232
 233                 for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
 234                         unsigned v = swizzle[c];
 235
 236                         bool t_upper = v > 3;
 237
 238                         /* Ensure we're doing something sane */
 239
 240                         if (mask & (1 << c)) {
 241                                 assert(t_upper == upper);
 242                                 assert(v <= 7);
 243                         }
 244
 245                         /* Use the non upper part */
 246                         v &= 0x3;
 247
 248                         packed |= v << (2 * (c % 4));
 249                 }
 250
 251
 252                 /* Replicate for now.. should really pick a side for
 253                  * dot products */
 254
 255                 if (reg_mode == midgard_reg_mode_16) {
 256                         *rep_low = !upper;
 257                         *rep_high = upper;
 258                 } else if (reg_mode == midgard_reg_mode_32) {
 259                         *rep_low = upper;
 260                 } else {
 261                         unreachable("Unhandled reg mode");
 262                 }
 263         }
 264
 265         return packed;
 266 }
 267
 268 static void
 269 mir_pack_vector_srcs(midgard_instruction *ins)
 270 {
 271         bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props);
 272
 273         midgard_reg_mode mode = ins->alu.reg_mode;
 274         unsigned base_size = (8 << mode);
 275
 276         for (unsigned i = 0; i < 2; ++i) {
 277                 if (ins->has_inline_constant && (i == 1))
 278                         continue;
 279
 280                 if (ins->src[i] == ~0)
 281                         continue;
 282
 283                 bool rep_lo = false, rep_hi = false;
 284                 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
 285                 bool half = (sz == (base_size >> 1));
 286
 287                 assert((sz == base_size) || half);
 288
 289                 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
 290                                 ins->src_types[i], ins->alu.reg_mode,
 291                                 channeled, &rep_lo, &rep_hi);
 292
 293                 midgard_vector_alu_src pack = {
 294                         .mod = mir_pack_mod(ins, i, false),
 295                         .rep_low = rep_lo,
 296                         .rep_high = rep_hi,
 297                         .half = half,
 298                         .swizzle = swizzle
 299                 };
 300
 301                 unsigned p = vector_alu_srco_unsigned(pack);
 302
 303                 if (i == 0)
 304                         ins->alu.src1 = p;
 305                 else
 306                         ins->alu.src2 = p;
 307         }
 308 }
 309
 310 static void
 311 mir_pack_swizzle_ldst(midgard_instruction *ins)
 312 {
 313         /* TODO: non-32-bit, non-vec4 */
 314         for (unsigned c = 0; c < 4; ++c) {
 315                 unsigned v = ins->swizzle[0][c];
 316
 317                 /* Check vec4 */
 318                 assert(v <= 3);
 319
 320                 ins->load_store.swizzle |= v << (2 * c);
 321         }
 322
 323         /* TODO: arg_1/2 */
 324 }
 325
 326 static void
 327 mir_pack_swizzle_tex(midgard_instruction *ins)
 328 {
 329         for (unsigned i = 0; i < 2; ++i) {
 330                 unsigned packed = 0;
 331
 332                 for (unsigned c = 0; c < 4; ++c) {
 333                         unsigned v = ins->swizzle[i][c];
 334
 335                         /* Check vec4 */
 336                         assert(v <= 3);
 337
 338                         packed |= v << (2 * c);
 339                 }
 340
 341                 if (i == 0)
 342                         ins->texture.swizzle = packed;
 343                 else
 344                         ins->texture.in_reg_swizzle = packed;
 345         }
 346
 347         /* TODO: bias component */
 348 }
 349
 350 /* Load store masks are 4-bits. Load/store ops pack for that. vec4 is the
 351  * natural mask width; vec8 is constrained to be in pairs, vec2 is duplicated. TODO: 8-bit?
 352  */
 353
 354 static void
 355 mir_pack_ldst_mask(midgard_instruction *ins)
 356 {
 357         unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
 358         unsigned packed = ins->mask;
 359
 360         if (sz == 64) {
 361                 packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) |
 362                          ((ins->mask & 0x1) ? (0x2 | 0x1) : 0);
 363         } else if (sz == 16) {
 364                 packed = 0;
 365
 366                 for (unsigned i = 0; i < 4; ++i) {
 367                         /* Make sure we're duplicated */
 368                         bool u = (ins->mask & (1 << (2*i + 0))) != 0;
 369                         bool v = (ins->mask & (1 << (2*i + 1))) != 0;
 370                         assert(u == v);
 371
 372                         packed |= (u << i);
 373                 }
 374         } else {
 375                 assert(sz == 32);
 376         }
 377
 378         ins->load_store.mask = packed;
 379 }
 380
 381 static void
 382 mir_lower_inverts(midgard_instruction *ins)
 383 {
 384         bool inv[3] = {
 385                 ins->src_invert[0],
 386                 ins->src_invert[1],
 387                 ins->src_invert[2]
 388         };
 389
 390         switch (ins->alu.op) {
 391         case midgard_alu_op_iand:
 392                 /* a & ~b = iandnot(a, b) */
 393                 /* ~a & ~b = ~(a | b) = inor(a, b) */
 394
 395                 if (inv[0] && inv[1])
 396                         ins->alu.op = midgard_alu_op_inor;
 397                 else if (inv[1])
 398                         ins->alu.op = midgard_alu_op_iandnot;
 399
 400                 break;
 401         case midgard_alu_op_ior:
 402                 /*  a | ~b = iornot(a, b) */
 403                 /* ~a | ~b = ~(a & b) = inand(a, b) */
 404
 405                 if (inv[0] && inv[1])
 406                         ins->alu.op = midgard_alu_op_inand;
 407                 else if (inv[1])
 408                         ins->alu.op = midgard_alu_op_iornot;
 409
 410                 break;
 411
 412         case midgard_alu_op_ixor:
 413                 /* ~a ^ b = a ^ ~b = ~(a ^ b) = inxor(a, b) */
 414                 /* ~a ^ ~b = a ^ b */
 415
 416                 if (inv[0] ^ inv[1])
 417                         ins->alu.op = midgard_alu_op_inxor;
 418
 419                 break;
 420
 421         default:
 422                 break;
 423         }
 424 }
 425
 426 static void
 427 emit_alu_bundle(compiler_context *ctx,
 428                 midgard_bundle *bundle,
 429                 struct util_dynarray *emission,
 430                 unsigned lookahead)
 431 {
 432         /* Emit the control word */
 433         util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
 434
 435         /* Next up, emit register words */
 436         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 437                 midgard_instruction *ins = bundle->instructions[i];
 438
 439                 /* Check if this instruction has registers */
 440                 if (ins->compact_branch) continue;
 441
 442                 /* Otherwise, just emit the registers */
 443                 uint16_t reg_word = 0;
 444                 memcpy(&reg_word, &ins->registers, sizeof(uint16_t));
 445                 util_dynarray_append(emission, uint16_t, reg_word);
 446         }
 447
 448         /* Now, we emit the body itself */
 449         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 450                 midgard_instruction *ins = bundle->instructions[i];
 451
 452                 /* Where is this body */
 453                 unsigned size = 0;
 454                 void *source = NULL;
 455
 456                 /* In case we demote to a scalar */
 457                 midgard_scalar_alu scalarized;
 458
 459                 if (!ins->compact_branch)
 460                         mir_lower_inverts(ins);
 461
 462                 if (ins->unit & UNITS_ANY_VECTOR) {
 463                         mir_pack_mask_alu(ins);
 464                         mir_pack_vector_srcs(ins);
 465                         size = sizeof(midgard_vector_alu);
 466                         source = &ins->alu;
 467                 } else if (ins->unit == ALU_ENAB_BR_COMPACT) {
 468                         size = sizeof(midgard_branch_cond);
 469                         source = &ins->br_compact;
 470                 } else if (ins->compact_branch) { /* misnomer */
 471                         size = sizeof(midgard_branch_extended);
 472                         source = &ins->branch_extended;
 473                 } else {
 474                         size = sizeof(midgard_scalar_alu);
 475                         scalarized = vector_to_scalar_alu(ins->alu, ins);
 476                         source = &scalarized;
 477                 }
 478
 479                 memcpy(util_dynarray_grow_bytes(emission, size, 1), source, size);
 480         }
 481
 482         /* Emit padding (all zero) */
 483         memset(util_dynarray_grow_bytes(emission, bundle->padding, 1), 0, bundle->padding);
 484
 485         /* Tack on constants */
 486
 487         if (bundle->has_embedded_constants)
 488                 util_dynarray_append(emission, midgard_constants, bundle->constants);
 489 }
 490
 491 /* Shift applied to the immediate used as an offset. Probably this is papering
 492  * over some other semantic distinction else well, but it unifies things in the
 493  * compiler so I don't mind. */
 494
 495 static unsigned
 496 mir_ldst_imm_shift(midgard_load_store_op op)
 497 {
 498         if (OP_IS_UBO_READ(op))
 499                 return 3;
 500         else
 501                 return 1;
 502 }
 503
 504 static enum mali_sampler_type
 505 midgard_sampler_type(nir_alu_type t) {
 506         switch (nir_alu_type_get_base_type(t))
 507         {
 508         case nir_type_float:
 509                 return MALI_SAMPLER_FLOAT;
 510         case nir_type_int:
 511                 return MALI_SAMPLER_SIGNED;
 512         case nir_type_uint:
 513                 return MALI_SAMPLER_UNSIGNED;
 514         default:
 515                 unreachable("Unknown sampler type");
 516         }
 517 }
 518
 519 /* After everything is scheduled, emit whole bundles at a time */
 520
 521 void
 522 emit_binary_bundle(compiler_context *ctx,
 523                    midgard_bundle *bundle,
 524                    struct util_dynarray *emission,
 525                    int next_tag)
 526 {
 527         int lookahead = next_tag << 4;
 528
 529         switch (bundle->tag) {
 530         case TAG_ALU_4:
 531         case TAG_ALU_8:
 532         case TAG_ALU_12:
 533         case TAG_ALU_16:
 534         case TAG_ALU_4 + 4:
 535         case TAG_ALU_8 + 4:
 536         case TAG_ALU_12 + 4:
 537         case TAG_ALU_16 + 4:
 538                 emit_alu_bundle(ctx, bundle, emission, lookahead);
 539                 break;
 540
 541         case TAG_LOAD_STORE_4: {
 542                 /* One or two composing instructions */
 543
 544                 uint64_t current64, next64 = LDST_NOP;
 545
 546                 /* Copy masks */
 547
 548                 for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 549                         mir_pack_ldst_mask(bundle->instructions[i]);
 550
 551                         mir_pack_swizzle_ldst(bundle->instructions[i]);
 552
 553                         /* Apply a constant offset */
 554                         unsigned offset = bundle->instructions[i]->constants.u32[0];
 555
 556                         if (offset) {
 557                                 unsigned shift = mir_ldst_imm_shift(bundle->instructions[i]->load_store.op);
 558                                 unsigned upper_shift = 10 - shift;
 559
 560                                 bundle->instructions[i]->load_store.varying_parameters |= (offset & ((1 << upper_shift) - 1)) << shift;
 561                                 bundle->instructions[i]->load_store.address |= (offset >> upper_shift);
 562                         }
 563                 }
 564
 565                 memcpy(&current64, &bundle->instructions[0]->load_store, sizeof(current64));
 566
 567                 if (bundle->instruction_count == 2)
 568                         memcpy(&next64, &bundle->instructions[1]->load_store, sizeof(next64));
 569
 570                 midgard_load_store instruction = {
 571                         .type = bundle->tag,
 572                         .next_type = next_tag,
 573                         .word1 = current64,
 574                         .word2 = next64
 575                 };
 576
 577                 util_dynarray_append(emission, midgard_load_store, instruction);
 578
 579                 break;
 580         }
 581
 582         case TAG_TEXTURE_4:
 583         case TAG_TEXTURE_4_VTX:
 584         case TAG_TEXTURE_4_BARRIER: {
 585                 /* Texture instructions are easy, since there is no pipelining
 586                  * nor VLIW to worry about. We may need to set .cont/.last
 587                  * flags. */
 588
 589                 midgard_instruction *ins = bundle->instructions[0];
 590
 591                 ins->texture.type = bundle->tag;
 592                 ins->texture.next_type = next_tag;
 593                 ins->texture.mask = ins->mask;
 594                 mir_pack_swizzle_tex(ins);
 595
 596                 unsigned osz = nir_alu_type_get_type_size(ins->dest_type);
 597                 unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]);
 598
 599                 assert(osz == 32 || osz == 16);
 600                 assert(isz == 32 || isz == 16);
 601
 602                 ins->texture.out_full = (osz == 32);
 603                 ins->texture.in_reg_full = (isz == 32);
 604                 ins->texture.sampler_type = midgard_sampler_type(ins->dest_type);
 605
 606                 if (mir_op_computes_derivatives(ctx->stage, ins->texture.op)) {
 607                         ins->texture.cont = !ins->helper_terminate;
 608                         ins->texture.last = ins->helper_terminate || ins->helper_execute;
 609                 } else {
 610                         ins->texture.cont = ins->texture.last = 1;
 611                 }
 612
 613                 util_dynarray_append(emission, midgard_texture_word, ins->texture);
 614                 break;
 615         }
 616
 617         default:
 618                 unreachable("Unknown midgard instruction type\n");
 619         }
 620 }