2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
27 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
28 * use scalar ALU instructions, for functional or performance reasons. To do
29 * this, we just demote vector ALU payloads to scalar. */
32 component_from_mask(unsigned mask
)
34 for (int c
= 0; c
< 8; ++c
) {
44 vector_to_scalar_source(unsigned u
, bool is_int
, bool is_full
,
47 midgard_vector_alu_src v
;
48 memcpy(&v
, &u
, sizeof(v
));
52 midgard_scalar_alu_src s
= { 0 };
55 /* For a 32-bit op, just check the source half flag */
58 /* For a 16-bit op that's not subdivided, never full */
61 /* We can't do 8-bit scalar, abort! */
65 /* Component indexing takes size into account */
68 s
.component
= component
<< 1;
70 s
.component
= component
;
75 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
76 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
80 memcpy(&o
, &s
, sizeof(s
));
82 return o
& ((1 << 6) - 1);
85 static midgard_scalar_alu
86 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
88 bool is_int
= midgard_is_integer_op(v
.op
);
89 bool is_full
= v
.reg_mode
== midgard_reg_mode_32
;
90 bool is_inline_constant
= ins
->has_inline_constant
;
92 unsigned comp
= component_from_mask(ins
->mask
);
94 /* The output component is from the mask */
95 midgard_scalar_alu s
= {
97 .src1
= vector_to_scalar_source(v
.src1
, is_int
, is_full
, ins
->swizzle
[0][comp
]),
98 .src2
= !is_inline_constant
? vector_to_scalar_source(v
.src2
, is_int
, is_full
, ins
->swizzle
[1][comp
]) : 0,
101 .output_full
= is_full
,
102 .output_component
= comp
105 /* Full components are physically spaced out */
107 assert(s
.output_component
< 4);
108 s
.output_component
<<= 1;
111 /* Inline constant is passed along rather than trying to extract it
114 if (ins
->has_inline_constant
) {
116 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
117 imm
|= (lower_11
>> 9) & 3;
118 imm
|= (lower_11
>> 6) & 4;
119 imm
|= (lower_11
>> 2) & 0x38;
120 imm
|= (lower_11
& 63) << 6;
129 mir_pack_swizzle_alu(midgard_instruction
*ins
)
131 midgard_vector_alu_src src
[] = {
132 vector_alu_from_unsigned(ins
->alu
.src1
),
133 vector_alu_from_unsigned(ins
->alu
.src2
)
136 for (unsigned i
= 0; i
< 2; ++i
) {
139 /* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
140 * the strategy is to check whether the nibble we're on is
141 * upper or lower. We need all components to be on the same
142 * "side"; that much is enforced by the ISA and should have
143 * been lowered. TODO: 8-bit/64-bit packing. TODO: vec8 */
145 unsigned first
= ins
->mask
? ffs(ins
->mask
) - 1 : 0;
146 bool upper
= ins
->swizzle
[i
][first
] > 3;
148 if (upper
&& ins
->mask
)
149 assert(mir_srcsize(ins
, i
) <= midgard_reg_mode_16
);
151 for (unsigned c
= 0; c
< 4; ++c
) {
152 unsigned v
= ins
->swizzle
[i
][c
];
154 bool t_upper
= v
> 3;
156 /* Ensure we're doing something sane */
158 if (ins
->mask
& (1 << c
)) {
159 assert(t_upper
== upper
);
163 /* Use the non upper part */
166 packed
|= v
<< (2 * c
);
169 src
[i
].swizzle
= packed
;
170 src
[i
].rep_high
= upper
;
173 ins
->alu
.src1
= vector_alu_srco_unsigned(src
[0]);
175 if (!ins
->has_inline_constant
)
176 ins
->alu
.src2
= vector_alu_srco_unsigned(src
[1]);
180 mir_pack_swizzle_ldst(midgard_instruction
*ins
)
182 /* TODO: non-32-bit, non-vec4 */
183 for (unsigned c
= 0; c
< 4; ++c
) {
184 unsigned v
= ins
->swizzle
[0][c
];
189 ins
->load_store
.swizzle
|= v
<< (2 * c
);
196 mir_pack_swizzle_tex(midgard_instruction
*ins
)
198 for (unsigned i
= 0; i
< 2; ++i
) {
201 for (unsigned c
= 0; c
< 4; ++c
) {
202 unsigned v
= ins
->swizzle
[i
][c
];
207 packed
|= v
<< (2 * c
);
211 ins
->texture
.swizzle
= packed
;
213 ins
->texture
.in_reg_swizzle
= packed
;
216 /* TODO: bias component */
220 emit_alu_bundle(compiler_context
*ctx
,
221 midgard_bundle
*bundle
,
222 struct util_dynarray
*emission
,
225 /* Emit the control word */
226 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
228 /* Next up, emit register words */
229 for (unsigned i
= 0; i
< bundle
->instruction_count
; ++i
) {
230 midgard_instruction
*ins
= bundle
->instructions
[i
];
232 /* Check if this instruction has registers */
233 if (ins
->compact_branch
|| ins
->prepacked_branch
) continue;
235 /* Otherwise, just emit the registers */
236 uint16_t reg_word
= 0;
237 memcpy(®_word
, &ins
->registers
, sizeof(uint16_t));
238 util_dynarray_append(emission
, uint16_t, reg_word
);
241 /* Now, we emit the body itself */
242 for (unsigned i
= 0; i
< bundle
->instruction_count
; ++i
) {
243 midgard_instruction
*ins
= bundle
->instructions
[i
];
245 /* Where is this body */
249 /* In case we demote to a scalar */
250 midgard_scalar_alu scalarized
;
252 if (ins
->unit
& UNITS_ANY_VECTOR
) {
253 if (ins
->alu
.reg_mode
== midgard_reg_mode_32
)
254 ins
->alu
.mask
= expand_writemask_32(ins
->mask
);
256 ins
->alu
.mask
= ins
->mask
;
258 mir_pack_swizzle_alu(ins
);
259 size
= sizeof(midgard_vector_alu
);
261 } else if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
262 size
= sizeof(midgard_branch_cond
);
263 source
= &ins
->br_compact
;
264 } else if (ins
->compact_branch
) { /* misnomer */
265 size
= sizeof(midgard_branch_extended
);
266 source
= &ins
->branch_extended
;
268 size
= sizeof(midgard_scalar_alu
);
269 scalarized
= vector_to_scalar_alu(ins
->alu
, ins
);
270 source
= &scalarized
;
273 memcpy(util_dynarray_grow_bytes(emission
, 1, size
), source
, size
);
276 /* Emit padding (all zero) */
277 memset(util_dynarray_grow_bytes(emission
, 1, bundle
->padding
), 0, bundle
->padding
);
279 /* Tack on constants */
281 if (bundle
->has_embedded_constants
) {
282 util_dynarray_append(emission
, float, bundle
->constants
[0]);
283 util_dynarray_append(emission
, float, bundle
->constants
[1]);
284 util_dynarray_append(emission
, float, bundle
->constants
[2]);
285 util_dynarray_append(emission
, float, bundle
->constants
[3]);
289 /* After everything is scheduled, emit whole bundles at a time */
292 emit_binary_bundle(compiler_context
*ctx
,
293 midgard_bundle
*bundle
,
294 struct util_dynarray
*emission
,
297 int lookahead
= next_tag
<< 4;
299 switch (bundle
->tag
) {
304 emit_alu_bundle(ctx
, bundle
, emission
, lookahead
);
307 case TAG_LOAD_STORE_4
: {
308 /* One or two composing instructions */
310 uint64_t current64
, next64
= LDST_NOP
;
314 for (unsigned i
= 0; i
< bundle
->instruction_count
; ++i
) {
315 bundle
->instructions
[i
]->load_store
.mask
=
316 bundle
->instructions
[i
]->mask
;
318 mir_pack_swizzle_ldst(bundle
->instructions
[i
]);
321 memcpy(¤t64
, &bundle
->instructions
[0]->load_store
, sizeof(current64
));
323 if (bundle
->instruction_count
== 2)
324 memcpy(&next64
, &bundle
->instructions
[1]->load_store
, sizeof(next64
));
326 midgard_load_store instruction
= {
328 .next_type
= next_tag
,
333 util_dynarray_append(emission
, midgard_load_store
, instruction
);
339 case TAG_TEXTURE_4_VTX
: {
340 /* Texture instructions are easy, since there is no pipelining
341 * nor VLIW to worry about. We may need to set .cont/.last
344 midgard_instruction
*ins
= bundle
->instructions
[0];
346 ins
->texture
.type
= bundle
->tag
;
347 ins
->texture
.next_type
= next_tag
;
348 ins
->texture
.mask
= ins
->mask
;
349 mir_pack_swizzle_tex(ins
);
351 ctx
->texture_op_count
--;
353 if (mir_op_computes_derivatives(ins
->texture
.op
)) {
354 bool continues
= ctx
->texture_op_count
> 0;
356 /* Control flow complicates helper invocation
357 * lifespans, so for now just keep helper threads
358 * around indefinitely with loops. TODO: Proper
360 continues
|= ctx
->loop_count
> 0;
362 ins
->texture
.cont
= continues
;
363 ins
->texture
.last
= !continues
;
365 ins
->texture
.cont
= ins
->texture
.last
= 1;
368 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
373 unreachable("Unknown midgard instruction type\n");