src/panfrost/midgard/midgard_opt_dce.c

   1 /*
   2  * Copyright (C) 2018 Alyssa Rosenzweig
   3  * Copyright (C) 2019 Collabora, Ltd.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "compiler.h"
  26
  27 /* Basic dead code elimination on the MIR itself */
  28
  29 bool
  30 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
  31 {
  32         bool progress = false;
  33
  34         mir_foreach_instr_in_block_safe(block, ins) {
  35                 if (ins->type != TAG_ALU_4) continue;
  36                 if (ins->compact_branch) continue;
  37
  38                 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
  39                 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
  40
  41                 mir_remove_instruction(ins);
  42                 progress = true;
  43         }
  44
  45         return progress;
  46 }
  47
  48 /* Removes dead moves, that is, moves with a destination overwritten before
  49  * being read. Normally handled implicitly as part of DCE, but this has to run
  50  * after the out-of-SSA pass */
  51
  52 bool
  53 midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block)
  54 {
  55         bool progress = false;
  56
  57         mir_foreach_instr_in_block_safe(block, ins) {
  58                 if (ins->type != TAG_ALU_4) continue;
  59                 if (ins->compact_branch) continue;
  60                 if (!OP_IS_MOVE(ins->alu.op)) continue;
  61
  62                 /* Check if it's overwritten in this block before being read */
  63                 bool overwritten = false;
  64
  65                 mir_foreach_instr_in_block_from(block, q, mir_next_op(ins)) {
  66                         if (q->compact_branch) continue;
  67
  68                         /* Check if used */
  69                         if (mir_has_arg(q, ins->ssa_args.dest))
  70                                 break;
  71
  72                         /* Check if overwritten */
  73                         if (q->ssa_args.dest == ins->ssa_args.dest) {
  74                                 /* Special case to vec4; component tracking is
  75                                  * harder */
  76
  77                                 overwritten = (q->mask == 0xF);
  78                                 break;
  79                         }
  80                 }
  81
  82                 if (overwritten) {
  83                         mir_remove_instruction(ins);
  84                         progress = true;
  85                 }
  86         }
  87
  88         return progress;
  89 }
  90
  91 /* An even further special case - to be run after RA runs but before
  92  * scheduling, eliminating moves that end up being useless even though they
  93  * appeared meaningful in the SSA. Part #2 of register coalescing. */
  94
  95 void
  96 midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g)
  97 {
  98         mir_foreach_instr_in_block_safe(block, ins) {
  99                 if (ins->type != TAG_ALU_4) continue;
 100                 if (ins->compact_branch) continue;
 101                 if (!OP_IS_MOVE(ins->alu.op)) continue;
 102
 103                 /* Check we're to the same place post-RA */
 104                 unsigned iA = ins->ssa_args.dest;
 105                 unsigned iB = ins->ssa_args.src1;
 106
 107                 if ((iA < 0) || (iB < 0)) continue;
 108
 109                 unsigned A = iA >= SSA_FIXED_MINIMUM ?
 110                         SSA_REG_FROM_FIXED(iA) :
 111                         ra_get_node_reg(g, iA);
 112
 113                 unsigned B = iB >= SSA_FIXED_MINIMUM ?
 114                         SSA_REG_FROM_FIXED(iB) :
 115                         ra_get_node_reg(g, iB);
 116
 117                 if (A != B) continue;
 118                 if (ins->ssa_args.inline_constant) continue;
 119
 120                 /* Check we're in the work zone. TODO: promoted
 121                  * uniforms? */
 122                 if (A >= 16) continue;
 123
 124                 /* Ensure there aren't side effects */
 125                 if (mir_nontrivial_source2_mod(ins)) continue;
 126                 if (mir_nontrivial_outmod(ins)) continue;
 127                 if (ins->mask != 0xF) continue;
 128
 129                 /* We do want to rewrite to keep the graph sane for pipeline
 130                  * register creation (TODO: is this the best approach?) */
 131                 mir_rewrite_index_dst(ctx, ins->ssa_args.src1, ins->ssa_args.dest);
 132
 133                 /* We're good to go */
 134                 mir_remove_instruction(ins);
 135
 136         }
 137
 138 }