src/panfrost/midgard/midgard_print.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include <math.h>
  25
  26 #include "util/bitscan.h"
  27 #include "util/half_float.h"
  28 #include "compiler.h"
  29 #include "helpers.h"
  30 #include "midgard_ops.h"
  31
  32 /* Pretty printer for Midgard IR, for use debugging compiler-internal
  33  * passes like register allocation. The output superficially resembles
  34  * Midgard assembly, with the exception that unit information and such is
  35  * (normally) omitted, and generic indices are usually used instead of
  36  * registers */
  37
  38 static void
  39 mir_print_index(int source)
  40 {
  41         if (source == ~0) {
  42                 printf("_");
  43                 return;
  44         }
  45
  46         if (source >= SSA_FIXED_MINIMUM) {
  47                 /* Specific register */
  48                 int reg = SSA_REG_FROM_FIXED(source);
  49
  50                 /* TODO: Moving threshold */
  51                 if (reg > 16 && reg < 24)
  52                         printf("u%d", 23 - reg);
  53                 else
  54                         printf("r%d", reg);
  55         } else {
  56                 printf("%d", source);
  57         }
  58 }
  59
  60 static const char components[16] = "xyzwefghijklmnop";
  61
  62 static void
  63 mir_print_mask(unsigned mask)
  64 {
  65         printf(".");
  66
  67         for (unsigned i = 0; i < 16; ++i) {
  68                 if (mask & (1 << i))
  69                         putchar(components[i]);
  70         }
  71 }
  72
  73 static void
  74 mir_print_swizzle(unsigned *swizzle)
  75 {
  76         printf(".");
  77
  78         for (unsigned i = 0; i < 16; ++i)
  79                 putchar(components[swizzle[i]]);
  80 }
  81
  82 static const char *
  83 mir_get_unit(unsigned unit)
  84 {
  85         switch (unit) {
  86         case ALU_ENAB_VEC_MUL:
  87                 return "vmul";
  88         case ALU_ENAB_SCAL_ADD:
  89                 return "sadd";
  90         case ALU_ENAB_VEC_ADD:
  91                 return "vadd";
  92         case ALU_ENAB_SCAL_MUL:
  93                 return "smul";
  94         case ALU_ENAB_VEC_LUT:
  95                 return "lut";
  96         case ALU_ENAB_BR_COMPACT:
  97                 return "br";
  98         case ALU_ENAB_BRANCH:
  99                 return "brx";
 100         default:
 101                 return "???";
 102         }
 103 }
 104
 105 void
 106 mir_print_constant_component(FILE *fp, const midgard_constants *consts, unsigned c,
 107                              midgard_reg_mode reg_mode, bool half,
 108                              unsigned mod, midgard_alu_op op)
 109 {
 110         bool is_sint = false, is_uint = false, is_hex = false;
 111         const char *opname = alu_opcode_props[op].name;
 112
 113         /* Add a sentinel name to prevent crashing */
 114         if (!opname)
 115                 opname = "unknown";
 116
 117         if (opname[0] == 'u') {
 118                 /* If the opcode starts with a 'u' we are sure we deal with an
 119                  * unsigned int operation
 120                  */
 121                 is_uint = true;
 122         } else if (opname[0] == 'i') {
 123                 /* Bit ops are easier to follow when the constant is printed in
 124                  * hexadecimal. Other operations starting with a 'i' are
 125                  * considered to operate on signed integers. That might not
 126                  * be true for all of them, but it's good enough for traces.
 127                  */
 128                 if (op >= midgard_alu_op_iand &&
 129                     op <= midgard_alu_op_ibitcount8)
 130                         is_hex = true;
 131                 else
 132                         is_sint = true;
 133         }
 134
 135         if (half)
 136                 reg_mode--;
 137
 138         switch (reg_mode) {
 139         case midgard_reg_mode_64:
 140                 if (is_sint) {
 141                         fprintf(fp, "%"PRIi64, consts->i64[c]);
 142                 } else if (is_uint) {
 143                         fprintf(fp, "%"PRIu64, consts->u64[c]);
 144                 } else if (is_hex) {
 145                         fprintf(fp, "0x%"PRIX64, consts->u64[c]);
 146                 } else {
 147                         double v = consts->f64[c];
 148
 149                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabs(v);
 150                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 151
 152                         printf("%g", v);
 153                 }
 154                 break;
 155
 156         case midgard_reg_mode_32:
 157                 if (is_sint) {
 158                         int64_t v;
 159
 160                         if (half && mod == midgard_int_zero_extend)
 161                                 v = consts->u32[c];
 162                         else if (half && mod == midgard_int_shift)
 163                                 v = (uint64_t)consts->u32[c] << 32;
 164                         else
 165                                 v = consts->i32[c];
 166
 167                         fprintf(fp, "%"PRIi64, v);
 168                 } else if (is_uint || is_hex) {
 169                         uint64_t v;
 170
 171                         if (half && mod == midgard_int_shift)
 172                                 v = (uint64_t)consts->u32[c] << 32;
 173                         else
 174                                 v = consts->u32[c];
 175
 176                         fprintf(fp, is_uint ? "%"PRIu64 : "0x%"PRIX64, v);
 177                 } else {
 178                         float v = consts->f32[c];
 179
 180                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
 181                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 182
 183                         fprintf(fp, "%g", v);
 184                 }
 185                 break;
 186
 187         case midgard_reg_mode_16:
 188                 if (is_sint) {
 189                         int32_t v;
 190
 191                         if (half && mod == midgard_int_zero_extend)
 192                                 v = consts->u16[c];
 193                         else if (half && mod == midgard_int_shift)
 194                                 v = (uint32_t)consts->u16[c] << 16;
 195                         else
 196                                 v = consts->i16[c];
 197
 198                         fprintf(fp, "%d", v);
 199                 } else if (is_uint || is_hex) {
 200                         uint32_t v;
 201
 202                         if (half && mod == midgard_int_shift)
 203                                 v = (uint32_t)consts->u16[c] << 16;
 204                         else
 205                                 v = consts->u16[c];
 206
 207                         fprintf(fp, is_uint ? "%u" : "0x%X", v);
 208                 } else {
 209                         float v = _mesa_half_to_float(consts->f16[c]);
 210
 211                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
 212                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 213
 214                         fprintf(fp, "%g", v);
 215                 }
 216                 break;
 217
 218         case midgard_reg_mode_8:
 219                 unreachable("XXX TODO: sort out how 8-bit constant encoding works");
 220                 break;
 221         }
 222 }
 223
 224 static void
 225 mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
 226 {
 227         unsigned type_size = mir_bytes_for_mode(ins->alu.reg_mode);
 228         midgard_vector_alu_src src;
 229
 230         assert(src_idx <= 1);
 231         if (src_idx == 0)
 232                 src = vector_alu_from_unsigned(ins->alu.src1);
 233         else
 234                 src = vector_alu_from_unsigned(ins->alu.src2);
 235
 236         unsigned *swizzle = ins->swizzle[src_idx];
 237         unsigned comp_mask = effective_writemask(&ins->alu, ins->mask);
 238         unsigned num_comp = util_bitcount(comp_mask);
 239         unsigned max_comp = 16 / type_size;
 240         bool first = true;
 241
 242         printf("#");
 243
 244         if (num_comp > 1)
 245                 printf("vec%d(", num_comp);
 246
 247         for (unsigned comp = 0; comp < max_comp; comp++) {
 248                 if (!(comp_mask & (1 << comp)))
 249                         continue;
 250
 251                 if (first)
 252                         first = false;
 253                 else
 254                         printf(", ");
 255
 256                 mir_print_constant_component(stdout, &ins->constants,
 257                                              swizzle[comp], ins->alu.reg_mode,
 258                                              src.half, src.mod, ins->alu.op);
 259         }
 260
 261         if (num_comp > 1)
 262                 printf(")");
 263 }
 264
 265 void
 266 mir_print_instruction(midgard_instruction *ins)
 267 {
 268         printf("\t");
 269
 270         if (midgard_is_branch_unit(ins->unit)) {
 271                 const char *branch_target_names[] = {
 272                         "goto", "break", "continue", "discard"
 273                 };
 274
 275                 printf("%s.", mir_get_unit(ins->unit));
 276                 if (ins->branch.target_type == TARGET_DISCARD)
 277                         printf("discard.");
 278                 else if (ins->writeout)
 279                         printf("write.");
 280                 else if (ins->unit == ALU_ENAB_BR_COMPACT &&
 281                          !ins->branch.conditional)
 282                         printf("uncond.");
 283                 else
 284                         printf("cond.");
 285
 286                 if (!ins->branch.conditional)
 287                         printf("always");
 288                 else if (ins->branch.invert_conditional)
 289                         printf("false");
 290                 else
 291                         printf("true");
 292
 293                 if (ins->branch.target_type != TARGET_DISCARD)
 294                         printf(" %s -> block(%d)\n",
 295                                branch_target_names[ins->branch.target_type],
 296                                ins->branch.target_block);
 297
 298                 return;
 299         }
 300
 301         switch (ins->type) {
 302         case TAG_ALU_4: {
 303                 midgard_alu_op op = ins->alu.op;
 304                 const char *name = alu_opcode_props[op].name;
 305
 306                 if (ins->unit)
 307                         printf("%s.", mir_get_unit(ins->unit));
 308
 309                 printf("%s", name ? name : "??");
 310                 break;
 311         }
 312
 313         case TAG_LOAD_STORE_4: {
 314                 midgard_load_store_op op = ins->load_store.op;
 315                 const char *name = load_store_opcode_props[op].name;
 316
 317                 assert(name);
 318                 printf("%s", name);
 319                 break;
 320         }
 321
 322         case TAG_TEXTURE_4: {
 323                 printf("texture");
 324                 break;
 325         }
 326
 327         default:
 328                 assert(0);
 329         }
 330
 331         if (ins->invert || (ins->compact_branch && ins->branch.invert_conditional))
 332                 printf(".not");
 333
 334         printf(" ");
 335         mir_print_index(ins->dest);
 336
 337         if (ins->mask != 0xF)
 338                 mir_print_mask(ins->mask);
 339
 340         printf(", ");
 341
 342         unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
 343
 344         if (ins->src[0] == r_constant)
 345                 mir_print_embedded_constant(ins, 0);
 346         else {
 347                 mir_print_index(ins->src[0]);
 348                 mir_print_swizzle(ins->swizzle[0]);
 349         }
 350         printf(", ");
 351
 352         if (ins->has_inline_constant)
 353                 printf("#%d", ins->inline_constant);
 354         else if (ins->src[1] == r_constant)
 355                 mir_print_embedded_constant(ins, 1);
 356         else {
 357                 mir_print_index(ins->src[1]);
 358                 mir_print_swizzle(ins->swizzle[1]);
 359         }
 360
 361         printf(", ");
 362         mir_print_index(ins->src[2]);
 363         mir_print_swizzle(ins->swizzle[2]);
 364
 365         printf(", ");
 366         mir_print_index(ins->src[3]);
 367         mir_print_swizzle(ins->swizzle[3]);
 368
 369         if (ins->no_spill)
 370                 printf(" /* no spill */");
 371
 372         printf("\n");
 373 }
 374
 375 /* Dumps MIR for a block or entire shader respective */
 376
 377 void
 378 mir_print_block(midgard_block *block)
 379 {
 380         printf("block%u: {\n", block->base.name);
 381
 382         if (block->scheduled) {
 383                 mir_foreach_bundle_in_block(block, bundle) {
 384                         for (unsigned i = 0; i < bundle->instruction_count; ++i)
 385                                 mir_print_instruction(bundle->instructions[i]);
 386
 387                         printf("\n");
 388                 }
 389         } else {
 390                 mir_foreach_instr_in_block(block, ins) {
 391                         mir_print_instruction(ins);
 392                 }
 393         }
 394
 395         printf("}");
 396
 397         if (block->base.nr_successors) {
 398                 printf(" -> ");
 399                 for (unsigned i = 0; i < block->base.nr_successors; ++i) {
 400                         printf("block%u%s", block->base.successors[i]->name,
 401                                         (i + 1) != block->base.nr_successors ? ", " : "");
 402                 }
 403         }
 404
 405         printf(" from { ");
 406         mir_foreach_predecessor(block, pred)
 407                 printf("block%u ", pred->base.name);
 408         printf("}");
 409
 410         printf("\n\n");
 411 }
 412
 413 void
 414 mir_print_shader(compiler_context *ctx)
 415 {
 416         mir_foreach_block(ctx, block) {
 417                 mir_print_block((midgard_block *) block);
 418         }
 419 }