src/panfrost/midgard/midgard_print.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include <math.h>
  25
  26 #include "util/bitscan.h"
  27 #include "util/half_float.h"
  28 #include "compiler.h"
  29 #include "helpers.h"
  30 #include "midgard_ops.h"
  31
  32 /* Pretty printer for Midgard IR, for use debugging compiler-internal
  33  * passes like register allocation. The output superficially resembles
  34  * Midgard assembly, with the exception that unit information and such is
  35  * (normally) omitted, and generic indices are usually used instead of
  36  * registers */
  37
  38 static void
  39 mir_print_index(int source)
  40 {
  41         if (source == ~0) {
  42                 printf("_");
  43                 return;
  44         }
  45
  46         if (source >= SSA_FIXED_MINIMUM) {
  47                 /* Specific register */
  48                 int reg = SSA_REG_FROM_FIXED(source);
  49
  50                 /* TODO: Moving threshold */
  51                 if (reg > 16 && reg < 24)
  52                         printf("u%d", 23 - reg);
  53                 else
  54                         printf("r%d", reg);
  55         } else {
  56                 printf("%d", source);
  57         }
  58 }
  59
  60 static const char components[16] = "xyzwefghijklmnop";
  61
  62 static void
  63 mir_print_mask(unsigned mask)
  64 {
  65         printf(".");
  66
  67         for (unsigned i = 0; i < 16; ++i) {
  68                 if (mask & (1 << i))
  69                         putchar(components[i]);
  70         }
  71 }
  72
  73 static void
  74 mir_print_swizzle(unsigned *swizzle, nir_alu_type T)
  75 {
  76         unsigned sz = nir_alu_type_get_type_size(T);
  77         unsigned comps = 128 / sz;
  78
  79         printf(".");
  80
  81         for (unsigned i = 0; i < comps; ++i) {
  82                 unsigned C = swizzle[i];
  83                 assert(C < comps);
  84                 putchar(components[C]);
  85         }
  86 }
  87
  88 static const char *
  89 mir_get_unit(unsigned unit)
  90 {
  91         switch (unit) {
  92         case ALU_ENAB_VEC_MUL:
  93                 return "vmul";
  94         case ALU_ENAB_SCAL_ADD:
  95                 return "sadd";
  96         case ALU_ENAB_VEC_ADD:
  97                 return "vadd";
  98         case ALU_ENAB_SCAL_MUL:
  99                 return "smul";
 100         case ALU_ENAB_VEC_LUT:
 101                 return "lut";
 102         case ALU_ENAB_BR_COMPACT:
 103                 return "br";
 104         case ALU_ENAB_BRANCH:
 105                 return "brx";
 106         default:
 107                 return "???";
 108         }
 109 }
 110
 111 void
 112 mir_print_constant_component(FILE *fp, const midgard_constants *consts, unsigned c,
 113                              midgard_reg_mode reg_mode, bool half,
 114                              unsigned mod, midgard_alu_op op)
 115 {
 116         bool is_sint = false, is_uint = false, is_hex = false;
 117         const char *opname = alu_opcode_props[op].name;
 118
 119         /* Add a sentinel name to prevent crashing */
 120         if (!opname)
 121                 opname = "unknown";
 122
 123         if (opname[0] == 'u') {
 124                 /* If the opcode starts with a 'u' we are sure we deal with an
 125                  * unsigned int operation
 126                  */
 127                 is_uint = true;
 128         } else if (opname[0] == 'i') {
 129                 /* Bit ops are easier to follow when the constant is printed in
 130                  * hexadecimal. Other operations starting with a 'i' are
 131                  * considered to operate on signed integers. That might not
 132                  * be true for all of them, but it's good enough for traces.
 133                  */
 134                 if (op >= midgard_alu_op_iand &&
 135                     op <= midgard_alu_op_ibitcount8)
 136                         is_hex = true;
 137                 else
 138                         is_sint = true;
 139         }
 140
 141         if (half)
 142                 reg_mode--;
 143
 144         switch (reg_mode) {
 145         case midgard_reg_mode_64:
 146                 if (is_sint) {
 147                         fprintf(fp, "%"PRIi64, consts->i64[c]);
 148                 } else if (is_uint) {
 149                         fprintf(fp, "%"PRIu64, consts->u64[c]);
 150                 } else if (is_hex) {
 151                         fprintf(fp, "0x%"PRIX64, consts->u64[c]);
 152                 } else {
 153                         double v = consts->f64[c];
 154
 155                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabs(v);
 156                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 157
 158                         printf("%g", v);
 159                 }
 160                 break;
 161
 162         case midgard_reg_mode_32:
 163                 if (is_sint) {
 164                         int64_t v;
 165
 166                         if (half && mod == midgard_int_zero_extend)
 167                                 v = consts->u32[c];
 168                         else if (half && mod == midgard_int_shift)
 169                                 v = (uint64_t)consts->u32[c] << 32;
 170                         else
 171                                 v = consts->i32[c];
 172
 173                         fprintf(fp, "%"PRIi64, v);
 174                 } else if (is_uint || is_hex) {
 175                         uint64_t v;
 176
 177                         if (half && mod == midgard_int_shift)
 178                                 v = (uint64_t)consts->u32[c] << 32;
 179                         else
 180                                 v = consts->u32[c];
 181
 182                         fprintf(fp, is_uint ? "%"PRIu64 : "0x%"PRIX64, v);
 183                 } else {
 184                         float v = consts->f32[c];
 185
 186                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
 187                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 188
 189                         fprintf(fp, "%g", v);
 190                 }
 191                 break;
 192
 193         case midgard_reg_mode_16:
 194                 if (is_sint) {
 195                         int32_t v;
 196
 197                         if (half && mod == midgard_int_zero_extend)
 198                                 v = consts->u16[c];
 199                         else if (half && mod == midgard_int_shift)
 200                                 v = (uint32_t)consts->u16[c] << 16;
 201                         else
 202                                 v = consts->i16[c];
 203
 204                         fprintf(fp, "%d", v);
 205                 } else if (is_uint || is_hex) {
 206                         uint32_t v;
 207
 208                         if (half && mod == midgard_int_shift)
 209                                 v = (uint32_t)consts->u16[c] << 16;
 210                         else
 211                                 v = consts->u16[c];
 212
 213                         fprintf(fp, is_uint ? "%u" : "0x%X", v);
 214                 } else {
 215                         float v = _mesa_half_to_float(consts->f16[c]);
 216
 217                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
 218                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 219
 220                         fprintf(fp, "%g", v);
 221                 }
 222                 break;
 223
 224         case midgard_reg_mode_8:
 225                 unreachable("XXX TODO: sort out how 8-bit constant encoding works");
 226                 break;
 227         }
 228 }
 229
 230 static void
 231 mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
 232 {
 233         unsigned type_size = mir_bytes_for_mode(ins->alu.reg_mode);
 234         midgard_vector_alu_src src;
 235
 236         assert(src_idx <= 1);
 237         if (src_idx == 0)
 238                 src = vector_alu_from_unsigned(ins->alu.src1);
 239         else
 240                 src = vector_alu_from_unsigned(ins->alu.src2);
 241
 242         unsigned *swizzle = ins->swizzle[src_idx];
 243         unsigned comp_mask = effective_writemask(&ins->alu, ins->mask);
 244         unsigned num_comp = util_bitcount(comp_mask);
 245         unsigned max_comp = 16 / type_size;
 246         bool first = true;
 247
 248         printf("#");
 249
 250         if (num_comp > 1)
 251                 printf("vec%d(", num_comp);
 252
 253         for (unsigned comp = 0; comp < max_comp; comp++) {
 254                 if (!(comp_mask & (1 << comp)))
 255                         continue;
 256
 257                 if (first)
 258                         first = false;
 259                 else
 260                         printf(", ");
 261
 262                 mir_print_constant_component(stdout, &ins->constants,
 263                                              swizzle[comp], ins->alu.reg_mode,
 264                                              src.half, src.mod, ins->alu.op);
 265         }
 266
 267         if (num_comp > 1)
 268                 printf(")");
 269 }
 270
 271 void
 272 mir_print_instruction(midgard_instruction *ins)
 273 {
 274         printf("\t");
 275
 276         if (midgard_is_branch_unit(ins->unit)) {
 277                 const char *branch_target_names[] = {
 278                         "goto", "break", "continue", "discard"
 279                 };
 280
 281                 printf("%s.", mir_get_unit(ins->unit));
 282                 if (ins->branch.target_type == TARGET_DISCARD)
 283                         printf("discard.");
 284                 else if (ins->writeout)
 285                         printf("write.");
 286                 else if (ins->unit == ALU_ENAB_BR_COMPACT &&
 287                          !ins->branch.conditional)
 288                         printf("uncond.");
 289                 else
 290                         printf("cond.");
 291
 292                 if (!ins->branch.conditional)
 293                         printf("always");
 294                 else if (ins->branch.invert_conditional)
 295                         printf("false");
 296                 else
 297                         printf("true");
 298
 299                 if (ins->branch.target_type != TARGET_DISCARD)
 300                         printf(" %s -> block(%d)\n",
 301                                ins->branch.target_type < 4 ?
 302                                        branch_target_names[ins->branch.target_type] : "??",
 303                                ins->branch.target_block);
 304
 305                 return;
 306         }
 307
 308         switch (ins->type) {
 309         case TAG_ALU_4: {
 310                 midgard_alu_op op = ins->alu.op;
 311                 const char *name = alu_opcode_props[op].name;
 312
 313                 if (ins->unit)
 314                         printf("%s.", mir_get_unit(ins->unit));
 315
 316                 printf("%s", name ? name : "??");
 317                 break;
 318         }
 319
 320         case TAG_LOAD_STORE_4: {
 321                 midgard_load_store_op op = ins->load_store.op;
 322                 const char *name = load_store_opcode_props[op].name;
 323
 324                 assert(name);
 325                 printf("%s", name);
 326                 break;
 327         }
 328
 329         case TAG_TEXTURE_4: {
 330                 printf("texture");
 331
 332                 if (ins->helper_terminate)
 333                         printf(".terminate");
 334
 335                 if (ins->helper_execute)
 336                         printf(".execute");
 337
 338                 break;
 339         }
 340
 341         default:
 342                 assert(0);
 343         }
 344
 345         if (ins->invert || (ins->compact_branch && ins->branch.invert_conditional))
 346                 printf(".not");
 347
 348         printf(" ");
 349         mir_print_index(ins->dest);
 350
 351         if (ins->dest) {
 352                 pan_print_alu_type(ins->dest_type, stdout);
 353                 mir_print_mask(ins->mask);
 354         }
 355
 356         printf(", ");
 357
 358         unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
 359
 360         if (ins->src[0] == r_constant)
 361                 mir_print_embedded_constant(ins, 0);
 362         else {
 363                 mir_print_index(ins->src[0]);
 364
 365                 if (ins->src[0] != ~0) {
 366                         pan_print_alu_type(ins->src_types[0], stdout);
 367                         mir_print_swizzle(ins->swizzle[0], ins->src_types[0]);
 368                 }
 369         }
 370         printf(", ");
 371
 372         if (ins->has_inline_constant)
 373                 printf("#%d", ins->inline_constant);
 374         else if (ins->src[1] == r_constant)
 375                 mir_print_embedded_constant(ins, 1);
 376         else {
 377                 mir_print_index(ins->src[1]);
 378
 379                 if (ins->src[1] != ~0) {
 380                         pan_print_alu_type(ins->src_types[1], stdout);
 381                         mir_print_swizzle(ins->swizzle[1], ins->src_types[1]);
 382                 }
 383         }
 384
 385         for (unsigned c = 2; c <= 3; ++c) {
 386                 printf(", ");
 387                 mir_print_index(ins->src[c]);
 388
 389                 if (ins->src[c] != ~0) {
 390                         pan_print_alu_type(ins->src_types[c], stdout);
 391                         mir_print_swizzle(ins->swizzle[c], ins->src_types[c]);
 392                 }
 393         }
 394
 395         if (ins->no_spill)
 396                 printf(" /* no spill */");
 397
 398         printf("\n");
 399 }
 400
 401 /* Dumps MIR for a block or entire shader respective */
 402
 403 void
 404 mir_print_block(midgard_block *block)
 405 {
 406         printf("block%u: {\n", block->base.name);
 407
 408         if (block->scheduled) {
 409                 mir_foreach_bundle_in_block(block, bundle) {
 410                         for (unsigned i = 0; i < bundle->instruction_count; ++i)
 411                                 mir_print_instruction(bundle->instructions[i]);
 412
 413                         printf("\n");
 414                 }
 415         } else {
 416                 mir_foreach_instr_in_block(block, ins) {
 417                         mir_print_instruction(ins);
 418                 }
 419         }
 420
 421         printf("}");
 422
 423         if (block->base.successors[0]) {
 424                 printf(" -> ");
 425                 pan_foreach_successor((&block->base), succ)
 426                         printf(" block%u ", succ->name);
 427         }
 428
 429         printf(" from { ");
 430         mir_foreach_predecessor(block, pred)
 431                 printf("block%u ", pred->base.name);
 432         printf("}");
 433
 434         printf("\n\n");
 435 }
 436
 437 void
 438 mir_print_shader(compiler_context *ctx)
 439 {
 440         mir_foreach_block(ctx, block) {
 441                 mir_print_block((midgard_block *) block);
 442         }
 443 }