2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 * Copyright (C) 2019 Collabora, Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "midgard_ops.h"
27 #include "util/register_allocate.h"
28 #include "util/u_math.h"
30 /* For work registers, we can subdivide in various ways. So we create
31 * classes for the various sizes and conflict accordingly, keeping in
32 * mind that physical registers are divided along 128-bit boundaries.
33 * The important part is that 128-bit boundaries are not crossed.
35 * For each 128-bit register, we can subdivide to 32-bits 10 ways
42 * For each 64-bit register, we can subdivide similarly to 16-bit
43 * (TODO: half-float RA, not that we support fp16 yet)
46 #define WORK_STRIDE 10
48 /* We have overlapping register classes for special registers, handled via
54 /* Prepacked masks/swizzles for virtual register types */
55 static unsigned reg_type_to_mask
[WORK_STRIDE
] = {
57 0x7, 0x7 << 1, /* xyz */
58 0x3, 0x3 << 1, 0x3 << 2, /* xy */
59 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
62 static unsigned reg_type_to_swizzle
[WORK_STRIDE
] = {
63 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
65 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
66 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
, COMPONENT_W
),
68 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
69 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_Z
, COMPONENT_W
),
70 SWIZZLE(COMPONENT_Z
, COMPONENT_W
, COMPONENT_Z
, COMPONENT_W
),
72 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
73 SWIZZLE(COMPONENT_Y
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
74 SWIZZLE(COMPONENT_Z
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
75 SWIZZLE(COMPONENT_W
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
84 /* Given the mask/swizzle of both the register and the original source,
85 * compose to find the actual mask/swizzle to give the hardware */
88 compose_writemask(unsigned mask
, struct phys_reg reg
)
90 /* Note: the reg mask is guaranteed to be contiguous. So we shift
91 * into the X place, compose via a simple AND, and shift back */
93 unsigned shift
= __builtin_ctz(reg
.mask
);
94 return ((reg
.mask
>> shift
) & mask
) << shift
;
98 compose_swizzle(unsigned swizzle
, unsigned mask
,
99 struct phys_reg reg
, struct phys_reg dst
)
101 unsigned out
= pan_compose_swizzle(swizzle
, reg
.swizzle
);
103 /* Based on the register mask, we need to adjust over. E.g if we're
104 * writing to yz, a base swizzle of xy__ becomes _xy_. Save the
105 * original first component (x). But to prevent duplicate shifting
106 * (only applies to ALU -- mask param is set to xyzw out on L/S to
107 * prevent changes), we have to account for the shift inherent to the
108 * original writemask */
110 unsigned rep
= out
& 0x3;
111 unsigned shift
= __builtin_ctz(dst
.mask
) - __builtin_ctz(mask
);
112 unsigned shifted
= out
<< (2*shift
);
114 /* ..but we fill in the gaps so it appears to replicate */
116 for (unsigned s
= 0; s
< shift
; ++s
)
117 shifted
|= rep
<< (2*s
);
122 /* Helper to return the default phys_reg for a given register */
124 static struct phys_reg
125 default_phys_reg(int reg
)
127 struct phys_reg r
= {
129 .mask
= 0xF, /* xyzw */
130 .swizzle
= 0xE4 /* xyzw */
136 /* Determine which physical register, swizzle, and mask a virtual
137 * register corresponds to */
139 static struct phys_reg
140 index_to_reg(compiler_context
*ctx
, struct ra_graph
*g
, int reg
)
142 /* Check for special cases */
143 if (reg
>= SSA_FIXED_MINIMUM
)
144 return default_phys_reg(SSA_REG_FROM_FIXED(reg
));
145 else if ((reg
< 0) || !g
)
146 return default_phys_reg(REGISTER_UNUSED
);
148 /* Special cases aside, we pick the underlying register */
149 int virt
= ra_get_node_reg(g
, reg
);
151 /* Divide out the register and classification */
152 int phys
= virt
/ WORK_STRIDE
;
153 int type
= virt
% WORK_STRIDE
;
155 /* Apply shadow registers */
157 if (phys
>= SHADOW_R28
&& phys
<= SHADOW_R29
)
158 phys
+= 28 - SHADOW_R28
;
160 struct phys_reg r
= {
162 .mask
= reg_type_to_mask
[type
],
163 .swizzle
= reg_type_to_swizzle
[type
]
166 /* Report that we actually use this register, and return it */
169 ctx
->work_registers
= MAX2(ctx
->work_registers
, phys
);
174 /* This routine creates a register set. Should be called infrequently since
175 * it's slow and can be cached. For legibility, variables are named in terms of
176 * work registers, although it is also used to create the register set for
177 * special register allocation */
180 add_shadow_conflicts (struct ra_regs
*regs
, unsigned base
, unsigned shadow
)
182 for (unsigned a
= 0; a
< WORK_STRIDE
; ++a
) {
183 unsigned reg_a
= (WORK_STRIDE
* base
) + a
;
185 for (unsigned b
= 0; b
< WORK_STRIDE
; ++b
) {
186 unsigned reg_b
= (WORK_STRIDE
* shadow
) + b
;
188 ra_add_reg_conflict(regs
, reg_a
, reg_b
);
189 ra_add_reg_conflict(regs
, reg_b
, reg_a
);
194 static struct ra_regs
*
195 create_register_set(unsigned work_count
, unsigned *classes
)
197 int virtual_count
= 32 * WORK_STRIDE
;
199 /* First, initialize the RA */
200 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, virtual_count
, true);
202 for (unsigned c
= 0; c
< NR_REG_CLASSES
; ++c
) {
203 int work_vec4
= ra_alloc_reg_class(regs
);
204 int work_vec3
= ra_alloc_reg_class(regs
);
205 int work_vec2
= ra_alloc_reg_class(regs
);
206 int work_vec1
= ra_alloc_reg_class(regs
);
208 classes
[4*c
+ 0] = work_vec1
;
209 classes
[4*c
+ 1] = work_vec2
;
210 classes
[4*c
+ 2] = work_vec3
;
211 classes
[4*c
+ 3] = work_vec4
;
213 /* Special register classes have other register counts */
215 (c
== REG_CLASS_WORK
) ? work_count
: 2;
218 (c
== REG_CLASS_LDST
) ? 26 :
219 (c
== REG_CLASS_TEXR
) ? 28 :
220 (c
== REG_CLASS_TEXW
) ? SHADOW_R28
:
223 /* Add the full set of work registers */
224 for (unsigned i
= first_reg
; i
< (first_reg
+ count
); ++i
) {
225 int base
= WORK_STRIDE
* i
;
227 /* Build a full set of subdivisions */
228 ra_class_add_reg(regs
, work_vec4
, base
);
229 ra_class_add_reg(regs
, work_vec3
, base
+ 1);
230 ra_class_add_reg(regs
, work_vec3
, base
+ 2);
231 ra_class_add_reg(regs
, work_vec2
, base
+ 3);
232 ra_class_add_reg(regs
, work_vec2
, base
+ 4);
233 ra_class_add_reg(regs
, work_vec2
, base
+ 5);
234 ra_class_add_reg(regs
, work_vec1
, base
+ 6);
235 ra_class_add_reg(regs
, work_vec1
, base
+ 7);
236 ra_class_add_reg(regs
, work_vec1
, base
+ 8);
237 ra_class_add_reg(regs
, work_vec1
, base
+ 9);
239 for (unsigned a
= 0; a
< 10; ++a
) {
240 unsigned mask1
= reg_type_to_mask
[a
];
242 for (unsigned b
= 0; b
< 10; ++b
) {
243 unsigned mask2
= reg_type_to_mask
[b
];
246 ra_add_reg_conflict(regs
,
254 /* We have duplicate classes */
255 add_shadow_conflicts(regs
, 28, SHADOW_R28
);
256 add_shadow_conflicts(regs
, 29, SHADOW_R29
);
258 /* We're done setting up */
259 ra_set_finalize(regs
, NULL
);
264 /* This routine gets a precomputed register set off the screen if it's able, or
265 * otherwise it computes one on the fly */
267 static struct ra_regs
*
268 get_register_set(struct midgard_screen
*screen
, unsigned work_count
, unsigned **classes
)
271 assert(work_count
>= 8);
272 assert(work_count
<= 16);
275 unsigned index
= work_count
- 8;
277 /* Find the reg set */
278 struct ra_regs
*cached
= screen
->regs
[index
];
281 assert(screen
->reg_classes
[index
]);
282 *classes
= screen
->reg_classes
[index
];
286 /* Otherwise, create one */
287 struct ra_regs
*created
= create_register_set(work_count
, screen
->reg_classes
[index
]);
289 /* Cache it and use it */
290 screen
->regs
[index
] = created
;
292 *classes
= screen
->reg_classes
[index
];
296 /* Assign a (special) class, ensuring that it is compatible with whatever class
300 set_class(unsigned *classes
, unsigned node
, unsigned class)
302 /* Check that we're even a node */
303 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
306 /* First 4 are work, next 4 are load/store.. */
307 unsigned current_class
= classes
[node
] >> 2;
310 if (class == current_class
)
313 /* If we're changing, we haven't assigned a special class */
314 assert(current_class
== REG_CLASS_WORK
);
316 classes
[node
] &= 0x3;
317 classes
[node
] |= (class << 2);
321 force_vec4(unsigned *classes
, unsigned node
)
323 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
327 classes
[node
] |= 0x3;
330 /* Special register classes impose special constraints on who can read their
331 * values, so check that */
334 check_read_class(unsigned *classes
, unsigned tag
, unsigned node
)
336 /* Non-nodes are implicitly ok */
337 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
340 unsigned current_class
= classes
[node
] >> 2;
342 switch (current_class
) {
344 return (tag
== TAG_LOAD_STORE_4
);
346 return (tag
== TAG_TEXTURE_4
);
348 return (tag
!= TAG_LOAD_STORE_4
);
350 return (tag
== TAG_ALU_4
);
352 unreachable("Invalid class");
357 check_write_class(unsigned *classes
, unsigned tag
, unsigned node
)
359 /* Non-nodes are implicitly ok */
360 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
363 unsigned current_class
= classes
[node
] >> 2;
365 switch (current_class
) {
369 return (tag
== TAG_TEXTURE_4
);
372 return (tag
== TAG_ALU_4
) || (tag
== TAG_LOAD_STORE_4
);
374 unreachable("Invalid class");
378 /* Prepass before RA to ensure special class restrictions are met. The idea is
379 * to create a bit field of types of instructions that read a particular index.
380 * Later, we'll add moves as appropriate and rewrite to specialize by type. */
383 mark_node_class (unsigned *bitfield
, unsigned node
)
385 if ((node
>= 0) && (node
< SSA_FIXED_MINIMUM
))
386 BITSET_SET(bitfield
, node
);
390 mir_lower_special_reads(compiler_context
*ctx
)
392 size_t sz
= BITSET_WORDS(ctx
->temp_count
) * sizeof(BITSET_WORD
);
394 /* Bitfields for the various types of registers we could have */
396 unsigned *alur
= calloc(sz
, 1);
397 unsigned *aluw
= calloc(sz
, 1);
398 unsigned *ldst
= calloc(sz
, 1);
399 unsigned *texr
= calloc(sz
, 1);
400 unsigned *texw
= calloc(sz
, 1);
402 /* Pass #1 is analysis, a linear scan to fill out the bitfields */
404 mir_foreach_instr_global(ctx
, ins
) {
407 mark_node_class(aluw
, ins
->ssa_args
.dest
);
408 mark_node_class(alur
, ins
->ssa_args
.src0
);
409 mark_node_class(alur
, ins
->ssa_args
.src1
);
412 case TAG_LOAD_STORE_4
:
413 mark_node_class(ldst
, ins
->ssa_args
.src0
);
414 mark_node_class(ldst
, ins
->ssa_args
.src1
);
417 mark_node_class(texr
, ins
->ssa_args
.src0
);
418 mark_node_class(texr
, ins
->ssa_args
.src1
);
419 mark_node_class(texw
, ins
->ssa_args
.dest
);
424 /* Pass #2 is lowering now that we've analyzed all the classes.
425 * Conceptually, if an index is only marked for a single type of use,
426 * there is nothing to lower. If it is marked for different uses, we
427 * split up based on the number of types of uses. To do so, we divide
428 * into N distinct classes of use (where N>1 by definition), emit N-1
429 * moves from the index to copies of the index, and finally rewrite N-1
430 * of the types of uses to use the corresponding move */
432 unsigned spill_idx
= ctx
->temp_count
;
434 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
435 bool is_alur
= BITSET_TEST(alur
, i
);
436 bool is_aluw
= BITSET_TEST(aluw
, i
);
437 bool is_ldst
= BITSET_TEST(ldst
, i
);
438 bool is_texr
= BITSET_TEST(texr
, i
);
439 bool is_texw
= BITSET_TEST(texw
, i
);
441 /* Analyse to check how many distinct uses there are. ALU ops
442 * (alur) can read the results of the texture pipeline (texw)
443 * but not ldst or texr. Load/store ops (ldst) cannot read
444 * anything but load/store inputs. Texture pipeline cannot read
445 * anything but texture inputs. TODO: Simplify. */
448 (is_alur
&& (is_ldst
|| is_texr
)) ||
449 (is_ldst
&& (is_alur
|| is_texr
|| is_texw
)) ||
450 (is_texr
&& (is_alur
|| is_ldst
|| is_texw
)) ||
451 (is_texw
&& (is_aluw
|| is_ldst
|| is_texr
));
456 /* Use the index as-is as the work copy. Emit copies for
459 unsigned classes
[] = { TAG_LOAD_STORE_4
, TAG_TEXTURE_4
, TAG_TEXTURE_4
};
460 bool collisions
[] = { is_ldst
, is_texr
, is_texw
&& is_aluw
};
462 for (unsigned j
= 0; j
< ARRAY_SIZE(collisions
); ++j
) {
463 if (!collisions
[j
]) continue;
465 /* When the hazard is from reading, we move and rewrite
466 * sources (typical case). When it's from writing, we
467 * flip the move and rewrite destinations (obscure,
468 * only from control flow -- impossible in SSA) */
470 bool hazard_write
= (j
== 2);
472 unsigned idx
= spill_idx
++;
474 midgard_instruction m
= hazard_write
?
475 v_mov(idx
, blank_alu_src
, i
) :
476 v_mov(i
, blank_alu_src
, idx
);
478 /* Insert move before each read/write, depending on the
479 * hazard we're trying to account for */
481 mir_foreach_instr_global_safe(ctx
, pre_use
) {
482 if (pre_use
->type
!= classes
[j
])
486 if (pre_use
->ssa_args
.dest
!= i
)
489 if (!mir_has_arg(pre_use
, i
))
494 midgard_instruction
*use
= mir_next_op(pre_use
);
496 mir_insert_instruction_before(use
, m
);
498 mir_insert_instruction_before(pre_use
, m
);
504 mir_rewrite_index_dst_tag(ctx
, i
, idx
, classes
[j
]);
506 mir_rewrite_index_src_tag(ctx
, i
, idx
, classes
[j
]);
517 /* This routine performs the actual register allocation. It should be succeeded
518 * by install_registers */
521 allocate_registers(compiler_context
*ctx
, bool *spilled
)
523 /* The number of vec4 work registers available depends on when the
524 * uniforms start, so compute that first */
525 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
526 unsigned *classes
= NULL
;
527 struct ra_regs
*regs
= get_register_set(ctx
->screen
, work_count
, &classes
);
529 assert(regs
!= NULL
);
530 assert(classes
!= NULL
);
532 /* No register allocation to do with no SSA */
534 if (!ctx
->temp_count
)
537 /* Let's actually do register allocation */
538 int nodes
= ctx
->temp_count
;
539 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
541 /* Register class (as known to the Mesa register allocator) is actually
542 * the product of both semantic class (work, load/store, texture..) and
543 * size (vec2/vec3..). First, we'll go through and determine the
544 * minimum size needed to hold values */
546 unsigned *found_class
= calloc(sizeof(unsigned), ctx
->temp_count
);
548 mir_foreach_instr_global(ctx
, ins
) {
549 if (ins
->ssa_args
.dest
< 0) continue;
550 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
552 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
553 int class = util_logbase2(ins
->mask
);
555 /* Use the largest class if there's ambiguity, this
556 * handles partial writes */
558 int dest
= ins
->ssa_args
.dest
;
559 found_class
[dest
] = MAX2(found_class
[dest
], class);
562 /* Next, we'll determine semantic class. We default to zero (work).
563 * But, if we're used with a special operation, that will force us to a
564 * particular class. Each node must be assigned to exactly one class; a
565 * prepass before RA should have lowered what-would-have-been
566 * multiclass nodes into a series of moves to break it up into multiple
569 mir_foreach_instr_global(ctx
, ins
) {
570 /* Check if this operation imposes any classes */
572 if (ins
->type
== TAG_LOAD_STORE_4
) {
573 bool force_vec4_only
= OP_IS_VEC4_ONLY(ins
->load_store
.op
);
575 set_class(found_class
, ins
->ssa_args
.src0
, REG_CLASS_LDST
);
576 set_class(found_class
, ins
->ssa_args
.src1
, REG_CLASS_LDST
);
578 if (force_vec4_only
) {
579 force_vec4(found_class
, ins
->ssa_args
.dest
);
580 force_vec4(found_class
, ins
->ssa_args
.src0
);
581 force_vec4(found_class
, ins
->ssa_args
.src1
);
583 } else if (ins
->type
== TAG_TEXTURE_4
) {
584 set_class(found_class
, ins
->ssa_args
.dest
, REG_CLASS_TEXW
);
585 set_class(found_class
, ins
->ssa_args
.src0
, REG_CLASS_TEXR
);
586 set_class(found_class
, ins
->ssa_args
.src1
, REG_CLASS_TEXR
);
590 /* Check that the semantics of the class are respected */
591 mir_foreach_instr_global(ctx
, ins
) {
592 assert(check_write_class(found_class
, ins
->type
, ins
->ssa_args
.dest
));
593 assert(check_read_class(found_class
, ins
->type
, ins
->ssa_args
.src0
));
594 assert(check_read_class(found_class
, ins
->type
, ins
->ssa_args
.src1
));
597 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
598 unsigned class = found_class
[i
];
599 ra_set_node_class(g
, i
, classes
[class]);
602 /* Determine liveness */
604 int *live_start
= malloc(nodes
* sizeof(int));
605 int *live_end
= malloc(nodes
* sizeof(int));
607 /* Initialize as non-existent */
609 for (int i
= 0; i
< nodes
; ++i
) {
610 live_start
[i
] = live_end
[i
] = -1;
615 mir_foreach_block(ctx
, block
) {
616 mir_foreach_instr_in_block(block
, ins
) {
617 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
618 /* If this destination is not yet live, it is
619 * now since we just wrote it */
621 int dest
= ins
->ssa_args
.dest
;
623 if (dest
>= 0 && live_start
[dest
] == -1)
624 live_start
[dest
] = d
;
627 /* Since we just used a source, the source might be
628 * dead now. Scan the rest of the block for
629 * invocations, and if there are none, the source dies
633 ins
->ssa_args
.src0
, ins
->ssa_args
.src1
636 for (int src
= 0; src
< 2; ++src
) {
637 int s
= sources
[src
];
641 if (s
>= SSA_FIXED_MINIMUM
) continue;
643 if (!mir_is_live_after(ctx
, block
, ins
, s
)) {
652 /* If a node still hasn't been killed, kill it now */
654 for (int i
= 0; i
< nodes
; ++i
) {
655 /* live_start == -1 most likely indicates a pinned output */
657 if (live_end
[i
] == -1)
661 /* Setup interference between nodes that are live at the same time */
663 for (int i
= 0; i
< nodes
; ++i
) {
664 for (int j
= i
+ 1; j
< nodes
; ++j
) {
665 bool j_overlaps_i
= live_start
[j
] < live_end
[i
];
666 bool i_overlaps_j
= live_end
[j
] < live_start
[i
];
668 if (i_overlaps_j
|| j_overlaps_i
)
669 ra_add_node_interference(g
, i
, j
);
677 if (!ra_allocate(g
)) {
683 /* Whether we were successful or not, report the graph so we can
684 * compute spill nodes */
689 /* Once registers have been decided via register allocation
690 * (allocate_registers), we need to rewrite the MIR to use registers instead of
694 install_registers_instr(
695 compiler_context
*ctx
,
697 midgard_instruction
*ins
)
699 ssa_args args
= ins
->ssa_args
;
703 struct phys_reg src1
= index_to_reg(ctx
, g
, args
.src0
);
704 struct phys_reg src2
= index_to_reg(ctx
, g
, args
.src1
);
705 struct phys_reg dest
= index_to_reg(ctx
, g
, args
.dest
);
707 unsigned uncomposed_mask
= ins
->mask
;
708 ins
->mask
= compose_writemask(uncomposed_mask
, dest
);
710 /* Adjust the dest mask if necessary. Mostly this is a no-op
711 * but it matters for dot products */
712 dest
.mask
= effective_writemask(&ins
->alu
, ins
->mask
);
714 midgard_vector_alu_src mod1
=
715 vector_alu_from_unsigned(ins
->alu
.src1
);
716 mod1
.swizzle
= compose_swizzle(mod1
.swizzle
, uncomposed_mask
, src1
, dest
);
717 ins
->alu
.src1
= vector_alu_srco_unsigned(mod1
);
719 ins
->registers
.src1_reg
= src1
.reg
;
721 ins
->registers
.src2_imm
= args
.inline_constant
;
723 if (args
.inline_constant
) {
724 /* Encode inline 16-bit constant. See disassembler for
725 * where the algorithm is from */
727 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
729 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
730 uint16_t imm
= ((lower_11
>> 8) & 0x7) |
731 ((lower_11
& 0xFF) << 3);
733 ins
->alu
.src2
= imm
<< 2;
735 midgard_vector_alu_src mod2
=
736 vector_alu_from_unsigned(ins
->alu
.src2
);
737 mod2
.swizzle
= compose_swizzle(
738 mod2
.swizzle
, uncomposed_mask
, src2
, dest
);
739 ins
->alu
.src2
= vector_alu_srco_unsigned(mod2
);
741 ins
->registers
.src2_reg
= src2
.reg
;
744 ins
->registers
.out_reg
= dest
.reg
;
748 case TAG_LOAD_STORE_4
: {
749 bool fixed
= args
.src0
>= SSA_FIXED_MINIMUM
;
751 /* Which physical register we read off depends on
752 * whether we are loading or storing -- think about the
753 * logical dataflow */
756 OP_IS_STORE(ins
->load_store
.op
) &&
757 ins
->load_store
.op
!= midgard_op_st_cubemap_coords
;
759 if (OP_IS_STORE_R26(ins
->load_store
.op
) && fixed
) {
760 ins
->load_store
.reg
= SSA_REG_FROM_FIXED(args
.src0
);
761 } else if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
762 struct phys_reg src
= index_to_reg(ctx
, g
, args
.src0
);
763 assert(src
.reg
== 26 || src
.reg
== 27);
765 ins
->load_store
.reg
= src
.reg
- 26;
767 /* TODO: swizzle/mask */
769 unsigned r
= encodes_src
?
770 args
.src0
: args
.dest
;
772 struct phys_reg src
= index_to_reg(ctx
, g
, r
);
774 ins
->load_store
.reg
= src
.reg
;
776 ins
->load_store
.swizzle
= compose_swizzle(
777 ins
->load_store
.swizzle
, 0xF,
778 default_phys_reg(0), src
);
780 ins
->mask
= compose_writemask(
784 /* We also follow up by actual arguments */
787 encodes_src
? args
.src1
: args
.src0
;
790 encodes_src
? -1 : args
.src1
;
793 struct phys_reg src
= index_to_reg(ctx
, g
, src2
);
794 unsigned component
= __builtin_ctz(src
.mask
);
795 ins
->load_store
.arg_1
|= midgard_ldst_reg(src
.reg
, component
);
799 struct phys_reg src
= index_to_reg(ctx
, g
, src3
);
800 unsigned component
= __builtin_ctz(src
.mask
);
801 ins
->load_store
.arg_2
|= midgard_ldst_reg(src
.reg
, component
);
807 case TAG_TEXTURE_4
: {
808 /* Grab RA results */
809 struct phys_reg dest
= index_to_reg(ctx
, g
, args
.dest
);
810 struct phys_reg coord
= index_to_reg(ctx
, g
, args
.src0
);
811 struct phys_reg lod
= index_to_reg(ctx
, g
, args
.src1
);
813 assert(dest
.reg
== 28 || dest
.reg
== 29);
814 assert(coord
.reg
== 28 || coord
.reg
== 29);
816 /* First, install the texture coordinate */
817 ins
->texture
.in_reg_full
= 1;
818 ins
->texture
.in_reg_upper
= 0;
819 ins
->texture
.in_reg_select
= coord
.reg
- 28;
820 ins
->texture
.in_reg_swizzle
=
821 compose_swizzle(ins
->texture
.in_reg_swizzle
, 0xF, coord
, dest
);
823 /* Next, install the destination */
824 ins
->texture
.out_full
= 1;
825 ins
->texture
.out_upper
= 0;
826 ins
->texture
.out_reg_select
= dest
.reg
- 28;
827 ins
->texture
.swizzle
=
828 compose_swizzle(ins
->texture
.swizzle
, dest
.mask
, dest
, dest
);
830 compose_writemask(ins
->mask
, dest
);
832 /* If there is a register LOD/bias, use it */
833 if (args
.src1
> -1) {
834 midgard_tex_register_select sel
= {
837 .component
= lod
.swizzle
& 3,
841 memcpy(&packed
, &sel
, sizeof(packed
));
842 ins
->texture
.bias
= packed
;
854 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
856 mir_foreach_block(ctx
, block
) {
857 mir_foreach_instr_in_block(block
, ins
) {
858 install_registers_instr(ctx
, g
, ins
);