src/panfrost/midgard/mir.c

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new)
  28 {
  29         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
  30                 if (ins->src[i] == old)
  31                         ins->src[i] = new;
  32         }
  33 }
  34
  35 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new)
  36 {
  37         if (ins->dest == old)
  38                 ins->dest = new;
  39 }
  40
  41 static void
  42 mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned *swizzle)
  43 {
  44         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
  45                 if (ins->src[i] != old) continue;
  46
  47                 ins->src[i] = new;
  48                 mir_compose_swizzle(ins->swizzle[i], swizzle, ins->swizzle[i]);
  49         }
  50 }
  51
  52 void
  53 mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new)
  54 {
  55         mir_foreach_instr_global(ctx, ins) {
  56                 mir_rewrite_index_src_single(ins, old, new);
  57         }
  58 }
  59
  60 void
  61 mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle)
  62 {
  63         mir_foreach_instr_global(ctx, ins) {
  64                 mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle);
  65         }
  66 }
  67
  68 void
  69 mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
  70 {
  71         mir_foreach_instr_global(ctx, ins) {
  72                 mir_rewrite_index_dst_single(ins, old, new);
  73         }
  74 }
  75
  76 void
  77 mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new)
  78 {
  79         mir_rewrite_index_src(ctx, old, new);
  80         mir_rewrite_index_dst(ctx, old, new);
  81 }
  82
  83 unsigned
  84 mir_use_count(compiler_context *ctx, unsigned value)
  85 {
  86         unsigned used_count = 0;
  87
  88         mir_foreach_instr_global(ctx, ins) {
  89                 if (mir_has_arg(ins, value))
  90                         ++used_count;
  91         }
  92
  93         return used_count;
  94 }
  95
  96 /* Checks if a value is used only once (or totally dead), which is an important
  97  * heuristic to figure out if certain optimizations are Worth It (TM) */
  98
  99 bool
 100 mir_single_use(compiler_context *ctx, unsigned value)
 101 {
 102         /* We can replicate constants in places so who cares */
 103         if (value == SSA_FIXED_REGISTER(REGISTER_CONSTANT))
 104                 return true;
 105
 106         return mir_use_count(ctx, value) <= 1;
 107 }
 108
 109 bool
 110 mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle)
 111 {
 112         bool is_int = midgard_is_integer_op(ins->alu.op);
 113
 114         if (is_int) {
 115                 if (ins->src_shift[i]) return true;
 116         } else {
 117                 if (ins->src_neg[i]) return true;
 118                 if (ins->src_abs[i]) return true;
 119         }
 120
 121         if (ins->dest_type != ins->src_types[i]) return true;
 122
 123         if (check_swizzle) {
 124                 for (unsigned c = 0; c < 16; ++c) {
 125                         if (!(ins->mask & (1 << c))) continue;
 126                         if (ins->swizzle[i][c] != c) return true;
 127                 }
 128         }
 129
 130         return false;
 131 }
 132
 133 bool
 134 mir_nontrivial_outmod(midgard_instruction *ins)
 135 {
 136         bool is_int = midgard_is_integer_op(ins->alu.op);
 137         unsigned mod = ins->alu.outmod;
 138
 139         if (ins->dest_type != ins->src_types[1])
 140                 return true;
 141
 142         if (is_int)
 143                 return mod != midgard_outmod_int_wrap;
 144         else
 145                 return mod != midgard_outmod_none;
 146 }
 147
 148 /* 128 / sz = exp2(log2(128 / sz))
 149  *          = exp2(log2(128) - log2(sz))
 150  *          = exp2(7 - log2(sz))
 151  *          = 1 << (7 - log2(sz))
 152  */
 153
 154 static unsigned
 155 mir_components_for_bits(unsigned bits)
 156 {
 157         return 1 << (7 - util_logbase2(bits));
 158 }
 159
 160 unsigned
 161 mir_components_for_type(nir_alu_type T)
 162 {
 163         unsigned sz = nir_alu_type_get_type_size(T);
 164         return mir_components_for_bits(sz);
 165 }
 166
 167 uint16_t
 168 mir_from_bytemask(uint16_t bytemask, unsigned bits)
 169 {
 170         unsigned value = 0;
 171         unsigned count = bits / 8;
 172
 173         for (unsigned c = 0, d = 0; c < 16; c += count, ++d) {
 174                 bool a = (bytemask & (1 << c)) != 0;
 175
 176                 for (unsigned q = c; q < count; ++q)
 177                         assert(((bytemask & (1 << q)) != 0) == a);
 178
 179                 value |= (a << d);
 180         }
 181
 182         return value;
 183 }
 184
 185 /* Rounds up a bytemask to fill a given component count. Iterate each
 186  * component, and check if any bytes in the component are masked on */
 187
 188 uint16_t
 189 mir_round_bytemask_up(uint16_t mask, unsigned bits)
 190 {
 191         unsigned bytes = bits / 8;
 192         unsigned maxmask = mask_of(bytes);
 193         unsigned channels = mir_components_for_bits(bits);
 194
 195         for (unsigned c = 0; c < channels; ++c) {
 196                 unsigned submask = maxmask << (c * bytes);
 197
 198                 if (mask & submask)
 199                         mask |= submask;
 200         }
 201
 202         return mask;
 203 }
 204
 205 /* Grabs the per-byte mask of an instruction (as opposed to per-component) */
 206
 207 uint16_t
 208 mir_bytemask(midgard_instruction *ins)
 209 {
 210         unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
 211         return pan_to_bytemask(type_size, ins->mask);
 212 }
 213
 214 void
 215 mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask)
 216 {
 217         unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
 218         ins->mask = mir_from_bytemask(bytemask, type_size);
 219 }
 220
 221 /* Checks if we should use an upper destination override, rather than the lower
 222  * one in the IR. Returns zero if no, returns the bytes to shift otherwise */
 223
 224 signed
 225 mir_upper_override(midgard_instruction *ins, unsigned inst_size)
 226 {
 227         unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
 228
 229         /* If the sizes are the same, there's nothing to override */
 230         if (type_size == inst_size)
 231                 return -1;
 232
 233         /* There are 16 bytes per vector, so there are (16/bytes)
 234          * components per vector. So the magic half is half of
 235          * (16/bytes), which simplifies to 8/bytes = 8 / (bits / 8) = 64 / bits
 236          * */
 237
 238         unsigned threshold = mir_components_for_bits(type_size) >> 1;
 239
 240         /* How many components did we shift over? */
 241         unsigned zeroes = __builtin_ctz(ins->mask);
 242
 243         /* Did we hit the threshold? */
 244         return (zeroes >= threshold) ? threshold : 0;
 245 }
 246
 247 /* Creates a mask of the components of a node read by an instruction, by
 248  * analyzing the swizzle with respect to the instruction's mask. E.g.:
 249  *
 250  *  fadd r0.xz, r1.yyyy, r2.zwyx
 251  *
 252  * will return a mask of Z/Y for r2
 253  */
 254
 255 static uint16_t
 256 mir_bytemask_of_read_components_single(unsigned *swizzle, unsigned inmask, unsigned bits)
 257 {
 258         unsigned cmask = 0;
 259
 260         for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
 261                 if (!(inmask & (1 << c))) continue;
 262                 cmask |= (1 << swizzle[c]);
 263         }
 264
 265         return pan_to_bytemask(bits, cmask);
 266 }
 267
 268 uint16_t
 269 mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i)
 270 {
 271         /* Conditional branches read one 32-bit component = 4 bytes (TODO: multi branch??) */
 272         if (ins->compact_branch && ins->branch.conditional && (i == 0))
 273                 return 0xF;
 274
 275         /* ALU ops act componentwise so we need to pay attention to
 276          * their mask. Texture/ldst does not so we don't clamp source
 277          * readmasks based on the writemask */
 278         unsigned qmask = ~0;
 279
 280         /* Handle dot products and things */
 281         if (ins->type == TAG_ALU_4 && !ins->compact_branch) {
 282                 unsigned props = alu_opcode_props[ins->alu.op].props;
 283
 284                 unsigned channel_override = GET_CHANNEL_COUNT(props);
 285
 286                 if (channel_override)
 287                         qmask = mask_of(channel_override);
 288                 else
 289                         qmask = ins->mask;
 290         }
 291
 292         return mir_bytemask_of_read_components_single(ins->swizzle[i], qmask,
 293                 nir_alu_type_get_type_size(ins->src_types[i]));
 294 }
 295
 296 uint16_t
 297 mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node)
 298 {
 299         uint16_t mask = 0;
 300
 301         if (node == ~0)
 302                 return 0;
 303
 304         mir_foreach_src(ins, i) {
 305                 if (ins->src[i] != node) continue;
 306                 mask |= mir_bytemask_of_read_components_index(ins, i);
 307         }
 308
 309         return mask;
 310 }
 311
 312 /* Register allocation occurs after instruction scheduling, which is fine until
 313  * we start needing to spill registers and therefore insert instructions into
 314  * an already-scheduled program. We don't have to be terribly efficient about
 315  * this, since spilling is already slow. So just semantically we need to insert
 316  * the instruction into a new bundle before/after the bundle of the instruction
 317  * in question */
 318
 319 static midgard_bundle
 320 mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
 321 {
 322         midgard_instruction *u = mir_upload_ins(ctx, ins);
 323
 324         midgard_bundle bundle = {
 325                 .tag = ins.type,
 326                 .instruction_count = 1,
 327                 .instructions = { u },
 328         };
 329
 330         if (bundle.tag == TAG_ALU_4) {
 331                 assert(OP_IS_MOVE(u->alu.op));
 332                 u->unit = UNIT_VMUL;
 333
 334                 size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
 335                 bundle.padding = ~(bytes_emitted - 1) & 0xF;
 336                 bundle.control = ins.type | u->unit;
 337         }
 338
 339         return bundle;
 340 }
 341
 342 static unsigned
 343 mir_bundle_idx_for_ins(midgard_instruction *tag, midgard_block *block)
 344 {
 345         midgard_bundle *bundles =
 346                 (midgard_bundle *) block->bundles.data;
 347
 348         size_t count = (block->bundles.size / sizeof(midgard_bundle));
 349
 350         for (unsigned i = 0; i < count; ++i) {
 351                 for (unsigned j = 0; j < bundles[i].instruction_count; ++j) {
 352                         if (bundles[i].instructions[j] == tag)
 353                                 return i;
 354                 }
 355         }
 356
 357         mir_print_instruction(tag);
 358         unreachable("Instruction not scheduled in block");
 359 }
 360
 361 void
 362 mir_insert_instruction_before_scheduled(
 363         compiler_context *ctx,
 364         midgard_block *block,
 365         midgard_instruction *tag,
 366         midgard_instruction ins)
 367 {
 368         unsigned before = mir_bundle_idx_for_ins(tag, block);
 369         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 370         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 371
 372         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 373         memmove(bundles + before + 1, bundles + before, (count - before) * sizeof(midgard_bundle));
 374         midgard_bundle *before_bundle = bundles + before + 1;
 375
 376         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 377         memcpy(bundles + before, &new, sizeof(new));
 378
 379         list_addtail(&new.instructions[0]->link, &before_bundle->instructions[0]->link);
 380         block->quadword_count += midgard_tag_props[new.tag].size;
 381 }
 382
 383 void
 384 mir_insert_instruction_after_scheduled(
 385         compiler_context *ctx,
 386         midgard_block *block,
 387         midgard_instruction *tag,
 388         midgard_instruction ins)
 389 {
 390         /* We need to grow the bundles array to add our new bundle */
 391         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 392         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 393
 394         /* Find the bundle that we want to insert after */
 395         unsigned after = mir_bundle_idx_for_ins(tag, block);
 396
 397         /* All the bundles after that one, we move ahead by one */
 398         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 399         memmove(bundles + after + 2, bundles + after + 1, (count - after - 1) * sizeof(midgard_bundle));
 400         midgard_bundle *after_bundle = bundles + after;
 401
 402         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 403         memcpy(bundles + after + 1, &new, sizeof(new));
 404         list_add(&new.instructions[0]->link, &after_bundle->instructions[after_bundle->instruction_count - 1]->link);
 405         block->quadword_count += midgard_tag_props[new.tag].size;
 406 }
 407
 408 /* Flip the first-two arguments of a (binary) op. Currently ALU
 409  * only, no known uses for ldst/tex */
 410
 411 void
 412 mir_flip(midgard_instruction *ins)
 413 {
 414         unsigned temp = ins->src[0];
 415         ins->src[0] = ins->src[1];
 416         ins->src[1] = temp;
 417
 418         assert(ins->type == TAG_ALU_4);
 419
 420         temp = ins->alu.src1;
 421         ins->alu.src1 = ins->alu.src2;
 422         ins->alu.src2 = temp;
 423
 424         temp = ins->src_types[0];
 425         ins->src_types[0] = ins->src_types[1];
 426         ins->src_types[1] = temp;
 427
 428         temp = ins->src_abs[0];
 429         ins->src_abs[0] = ins->src_abs[1];
 430         ins->src_abs[1] = temp;
 431
 432         temp = ins->src_neg[0];
 433         ins->src_neg[0] = ins->src_neg[1];
 434         ins->src_neg[1] = temp;
 435
 436         temp = ins->src_invert[0];
 437         ins->src_invert[0] = ins->src_invert[1];
 438         ins->src_invert[1] = temp;
 439
 440         unsigned temp_swizzle[16];
 441         memcpy(temp_swizzle, ins->swizzle[0], sizeof(ins->swizzle[0]));
 442         memcpy(ins->swizzle[0], ins->swizzle[1], sizeof(ins->swizzle[0]));
 443         memcpy(ins->swizzle[1], temp_swizzle, sizeof(ins->swizzle[0]));
 444 }
 445
 446 /* Before squashing, calculate ctx->temp_count just by observing the MIR */
 447
 448 void
 449 mir_compute_temp_count(compiler_context *ctx)
 450 {
 451         if (ctx->temp_count)
 452                 return;
 453
 454         unsigned max_dest = 0;
 455
 456         mir_foreach_instr_global(ctx, ins) {
 457                 if (ins->dest < SSA_FIXED_MINIMUM)
 458                         max_dest = MAX2(max_dest, ins->dest + 1);
 459         }
 460
 461         ctx->temp_count = max_dest;
 462 }