src/panfrost/midgard/mir.c

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new)
  28 {
  29         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
  30                 if (ins->src[i] == old)
  31                         ins->src[i] = new;
  32         }
  33 }
  34
  35 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new)
  36 {
  37         if (ins->dest == old)
  38                 ins->dest = new;
  39 }
  40
  41 unsigned
  42 mir_get_swizzle(midgard_instruction *ins, unsigned idx)
  43 {
  44         if (ins->type == TAG_ALU_4) {
  45                 if (idx == 2 || ins->compact_branch)
  46                         return ins->cond_swizzle;
  47
  48                 unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
  49
  50                 midgard_vector_alu_src s =
  51                         vector_alu_from_unsigned(b);
  52
  53                 return s.swizzle;
  54         } else if (ins->type == TAG_LOAD_STORE_4) {
  55                 /* Main swizzle of a load is on the destination */
  56                 if (!OP_IS_STORE(ins->load_store.op))
  57                         idx++;
  58
  59                 switch (idx) {
  60                 case 0:
  61                         return ins->load_store.swizzle;
  62                 case 1:
  63                 case 2: {
  64                         uint8_t raw =
  65                                 (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
  66
  67                         /* TODO: Integrate component count with properties */
  68                         unsigned components = 1;
  69                         switch (ins->load_store.op) {
  70                         case midgard_op_ld_int4:
  71                                 components = (idx == 0) ? 2 : 1;
  72                                 break;
  73                         case midgard_op_st_int4:
  74                                 components = (idx == 1) ? 2 : 1;
  75                                 break;
  76                         case midgard_op_ld_cubemap_coords:
  77                                 components = 3;
  78                                 break;
  79                         default:
  80                                 components = 1;
  81                                 break;
  82                         }
  83
  84                         return component_to_swizzle(midgard_ldst_select(raw).component, components);
  85                 }
  86                 default:
  87                         unreachable("Unknown load/store source");
  88                 }
  89         } else if (ins->type == TAG_TEXTURE_4) {
  90                 switch (idx) {
  91                 case 0:
  92                         return ins->texture.in_reg_swizzle;
  93                 case 1:
  94                         /* Swizzle on bias doesn't make sense */
  95                         return 0;
  96                 default:
  97                         unreachable("Unknown texture source");
  98                 }
  99         } else {
 100                 unreachable("Unknown type");
 101         }
 102 }
 103
 104 void
 105 mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new)
 106 {
 107         if (ins->type == TAG_ALU_4) {
 108                 if (idx == 2 || ins->compact_branch) {
 109                         ins->cond_swizzle = new;
 110                         return;
 111                 }
 112
 113                 unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
 114
 115                 midgard_vector_alu_src s =
 116                         vector_alu_from_unsigned(b);
 117
 118                 s.swizzle = new;
 119                 unsigned pack = vector_alu_srco_unsigned(s);
 120
 121                 if (idx == 0)
 122                         ins->alu.src1 = pack;
 123                 else
 124                         ins->alu.src2 = pack;
 125         } else if (ins->type == TAG_LOAD_STORE_4) {
 126                 /* Main swizzle of a load is on the destination */
 127                 if (!OP_IS_STORE(ins->load_store.op))
 128                         idx++;
 129
 130                 switch (idx) {
 131                 case 0:
 132                         ins->load_store.swizzle = new;
 133                         break;
 134                 case 1:
 135                 case 2: {
 136                         uint8_t raw =
 137                                 (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
 138
 139                         midgard_ldst_register_select sel
 140                                 = midgard_ldst_select(raw);
 141                         sel.component = swizzle_to_component(new);
 142                         uint8_t packed = midgard_ldst_pack(sel);
 143
 144                         if (idx == 2)
 145                                 ins->load_store.arg_2 = packed;
 146                         else
 147                                 ins->load_store.arg_1 = packed;
 148
 149                         break;
 150                 }
 151                 default:
 152                         assert(new == 0);
 153                         break;
 154                 }
 155         } else if (ins->type == TAG_TEXTURE_4) {
 156                 switch (idx) {
 157                 case 0:
 158                         ins->texture.in_reg_swizzle = new;
 159                         break;
 160                 default:
 161                         assert(new == 0);
 162                         break;
 163                 }
 164         } else {
 165                 unreachable("Unknown type");
 166         }
 167 }
 168
 169 static void
 170 mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned swizzle)
 171 {
 172         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 173                 if (ins->src[i] != old) continue;
 174
 175                 ins->src[i] = new;
 176
 177                 mir_set_swizzle(ins, i,
 178                         pan_compose_swizzle(mir_get_swizzle(ins, i), swizzle));
 179         }
 180 }
 181
 182 void
 183 mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new)
 184 {
 185         mir_foreach_instr_global(ctx, ins) {
 186                 mir_rewrite_index_src_single(ins, old, new);
 187         }
 188 }
 189
 190 void
 191 mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle)
 192 {
 193         mir_foreach_instr_global(ctx, ins) {
 194                 mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle);
 195         }
 196 }
 197
 198 void
 199 mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
 200 {
 201         mir_foreach_instr_global(ctx, ins) {
 202                 mir_rewrite_index_dst_single(ins, old, new);
 203         }
 204 }
 205
 206 void
 207 mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new)
 208 {
 209         mir_rewrite_index_src(ctx, old, new);
 210         mir_rewrite_index_dst(ctx, old, new);
 211 }
 212
 213 unsigned
 214 mir_use_count(compiler_context *ctx, unsigned value)
 215 {
 216         unsigned used_count = 0;
 217
 218         mir_foreach_instr_global(ctx, ins) {
 219                 if (mir_has_arg(ins, value))
 220                         ++used_count;
 221         }
 222
 223         return used_count;
 224 }
 225
 226 /* Checks if a value is used only once (or totally dead), which is an important
 227  * heuristic to figure out if certain optimizations are Worth It (TM) */
 228
 229 bool
 230 mir_single_use(compiler_context *ctx, unsigned value)
 231 {
 232         /* We can replicate constants in places so who cares */
 233         if (value == SSA_FIXED_REGISTER(REGISTER_CONSTANT))
 234                 return true;
 235
 236         return mir_use_count(ctx, value) <= 1;
 237 }
 238
 239 static bool
 240 mir_nontrivial_raw_mod(midgard_vector_alu_src src, bool is_int)
 241 {
 242         if (is_int)
 243                 return src.mod == midgard_int_shift;
 244         else
 245                 return src.mod;
 246 }
 247
 248 bool
 249 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
 250 {
 251         if (mir_nontrivial_raw_mod(src, is_int)) return true;
 252
 253         /* size-conversion */
 254         if (src.half) return true;
 255
 256         /* swizzle */
 257         for (unsigned c = 0; c < 4; ++c) {
 258                 if (!(mask & (1 << c))) continue;
 259                 if (((src.swizzle >> (2*c)) & 3) != c) return true;
 260         }
 261
 262         return false;
 263 }
 264
 265 bool
 266 mir_nontrivial_source2_mod(midgard_instruction *ins)
 267 {
 268         bool is_int = midgard_is_integer_op(ins->alu.op);
 269
 270         midgard_vector_alu_src src2 =
 271                 vector_alu_from_unsigned(ins->alu.src2);
 272
 273         return mir_nontrivial_mod(src2, is_int, ins->mask);
 274 }
 275
 276 bool
 277 mir_nontrivial_source2_mod_simple(midgard_instruction *ins)
 278 {
 279         bool is_int = midgard_is_integer_op(ins->alu.op);
 280
 281         midgard_vector_alu_src src2 =
 282                 vector_alu_from_unsigned(ins->alu.src2);
 283
 284         return mir_nontrivial_raw_mod(src2, is_int) || src2.half;
 285 }
 286
 287 bool
 288 mir_nontrivial_outmod(midgard_instruction *ins)
 289 {
 290         bool is_int = midgard_is_integer_op(ins->alu.op);
 291         unsigned mod = ins->alu.outmod;
 292
 293         /* Pseudo-outmod */
 294         if (ins->invert)
 295                 return true;
 296
 297         /* Type conversion is a sort of outmod */
 298         if (ins->alu.dest_override != midgard_dest_override_none)
 299                 return true;
 300
 301         if (is_int)
 302                 return mod != midgard_outmod_int_wrap;
 303         else
 304                 return mod != midgard_outmod_none;
 305 }
 306
 307 /* Checks if an index will be used as a special register -- basically, if we're
 308  * used as the input to a non-ALU op */
 309
 310 bool
 311 mir_special_index(compiler_context *ctx, unsigned idx)
 312 {
 313         mir_foreach_instr_global(ctx, ins) {
 314                 bool is_ldst = ins->type == TAG_LOAD_STORE_4;
 315                 bool is_tex = ins->type == TAG_TEXTURE_4;
 316                 bool is_writeout = ins->compact_branch && ins->writeout;
 317
 318                 if (!(is_ldst || is_tex || is_writeout))
 319                         continue;
 320
 321                 if (mir_has_arg(ins, idx))
 322                         return true;
 323         }
 324
 325         return false;
 326 }
 327
 328 /* Is a node written before a given instruction? */
 329
 330 bool
 331 mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node)
 332 {
 333         if (node >= SSA_FIXED_MINIMUM)
 334                 return true;
 335
 336         mir_foreach_instr_global(ctx, q) {
 337                 if (q == ins)
 338                         break;
 339
 340                 if (q->dest == node)
 341                         return true;
 342         }
 343
 344         return false;
 345 }
 346
 347 /* Creates a mask of the components of a node read by an instruction, by
 348  * analyzing the swizzle with respect to the instruction's mask. E.g.:
 349  *
 350  *  fadd r0.xz, r1.yyyy, r2.zwyx
 351  *
 352  * will return a mask of Z/Y for r2
 353  */
 354
 355 static unsigned
 356 mir_mask_of_read_components_single(unsigned swizzle, unsigned outmask)
 357 {
 358         unsigned mask = 0;
 359
 360         for (unsigned c = 0; c < 4; ++c) {
 361                 if (!(outmask & (1 << c))) continue;
 362
 363                 unsigned comp = (swizzle >> (2*c)) & 3;
 364                 mask |= (1 << comp);
 365         }
 366
 367         return mask;
 368 }
 369
 370 static unsigned
 371 mir_source_count(midgard_instruction *ins)
 372 {
 373         if (ins->type == TAG_ALU_4) {
 374                 /* ALU is always binary, except csel */
 375                 return OP_IS_CSEL(ins->alu.op) ? 3 : 2;
 376         } else if (ins->type == TAG_LOAD_STORE_4) {
 377                 bool load = !OP_IS_STORE(ins->load_store.op);
 378                 return (load ? 2 : 3);
 379         } else if (ins->type == TAG_TEXTURE_4) {
 380                 /* Coords, bias.. TODO: Offsets? */
 381                 return 2;
 382         } else {
 383                 unreachable("Invalid instruction type");
 384         }
 385 }
 386
 387 unsigned
 388 mir_mask_of_read_components(midgard_instruction *ins, unsigned node)
 389 {
 390         unsigned mask = 0;
 391
 392         for (unsigned i = 0; i < mir_source_count(ins); ++i) {
 393                 if (ins->src[i] != node) continue;
 394
 395                 /* Branch writeout uses all components */
 396                 if (ins->compact_branch && ins->writeout && (i == 0))
 397                         return 0xF;
 398
 399                 /* ALU ops act componentwise so we need to pay attention to
 400                  * their mask. Texture/ldst does not so we don't clamp source
 401                  * readmasks based on the writemask */
 402                 unsigned qmask = (ins->type == TAG_ALU_4) ? ins->mask : 0xF;
 403
 404                 unsigned swizzle = mir_get_swizzle(ins, i);
 405                 unsigned m = mir_mask_of_read_components_single(swizzle, qmask);
 406
 407                 /* Handle dot products and things */
 408                 if (ins->type == TAG_ALU_4 && !ins->compact_branch) {
 409                         unsigned channel_override =
 410                                 GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props);
 411
 412                         if (channel_override)
 413                                 m = mask_of(channel_override);
 414                 }
 415
 416                 mask |= m;
 417         }
 418
 419         return mask;
 420 }
 421
 422 unsigned
 423 mir_ubo_shift(midgard_load_store_op op)
 424 {
 425         switch (op) {
 426         case midgard_op_ld_ubo_char:
 427                 return 0;
 428         case midgard_op_ld_ubo_char2:
 429                 return 1;
 430         case midgard_op_ld_ubo_char4:
 431                 return 2;
 432         case midgard_op_ld_ubo_short4:
 433                 return 3;
 434         case midgard_op_ld_ubo_int4:
 435                 return 4;
 436         default:
 437                 unreachable("Invalid op");
 438         }
 439 }
 440
 441 /* Register allocation occurs after instruction scheduling, which is fine until
 442  * we start needing to spill registers and therefore insert instructions into
 443  * an already-scheduled program. We don't have to be terribly efficient about
 444  * this, since spilling is already slow. So just semantically we need to insert
 445  * the instruction into a new bundle before/after the bundle of the instruction
 446  * in question */
 447
 448 static midgard_bundle
 449 mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
 450 {
 451         midgard_instruction *u = mir_upload_ins(ctx, ins);
 452
 453         midgard_bundle bundle = {
 454                 .tag = ins.type,
 455                 .instruction_count = 1,
 456                 .instructions = { u },
 457         };
 458
 459         if (bundle.tag == TAG_ALU_4) {
 460                 assert(OP_IS_MOVE(u->alu.op));
 461                 u->unit = UNIT_VMUL;
 462
 463                 size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
 464                 bundle.padding = ~(bytes_emitted - 1) & 0xF;
 465                 bundle.control = ins.type | u->unit;
 466         }
 467
 468         return bundle;
 469 }
 470
 471 static unsigned
 472 mir_bundle_idx_for_ins(midgard_instruction *tag, midgard_block *block)
 473 {
 474         midgard_bundle *bundles =
 475                 (midgard_bundle *) block->bundles.data;
 476
 477         size_t count = (block->bundles.size / sizeof(midgard_bundle));
 478
 479         for (unsigned i = 0; i < count; ++i) {
 480                 for (unsigned j = 0; j < bundles[i].instruction_count; ++j) {
 481                         if (bundles[i].instructions[j] == tag)
 482                                 return i;
 483                 }
 484         }
 485
 486         mir_print_instruction(tag);
 487         unreachable("Instruction not scheduled in block");
 488 }
 489
 490 void
 491 mir_insert_instruction_before_scheduled(
 492         compiler_context *ctx,
 493         midgard_block *block,
 494         midgard_instruction *tag,
 495         midgard_instruction ins)
 496 {
 497         unsigned before = mir_bundle_idx_for_ins(tag, block);
 498         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 499         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 500
 501         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 502         memmove(bundles + before + 1, bundles + before, (count - before) * sizeof(midgard_bundle));
 503         midgard_bundle *before_bundle = bundles + before + 1;
 504
 505         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 506         memcpy(bundles + before, &new, sizeof(new));
 507
 508         list_addtail(&new.instructions[0]->link, &before_bundle->instructions[0]->link);
 509 }
 510
 511 void
 512 mir_insert_instruction_after_scheduled(
 513         compiler_context *ctx,
 514         midgard_block *block,
 515         midgard_instruction *tag,
 516         midgard_instruction ins)
 517 {
 518         unsigned after = mir_bundle_idx_for_ins(tag, block);
 519         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 520         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 521
 522         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 523         memmove(bundles + after + 2, bundles + after + 1, (count - after - 1) * sizeof(midgard_bundle));
 524         midgard_bundle *after_bundle_1 = bundles + after + 2;
 525
 526         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 527         memcpy(bundles + after + 1, &new, sizeof(new));
 528         list_addtail(&new.instructions[0]->link, &after_bundle_1->instructions[0]->link);
 529 }
 530
 531 /* Flip the first-two arguments of a (binary) op. Currently ALU
 532  * only, no known uses for ldst/tex */
 533
 534 void
 535 mir_flip(midgard_instruction *ins)
 536 {
 537         unsigned temp = ins->src[0];
 538         ins->src[0] = ins->src[1];
 539         ins->src[1] = temp;
 540
 541         assert(ins->type == TAG_ALU_4);
 542
 543         temp = ins->alu.src1;
 544         ins->alu.src1 = ins->alu.src2;
 545         ins->alu.src2 = temp;
 546 }
 547
 548 /* Before squashing, calculate ctx->temp_count just by observing the MIR */
 549
 550 void
 551 mir_compute_temp_count(compiler_context *ctx)
 552 {
 553         if (ctx->temp_count)
 554                 return;
 555
 556         unsigned max_dest = 0;
 557
 558         mir_foreach_instr_global(ctx, ins) {
 559                 if (ins->dest < SSA_FIXED_MINIMUM)
 560                         max_dest = MAX2(max_dest, ins->dest);
 561         }
 562
 563         ctx->temp_count = max_dest;
 564 }