src/panfrost/midgard/mir.c

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new)
  28 {
  29         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
  30                 if (ins->src[i] == old)
  31                         ins->src[i] = new;
  32         }
  33 }
  34
  35 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new)
  36 {
  37         if (ins->dest == old)
  38                 ins->dest = new;
  39 }
  40
  41 static void
  42 mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned *swizzle)
  43 {
  44         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
  45                 if (ins->src[i] != old) continue;
  46
  47                 ins->src[i] = new;
  48                 mir_compose_swizzle(ins->swizzle[i], swizzle, ins->swizzle[i]);
  49         }
  50 }
  51
  52 void
  53 mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new)
  54 {
  55         mir_foreach_instr_global(ctx, ins) {
  56                 mir_rewrite_index_src_single(ins, old, new);
  57         }
  58 }
  59
  60 void
  61 mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle)
  62 {
  63         mir_foreach_instr_global(ctx, ins) {
  64                 mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle);
  65         }
  66 }
  67
  68 void
  69 mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
  70 {
  71         mir_foreach_instr_global(ctx, ins) {
  72                 mir_rewrite_index_dst_single(ins, old, new);
  73         }
  74 }
  75
  76 void
  77 mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new)
  78 {
  79         mir_rewrite_index_src(ctx, old, new);
  80         mir_rewrite_index_dst(ctx, old, new);
  81 }
  82
  83 unsigned
  84 mir_use_count(compiler_context *ctx, unsigned value)
  85 {
  86         unsigned used_count = 0;
  87
  88         mir_foreach_instr_global(ctx, ins) {
  89                 if (mir_has_arg(ins, value))
  90                         ++used_count;
  91         }
  92
  93         return used_count;
  94 }
  95
  96 /* Checks if a value is used only once (or totally dead), which is an important
  97  * heuristic to figure out if certain optimizations are Worth It (TM) */
  98
  99 bool
 100 mir_single_use(compiler_context *ctx, unsigned value)
 101 {
 102         /* We can replicate constants in places so who cares */
 103         if (value == SSA_FIXED_REGISTER(REGISTER_CONSTANT))
 104                 return true;
 105
 106         return mir_use_count(ctx, value) <= 1;
 107 }
 108
 109 static bool
 110 mir_nontrivial_raw_mod(midgard_vector_alu_src src, bool is_int)
 111 {
 112         if (is_int)
 113                 return src.mod == midgard_int_shift;
 114         else
 115                 return src.mod;
 116 }
 117
 118 static bool
 119 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask, unsigned *swizzle)
 120 {
 121         if (mir_nontrivial_raw_mod(src, is_int)) return true;
 122
 123         /* size-conversion */
 124         if (src.half) return true;
 125
 126         for (unsigned c = 0; c < 16; ++c) {
 127                 if (!(mask & (1 << c))) continue;
 128                 if (swizzle[c] != c) return true;
 129         }
 130
 131         return false;
 132 }
 133
 134 bool
 135 mir_nontrivial_source2_mod(midgard_instruction *ins)
 136 {
 137         bool is_int = midgard_is_integer_op(ins->alu.op);
 138
 139         midgard_vector_alu_src src2 =
 140                 vector_alu_from_unsigned(ins->alu.src2);
 141
 142         return mir_nontrivial_mod(src2, is_int, ins->mask, ins->swizzle[1]);
 143 }
 144
 145 bool
 146 mir_nontrivial_source2_mod_simple(midgard_instruction *ins)
 147 {
 148         bool is_int = midgard_is_integer_op(ins->alu.op);
 149
 150         midgard_vector_alu_src src2 =
 151                 vector_alu_from_unsigned(ins->alu.src2);
 152
 153         return mir_nontrivial_raw_mod(src2, is_int) || src2.half;
 154 }
 155
 156 bool
 157 mir_nontrivial_outmod(midgard_instruction *ins)
 158 {
 159         bool is_int = midgard_is_integer_op(ins->alu.op);
 160         unsigned mod = ins->alu.outmod;
 161
 162         /* Type conversion is a sort of outmod */
 163         if (ins->alu.dest_override != midgard_dest_override_none)
 164                 return true;
 165
 166         if (is_int)
 167                 return mod != midgard_outmod_int_wrap;
 168         else
 169                 return mod != midgard_outmod_none;
 170 }
 171
 172 uint16_t
 173 mir_from_bytemask(uint16_t bytemask, unsigned bits)
 174 {
 175         unsigned value = 0;
 176         unsigned count = bits / 8;
 177
 178         for (unsigned c = 0, d = 0; c < 16; c += count, ++d) {
 179                 bool a = (bytemask & (1 << c)) != 0;
 180
 181                 for (unsigned q = c; q < count; ++q)
 182                         assert(((bytemask & (1 << q)) != 0) == a);
 183
 184                 value |= (a << d);
 185         }
 186
 187         return value;
 188 }
 189
 190 /* Rounds up a bytemask to fill a given component count. Iterate each
 191  * component, and check if any bytes in the component are masked on */
 192
 193 uint16_t
 194 mir_round_bytemask_up(uint16_t mask, unsigned bits)
 195 {
 196         unsigned bytes = bits / 8;
 197         unsigned maxmask = mask_of(bytes);
 198         unsigned channels = 16 / bytes;
 199
 200         for (unsigned c = 0; c < channels; ++c) {
 201                 unsigned submask = maxmask << (c * bytes);
 202
 203                 if (mask & submask)
 204                         mask |= submask;
 205         }
 206
 207         return mask;
 208 }
 209
 210 /* Grabs the per-byte mask of an instruction (as opposed to per-component) */
 211
 212 uint16_t
 213 mir_bytemask(midgard_instruction *ins)
 214 {
 215         unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
 216         return pan_to_bytemask(type_size, ins->mask);
 217 }
 218
 219 void
 220 mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask)
 221 {
 222         unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
 223         ins->mask = mir_from_bytemask(bytemask, type_size);
 224 }
 225
 226 /* Checks if we should use an upper destination override, rather than the lower
 227  * one in the IR. Returns zero if no, returns the bytes to shift otherwise */
 228
 229 unsigned
 230 mir_upper_override(midgard_instruction *ins)
 231 {
 232         /* If there is no override, there is no upper override, tautology */
 233         if (ins->alu.dest_override == midgard_dest_override_none)
 234                 return 0;
 235
 236         /* Make sure we didn't already lower somehow */
 237         assert(ins->alu.dest_override == midgard_dest_override_lower);
 238
 239         /* There are 16 bytes per vector, so there are (16/bytes)
 240          * components per vector. So the magic half is half of
 241          * (16/bytes), which simplifies to 8/bytes = 8 / (bits / 8) = 64 / bits
 242          * */
 243
 244         unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
 245         unsigned threshold = 64 / type_size;
 246
 247         /* How many components did we shift over? */
 248         unsigned zeroes = __builtin_ctz(ins->mask);
 249
 250         /* Did we hit the threshold? */
 251         return (zeroes >= threshold) ? threshold : 0;
 252 }
 253
 254 /* Creates a mask of the components of a node read by an instruction, by
 255  * analyzing the swizzle with respect to the instruction's mask. E.g.:
 256  *
 257  *  fadd r0.xz, r1.yyyy, r2.zwyx
 258  *
 259  * will return a mask of Z/Y for r2
 260  */
 261
 262 static uint16_t
 263 mir_bytemask_of_read_components_single(unsigned *swizzle, unsigned inmask, unsigned bits)
 264 {
 265         unsigned cmask = 0;
 266
 267         for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
 268                 if (!(inmask & (1 << c))) continue;
 269                 cmask |= (1 << swizzle[c]);
 270         }
 271
 272         return pan_to_bytemask(bits, cmask);
 273 }
 274
 275 uint16_t
 276 mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i)
 277 {
 278         if (ins->compact_branch && ins->writeout && (i == 0)) {
 279                 /* Non-ZS writeout uses all components */
 280                 if (!ins->writeout_depth && !ins->writeout_stencil)
 281                         return 0xFFFF;
 282
 283                 /* For ZS-writeout, if both Z and S are written we need two
 284                  * components, otherwise we only need one.
 285                  */
 286                 if (ins->writeout_depth && ins->writeout_stencil)
 287                         return 0xFF;
 288                 else
 289                         return 0xF;
 290         }
 291
 292         /* Conditional branches read one 32-bit component = 4 bytes (TODO: multi branch??) */
 293         if (ins->compact_branch && ins->branch.conditional && (i == 0))
 294                 return 0xF;
 295
 296         /* ALU ops act componentwise so we need to pay attention to
 297          * their mask. Texture/ldst does not so we don't clamp source
 298          * readmasks based on the writemask */
 299         unsigned qmask = (ins->type == TAG_ALU_4) ? ins->mask : ~0;
 300
 301         /* Handle dot products and things */
 302         if (ins->type == TAG_ALU_4 && !ins->compact_branch) {
 303                 unsigned props = alu_opcode_props[ins->alu.op].props;
 304
 305                 unsigned channel_override = GET_CHANNEL_COUNT(props);
 306
 307                 if (channel_override)
 308                         qmask = mask_of(channel_override);
 309         }
 310
 311         return mir_bytemask_of_read_components_single(ins->swizzle[i], qmask,
 312                 nir_alu_type_get_type_size(ins->src_types[i]));
 313 }
 314
 315 uint16_t
 316 mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node)
 317 {
 318         uint16_t mask = 0;
 319
 320         if (node == ~0)
 321                 return 0;
 322
 323         mir_foreach_src(ins, i) {
 324                 if (ins->src[i] != node) continue;
 325                 mask |= mir_bytemask_of_read_components_index(ins, i);
 326         }
 327
 328         return mask;
 329 }
 330
 331 /* Register allocation occurs after instruction scheduling, which is fine until
 332  * we start needing to spill registers and therefore insert instructions into
 333  * an already-scheduled program. We don't have to be terribly efficient about
 334  * this, since spilling is already slow. So just semantically we need to insert
 335  * the instruction into a new bundle before/after the bundle of the instruction
 336  * in question */
 337
 338 static midgard_bundle
 339 mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
 340 {
 341         midgard_instruction *u = mir_upload_ins(ctx, ins);
 342
 343         midgard_bundle bundle = {
 344                 .tag = ins.type,
 345                 .instruction_count = 1,
 346                 .instructions = { u },
 347         };
 348
 349         if (bundle.tag == TAG_ALU_4) {
 350                 assert(OP_IS_MOVE(u->alu.op));
 351                 u->unit = UNIT_VMUL;
 352
 353                 size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
 354                 bundle.padding = ~(bytes_emitted - 1) & 0xF;
 355                 bundle.control = ins.type | u->unit;
 356         }
 357
 358         return bundle;
 359 }
 360
 361 static unsigned
 362 mir_bundle_idx_for_ins(midgard_instruction *tag, midgard_block *block)
 363 {
 364         midgard_bundle *bundles =
 365                 (midgard_bundle *) block->bundles.data;
 366
 367         size_t count = (block->bundles.size / sizeof(midgard_bundle));
 368
 369         for (unsigned i = 0; i < count; ++i) {
 370                 for (unsigned j = 0; j < bundles[i].instruction_count; ++j) {
 371                         if (bundles[i].instructions[j] == tag)
 372                                 return i;
 373                 }
 374         }
 375
 376         mir_print_instruction(tag);
 377         unreachable("Instruction not scheduled in block");
 378 }
 379
 380 void
 381 mir_insert_instruction_before_scheduled(
 382         compiler_context *ctx,
 383         midgard_block *block,
 384         midgard_instruction *tag,
 385         midgard_instruction ins)
 386 {
 387         unsigned before = mir_bundle_idx_for_ins(tag, block);
 388         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 389         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 390
 391         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 392         memmove(bundles + before + 1, bundles + before, (count - before) * sizeof(midgard_bundle));
 393         midgard_bundle *before_bundle = bundles + before + 1;
 394
 395         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 396         memcpy(bundles + before, &new, sizeof(new));
 397
 398         list_addtail(&new.instructions[0]->link, &before_bundle->instructions[0]->link);
 399         block->quadword_count += midgard_tag_props[new.tag].size;
 400 }
 401
 402 void
 403 mir_insert_instruction_after_scheduled(
 404         compiler_context *ctx,
 405         midgard_block *block,
 406         midgard_instruction *tag,
 407         midgard_instruction ins)
 408 {
 409         /* We need to grow the bundles array to add our new bundle */
 410         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 411         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 412
 413         /* Find the bundle that we want to insert after */
 414         unsigned after = mir_bundle_idx_for_ins(tag, block);
 415
 416         /* All the bundles after that one, we move ahead by one */
 417         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 418         memmove(bundles + after + 2, bundles + after + 1, (count - after - 1) * sizeof(midgard_bundle));
 419         midgard_bundle *after_bundle = bundles + after;
 420
 421         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 422         memcpy(bundles + after + 1, &new, sizeof(new));
 423         list_add(&new.instructions[0]->link, &after_bundle->instructions[after_bundle->instruction_count - 1]->link);
 424         block->quadword_count += midgard_tag_props[new.tag].size;
 425 }
 426
 427 /* Flip the first-two arguments of a (binary) op. Currently ALU
 428  * only, no known uses for ldst/tex */
 429
 430 void
 431 mir_flip(midgard_instruction *ins)
 432 {
 433         unsigned temp = ins->src[0];
 434         ins->src[0] = ins->src[1];
 435         ins->src[1] = temp;
 436
 437         assert(ins->type == TAG_ALU_4);
 438
 439         temp = ins->alu.src1;
 440         ins->alu.src1 = ins->alu.src2;
 441         ins->alu.src2 = temp;
 442
 443         unsigned temp_swizzle[16];
 444         memcpy(temp_swizzle, ins->swizzle[0], sizeof(ins->swizzle[0]));
 445         memcpy(ins->swizzle[0], ins->swizzle[1], sizeof(ins->swizzle[0]));
 446         memcpy(ins->swizzle[1], temp_swizzle, sizeof(ins->swizzle[0]));
 447 }
 448
 449 /* Before squashing, calculate ctx->temp_count just by observing the MIR */
 450
 451 void
 452 mir_compute_temp_count(compiler_context *ctx)
 453 {
 454         if (ctx->temp_count)
 455                 return;
 456
 457         unsigned max_dest = 0;
 458
 459         mir_foreach_instr_global(ctx, ins) {
 460                 if (ins->dest < SSA_FIXED_MINIMUM)
 461                         max_dest = MAX2(max_dest, ins->dest + 1);
 462         }
 463
 464         ctx->temp_count = max_dest;
 465 }