src/util/u_cpu_detect.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Dennis Smit
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  20  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  **************************************************************************/
  26
  27 /**
  28  * @file
  29  * CPU feature detection.
  30  *
  31  * @author Dennis Smit
  32  * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
  33  */
  34
  35 #include "pipe/p_config.h"
  36
  37 #include "util/u_debug.h"
  38 #include "u_cpu_detect.h"
  39 #include "c11/threads.h"
  40
  41 #if defined(PIPE_ARCH_PPC)
  42 #if defined(PIPE_OS_APPLE)
  43 #include <sys/sysctl.h>
  44 #else
  45 #include <signal.h>
  46 #include <setjmp.h>
  47 #endif
  48 #endif
  49
  50 #if defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
  51 #include <sys/param.h>
  52 #include <sys/sysctl.h>
  53 #include <machine/cpu.h>
  54 #endif
  55
  56 #if defined(PIPE_OS_FREEBSD) || defined(PIPE_OS_DRAGONFLY)
  57 #include <sys/types.h>
  58 #include <sys/sysctl.h>
  59 #if __has_include(<sys/auxv.h>)
  60 #include <sys/auxv.h>
  61 #define HAVE_ELF_AUX_INFO
  62 #endif
  63 #endif
  64
  65 #if defined(PIPE_OS_LINUX)
  66 #include <signal.h>
  67 #include <fcntl.h>
  68 #include <elf.h>
  69 #endif
  70
  71 #ifdef PIPE_OS_UNIX
  72 #include <unistd.h>
  73 #endif
  74
  75 #if defined(HAS_ANDROID_CPUFEATURES)
  76 #include <cpu-features.h>
  77 #endif
  78
  79 #if defined(PIPE_OS_WINDOWS)
  80 #include <windows.h>
  81 #if defined(PIPE_CC_MSVC)
  82 #include <intrin.h>
  83 #endif
  84 #endif
  85
  86
  87 #ifdef DEBUG
  88 DEBUG_GET_ONCE_BOOL_OPTION(dump_cpu, "GALLIUM_DUMP_CPU", FALSE)
  89 #endif
  90
  91
  92 struct util_cpu_caps util_cpu_caps;
  93
  94 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
  95 static int has_cpuid(void);
  96 #endif
  97
  98
  99 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_APPLE) && !defined(PIPE_OS_LINUX)
 100 static jmp_buf  __lv_powerpc_jmpbuf;
 101 static volatile sig_atomic_t __lv_powerpc_canjump = 0;
 102
 103 static void
 104 sigill_handler(int sig)
 105 {
 106    if (!__lv_powerpc_canjump) {
 107       signal (sig, SIG_DFL);
 108       raise (sig);
 109    }
 110
 111    __lv_powerpc_canjump = 0;
 112    longjmp(__lv_powerpc_jmpbuf, 1);
 113 }
 114 #endif
 115
 116 #if defined(PIPE_ARCH_PPC)
 117 static void
 118 check_os_altivec_support(void)
 119 {
 120 #if defined(PIPE_OS_APPLE)
 121    int sels[2] = {CTL_HW, HW_VECTORUNIT};
 122    int has_vu = 0;
 123    int len = sizeof (has_vu);
 124    int err;
 125
 126    err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 127
 128    if (err == 0) {
 129       if (has_vu != 0) {
 130          util_cpu_caps.has_altivec = 1;
 131       }
 132    }
 133 #elif defined(PIPE_OS_LINUX) /* !PIPE_OS_APPLE */
 134 #if defined(PIPE_ARCH_PPC_64)
 135     Elf64_auxv_t aux;
 136 #else
 137     Elf32_auxv_t aux;
 138 #endif
 139     int fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 140     if (fd >= 0) {
 141        while (read(fd, &aux, sizeof(aux)) == sizeof(aux)) {
 142           if (aux.a_type == AT_HWCAP) {
 143              char *env_vsx = getenv("GALLIVM_VSX");
 144              uint64_t hwcap = aux.a_un.a_val;
 145              util_cpu_caps.has_altivec = (hwcap >> 28) & 1;
 146              if (!env_vsx || env_vsx[0] != '0') {
 147                 util_cpu_caps.has_vsx  = (hwcap >>  7) & 1;
 148              }
 149              break;
 150           }
 151        }
 152        close(fd);
 153     }
 154 #else /* !PIPE_OS_APPLE && !PIPE_OS_LINUX */
 155    /* not on Apple/Darwin or Linux, do it the brute-force way */
 156    /* this is borrowed from the libmpeg2 library */
 157    signal(SIGILL, sigill_handler);
 158    if (setjmp(__lv_powerpc_jmpbuf)) {
 159       signal(SIGILL, SIG_DFL);
 160    } else {
 161       boolean enable_altivec = TRUE;    /* Default: enable  if available, and if not overridden */
 162       boolean enable_vsx = TRUE;
 163 #ifdef DEBUG
 164       /* Disabling Altivec code generation is not the same as disabling VSX code generation,
 165        * which can be done simply by passing -mattr=-vsx to the LLVM compiler; cf.
 166        * lp_build_create_jit_compiler_for_module().
 167        * If you want to disable Altivec code generation, the best place to do it is here.
 168        */
 169       char *env_control = getenv("GALLIVM_ALTIVEC");    /* 1=enable (default); 0=disable */
 170       if (env_control && env_control[0] == '0') {
 171          enable_altivec = FALSE;
 172       }
 173 #endif
 174       /* VSX instructions can be explicitly enabled/disabled via GALLIVM_VSX=1 or 0 */
 175       char *env_vsx = getenv("GALLIVM_VSX");
 176       if (env_vsx && env_vsx[0] == '0') {
 177          enable_vsx = FALSE;
 178       }
 179       if (enable_altivec) {
 180          __lv_powerpc_canjump = 1;
 181
 182          __asm __volatile
 183             ("mtspr 256, %0\n\t"
 184              "vand %%v0, %%v0, %%v0"
 185              :
 186              : "r" (-1));
 187
 188          util_cpu_caps.has_altivec = 1;
 189
 190          if (enable_vsx) {
 191             __asm __volatile("xxland %vs0, %vs0, %vs0");
 192             util_cpu_caps.has_vsx = 1;
 193          }
 194          signal(SIGILL, SIG_DFL);
 195       } else {
 196          util_cpu_caps.has_altivec = 0;
 197       }
 198    }
 199 #endif /* !PIPE_OS_APPLE && !PIPE_OS_LINUX */
 200 }
 201 #endif /* PIPE_ARCH_PPC */
 202
 203
 204 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
 205 static int has_cpuid(void)
 206 {
 207 #if defined(PIPE_ARCH_X86)
 208 #if defined(PIPE_OS_GCC)
 209    int a, c;
 210
 211    __asm __volatile
 212       ("pushf\n"
 213        "popl %0\n"
 214        "movl %0, %1\n"
 215        "xorl $0x200000, %0\n"
 216        "push %0\n"
 217        "popf\n"
 218        "pushf\n"
 219        "popl %0\n"
 220        : "=a" (a), "=c" (c)
 221        :
 222        : "cc");
 223
 224    return a != c;
 225 #else
 226    /* FIXME */
 227    return 1;
 228 #endif
 229 #elif defined(PIPE_ARCH_X86_64)
 230    return 1;
 231 #else
 232    return 0;
 233 #endif
 234 }
 235
 236
 237 /**
 238  * @sa cpuid.h included in gcc-4.3 onwards.
 239  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
 240  */
 241 static inline void
 242 cpuid(uint32_t ax, uint32_t *p)
 243 {
 244 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 245    __asm __volatile (
 246      "xchgl %%ebx, %1\n\t"
 247      "cpuid\n\t"
 248      "xchgl %%ebx, %1"
 249      : "=a" (p[0]),
 250        "=S" (p[1]),
 251        "=c" (p[2]),
 252        "=d" (p[3])
 253      : "0" (ax)
 254    );
 255 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 256    __asm __volatile (
 257      "cpuid\n\t"
 258      : "=a" (p[0]),
 259        "=b" (p[1]),
 260        "=c" (p[2]),
 261        "=d" (p[3])
 262      : "0" (ax)
 263    );
 264 #elif defined(PIPE_CC_MSVC)
 265    __cpuid(p, ax);
 266 #else
 267    p[0] = 0;
 268    p[1] = 0;
 269    p[2] = 0;
 270    p[3] = 0;
 271 #endif
 272 }
 273
 274 /**
 275  * @sa cpuid.h included in gcc-4.4 onwards.
 276  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh%28v=vs.90%29.aspx
 277  */
 278 static inline void
 279 cpuid_count(uint32_t ax, uint32_t cx, uint32_t *p)
 280 {
 281 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 282    __asm __volatile (
 283      "xchgl %%ebx, %1\n\t"
 284      "cpuid\n\t"
 285      "xchgl %%ebx, %1"
 286      : "=a" (p[0]),
 287        "=S" (p[1]),
 288        "=c" (p[2]),
 289        "=d" (p[3])
 290      : "0" (ax), "2" (cx)
 291    );
 292 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 293    __asm __volatile (
 294      "cpuid\n\t"
 295      : "=a" (p[0]),
 296        "=b" (p[1]),
 297        "=c" (p[2]),
 298        "=d" (p[3])
 299      : "0" (ax), "2" (cx)
 300    );
 301 #elif defined(PIPE_CC_MSVC)
 302    __cpuidex(p, ax, cx);
 303 #else
 304    p[0] = 0;
 305    p[1] = 0;
 306    p[2] = 0;
 307    p[3] = 0;
 308 #endif
 309 }
 310
 311
 312 static inline uint64_t xgetbv(void)
 313 {
 314 #if defined(PIPE_CC_GCC)
 315    uint32_t eax, edx;
 316
 317    __asm __volatile (
 318      ".byte 0x0f, 0x01, 0xd0" // xgetbv isn't supported on gcc < 4.4
 319      : "=a"(eax),
 320        "=d"(edx)
 321      : "c"(0)
 322    );
 323
 324    return ((uint64_t)edx << 32) | eax;
 325 #elif defined(PIPE_CC_MSVC) && defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
 326    return _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
 327 #else
 328    return 0;
 329 #endif
 330 }
 331
 332
 333 #if defined(PIPE_ARCH_X86)
 334 PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
 335 {
 336    struct {
 337       uint32_t pad1[7];
 338       uint32_t mxcsr_mask;
 339       uint32_t pad2[128-8];
 340    } PIPE_ALIGN_VAR(16) fxarea;
 341
 342    fxarea.mxcsr_mask = 0;
 343 #if defined(PIPE_CC_GCC)
 344    __asm __volatile ("fxsave %0" : "+m" (fxarea));
 345 #elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL)
 346    _fxsave(&fxarea);
 347 #else
 348    fxarea.mxcsr_mask = 0;
 349 #endif
 350    return !!(fxarea.mxcsr_mask & (1 << 6));
 351 }
 352 #endif
 353
 354 #endif /* X86 or X86_64 */
 355
 356 #if defined(PIPE_ARCH_ARM)
 357 static void
 358 check_os_arm_support(void)
 359 {
 360    /*
 361     * On Android, the cpufeatures library is preferred way of checking
 362     * CPU capabilities. However, it is not available for standalone Mesa
 363     * builds, i.e. when Android build system (Android.mk-based) is not
 364     * used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
 365     * have a separate macro that only gets enabled from respective Android.mk.
 366     */
 367 #if defined(__ARM_NEON) || defined(__ARM_NEON__)
 368    util_cpu_caps.has_neon = 1;
 369 #elif defined(PIPE_OS_FREEBSD) && defined(HAVE_ELF_AUX_INFO)
 370    unsigned long hwcap = 0;
 371    elf_aux_info(AT_HWCAP, &hwcap, sizeof(hwcap));
 372    if (hwcap & HWCAP_NEON)
 373       util_cpu_caps.has_neon = 1;
 374 #elif defined(HAS_ANDROID_CPUFEATURES)
 375    AndroidCpuFamily cpu_family = android_getCpuFamily();
 376    uint64_t cpu_features = android_getCpuFeatures();
 377
 378    if (cpu_family == ANDROID_CPU_FAMILY_ARM) {
 379       if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)
 380          util_cpu_caps.has_neon = 1;
 381    }
 382 #elif defined(PIPE_OS_LINUX)
 383     Elf32_auxv_t aux;
 384     int fd;
 385
 386     fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC);
 387     if (fd >= 0) {
 388        while (read(fd, &aux, sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
 389           if (aux.a_type == AT_HWCAP) {
 390              uint32_t hwcap = aux.a_un.a_val;
 391
 392              util_cpu_caps.has_neon = (hwcap >> 12) & 1;
 393              break;
 394           }
 395        }
 396        close (fd);
 397     }
 398 #endif /* PIPE_OS_LINUX */
 399 }
 400
 401 #elif defined(PIPE_ARCH_AARCH64)
 402 static void
 403 check_os_arm_support(void)
 404 {
 405     util_cpu_caps.has_neon = true;
 406 }
 407 #endif /* PIPE_ARCH_ARM || PIPE_ARCH_AARCH64 */
 408
 409 static void
 410 get_cpu_topology(void)
 411 {
 412    /* Default. This is correct if L3 is not present or there is only one. */
 413    util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
 414
 415 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 416    /* AMD Zen */
 417    if (util_cpu_caps.x86_cpu_type == 0x17) {
 418       uint32_t regs[4];
 419
 420       /* Query the L3 cache topology information. */
 421       cpuid_count(0x8000001D, 3, regs);
 422       unsigned cache_level = (regs[0] >> 5) & 0x7;
 423       unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
 424
 425       if (cache_level == 3)
 426          util_cpu_caps.cores_per_L3 = cores_per_cache;
 427    }
 428 #endif
 429 }
 430
 431 static void
 432 util_cpu_detect_once(void)
 433 {
 434    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
 435
 436    /* Count the number of CPUs in system */
 437 #if defined(PIPE_OS_WINDOWS)
 438    {
 439       SYSTEM_INFO system_info;
 440       GetSystemInfo(&system_info);
 441       util_cpu_caps.nr_cpus = system_info.dwNumberOfProcessors;
 442    }
 443 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
 444    util_cpu_caps.nr_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 445    if (util_cpu_caps.nr_cpus == ~0)
 446       util_cpu_caps.nr_cpus = 1;
 447 #elif defined(PIPE_OS_BSD)
 448    {
 449       int mib[2], ncpu;
 450       int len;
 451
 452       mib[0] = CTL_HW;
 453       mib[1] = HW_NCPU;
 454
 455       len = sizeof (ncpu);
 456       sysctl(mib, 2, &ncpu, &len, NULL, 0);
 457       util_cpu_caps.nr_cpus = ncpu;
 458    }
 459 #else
 460    util_cpu_caps.nr_cpus = 1;
 461 #endif
 462
 463    /* Make the fallback cacheline size nonzero so that it can be
 464     * safely passed to align().
 465     */
 466    util_cpu_caps.cacheline = sizeof(void *);
 467
 468 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 469    if (has_cpuid()) {
 470       uint32_t regs[4];
 471       uint32_t regs2[4];
 472
 473       util_cpu_caps.cacheline = 32;
 474
 475       /* Get max cpuid level */
 476       cpuid(0x00000000, regs);
 477
 478       if (regs[0] >= 0x00000001) {
 479          unsigned int cacheline;
 480
 481          cpuid (0x00000001, regs2);
 482
 483          util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf;
 484          /* Add "extended family". */
 485          if (util_cpu_caps.x86_cpu_type == 0xf)
 486              util_cpu_caps.x86_cpu_type += ((regs2[0] >> 20) & 0xff);
 487
 488          /* general feature flags */
 489          util_cpu_caps.has_tsc    = (regs2[3] >>  4) & 1; /* 0x0000010 */
 490          util_cpu_caps.has_mmx    = (regs2[3] >> 23) & 1; /* 0x0800000 */
 491          util_cpu_caps.has_sse    = (regs2[3] >> 25) & 1; /* 0x2000000 */
 492          util_cpu_caps.has_sse2   = (regs2[3] >> 26) & 1; /* 0x4000000 */
 493          util_cpu_caps.has_sse3   = (regs2[2] >>  0) & 1; /* 0x0000001 */
 494          util_cpu_caps.has_ssse3  = (regs2[2] >>  9) & 1; /* 0x0000020 */
 495          util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1;
 496          util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1;
 497          util_cpu_caps.has_popcnt = (regs2[2] >> 23) & 1;
 498          util_cpu_caps.has_avx    = ((regs2[2] >> 28) & 1) && // AVX
 499                                     ((regs2[2] >> 27) & 1) && // OSXSAVE
 500                                     ((xgetbv() & 6) == 6);    // XMM & YMM
 501          util_cpu_caps.has_f16c   = ((regs2[2] >> 29) & 1) && util_cpu_caps.has_avx;
 502          util_cpu_caps.has_fma    = ((regs2[2] >> 12) & 1) && util_cpu_caps.has_avx;
 503          util_cpu_caps.has_mmx2   = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
 504 #if defined(PIPE_ARCH_X86_64)
 505          util_cpu_caps.has_daz = 1;
 506 #else
 507          util_cpu_caps.has_daz = util_cpu_caps.has_sse3 ||
 508             (util_cpu_caps.has_sse2 && sse2_has_daz());
 509 #endif
 510
 511          cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
 512          if (cacheline > 0)
 513             util_cpu_caps.cacheline = cacheline;
 514       }
 515       if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) {
 516          uint32_t regs7[4];
 517          cpuid_count(0x00000007, 0x00000000, regs7);
 518          util_cpu_caps.has_avx2 = (regs7[1] >> 5) & 1;
 519       }
 520
 521       // check for avx512
 522       if (((regs2[2] >> 27) & 1) && // OSXSAVE
 523           (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS
 524           ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS
 525          uint32_t regs3[4];
 526          cpuid_count(0x00000007, 0x00000000, regs3);
 527          util_cpu_caps.has_avx512f    = (regs3[1] >> 16) & 1;
 528          util_cpu_caps.has_avx512dq   = (regs3[1] >> 17) & 1;
 529          util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1;
 530          util_cpu_caps.has_avx512pf   = (regs3[1] >> 26) & 1;
 531          util_cpu_caps.has_avx512er   = (regs3[1] >> 27) & 1;
 532          util_cpu_caps.has_avx512cd   = (regs3[1] >> 28) & 1;
 533          util_cpu_caps.has_avx512bw   = (regs3[1] >> 30) & 1;
 534          util_cpu_caps.has_avx512vl   = (regs3[1] >> 31) & 1;
 535          util_cpu_caps.has_avx512vbmi = (regs3[2] >>  1) & 1;
 536       }
 537
 538       if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) {
 539          /* GenuineIntel */
 540          util_cpu_caps.has_intel = 1;
 541       }
 542
 543       cpuid(0x80000000, regs);
 544
 545       if (regs[0] >= 0x80000001) {
 546
 547          cpuid(0x80000001, regs2);
 548
 549          util_cpu_caps.has_mmx  |= (regs2[3] >> 23) & 1;
 550          util_cpu_caps.has_mmx2 |= (regs2[3] >> 22) & 1;
 551          util_cpu_caps.has_3dnow = (regs2[3] >> 31) & 1;
 552          util_cpu_caps.has_3dnow_ext = (regs2[3] >> 30) & 1;
 553
 554          util_cpu_caps.has_xop = util_cpu_caps.has_avx &&
 555                                  ((regs2[2] >> 11) & 1);
 556       }
 557
 558       if (regs[0] >= 0x80000006) {
 559          /* should we really do this if the clflush size above worked? */
 560          unsigned int cacheline;
 561          cpuid(0x80000006, regs2);
 562          cacheline = regs2[2] & 0xFF;
 563          if (cacheline > 0)
 564             util_cpu_caps.cacheline = cacheline;
 565       }
 566
 567       if (!util_cpu_caps.has_sse) {
 568          util_cpu_caps.has_sse2 = 0;
 569          util_cpu_caps.has_sse3 = 0;
 570          util_cpu_caps.has_ssse3 = 0;
 571          util_cpu_caps.has_sse4_1 = 0;
 572       }
 573    }
 574 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 575
 576 #if defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_AARCH64)
 577    check_os_arm_support();
 578 #endif
 579
 580 #if defined(PIPE_ARCH_PPC)
 581    check_os_altivec_support();
 582 #endif /* PIPE_ARCH_PPC */
 583
 584    get_cpu_topology();
 585
 586 #ifdef DEBUG
 587    if (debug_get_option_dump_cpu()) {
 588       debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
 589
 590       debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps.x86_cpu_type);
 591       debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
 592
 593       debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
 594       debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
 595       debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
 596       debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps.has_sse);
 597       debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps.has_sse2);
 598       debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
 599       debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
 600       debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
 601       debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps.has_sse4_2);
 602       debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps.has_avx);
 603       debug_printf("util_cpu_caps.has_avx2 = %u\n", util_cpu_caps.has_avx2);
 604       debug_printf("util_cpu_caps.has_f16c = %u\n", util_cpu_caps.has_f16c);
 605       debug_printf("util_cpu_caps.has_popcnt = %u\n", util_cpu_caps.has_popcnt);
 606       debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
 607       debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
 608       debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
 609       debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
 610       debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx);
 611       debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
 612       debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
 613       debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
 614       debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
 615       debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
 616       debug_printf("util_cpu_caps.has_avx512pf = %u\n", util_cpu_caps.has_avx512pf);
 617       debug_printf("util_cpu_caps.has_avx512er = %u\n", util_cpu_caps.has_avx512er);
 618       debug_printf("util_cpu_caps.has_avx512cd = %u\n", util_cpu_caps.has_avx512cd);
 619       debug_printf("util_cpu_caps.has_avx512bw = %u\n", util_cpu_caps.has_avx512bw);
 620       debug_printf("util_cpu_caps.has_avx512vl = %u\n", util_cpu_caps.has_avx512vl);
 621       debug_printf("util_cpu_caps.has_avx512vbmi = %u\n", util_cpu_caps.has_avx512vbmi);
 622    }
 623 #endif
 624 }
 625
 626 static once_flag cpu_once_flag = ONCE_FLAG_INIT;
 627
 628 void
 629 util_cpu_detect(void)
 630 {
 631    call_once(&cpu_once_flag, util_cpu_detect_once);
 632 }