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anv: pCreateInfo->pApplicationInfo parameter to vkCreateInstance may be NULL
[mesa.git] / src / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "nir/spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 const uint32_t *data =
127 spec_info->pData + spec_info->pMapEntries[i].offset;
128 assert((const void *)(data + 1) <=
129 spec_info->pData + spec_info->dataSize);
130
131 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
132 spec_entries[i].data = *data;
133 }
134 }
135
136 entry_point = spirv_to_nir(spirv, module->size / 4,
137 spec_entries, num_spec_entries,
138 stage, entrypoint_name, nir_options);
139 nir = entry_point->shader;
140 assert(nir->stage == stage);
141 nir_validate_shader(nir);
142
143 free(spec_entries);
144
145 nir_lower_returns(nir);
146 nir_validate_shader(nir);
147
148 nir_inline_functions(nir);
149 nir_validate_shader(nir);
150
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
153 if (func != entry_point)
154 exec_node_remove(&func->node);
155 }
156 assert(exec_list_length(&nir->functions) == 1);
157 entry_point->name = ralloc_strdup(entry_point, "main");
158
159 nir_remove_dead_variables(nir, nir_var_shader_in);
160 nir_remove_dead_variables(nir, nir_var_shader_out);
161 nir_remove_dead_variables(nir, nir_var_system_value);
162 nir_validate_shader(nir);
163
164 nir_lower_outputs_to_temporaries(entry_point->shader, entry_point);
165
166 nir_lower_system_values(nir);
167 nir_validate_shader(nir);
168 }
169
170 /* Vulkan uses the separate-shader linking model */
171 nir->info.separate_shader = true;
172
173 nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
174
175 nir_shader_gather_info(nir, entry_point->impl);
176
177 uint32_t indirect_mask = 0;
178 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
179 indirect_mask |= (1 << nir_var_shader_in);
180 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
181 indirect_mask |= 1 << nir_var_local;
182
183 nir_lower_indirect_derefs(nir, indirect_mask);
184
185 return nir;
186 }
187
188 void anv_DestroyPipeline(
189 VkDevice _device,
190 VkPipeline _pipeline,
191 const VkAllocationCallbacks* pAllocator)
192 {
193 ANV_FROM_HANDLE(anv_device, device, _device);
194 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
195
196 anv_reloc_list_finish(&pipeline->batch_relocs,
197 pAllocator ? pAllocator : &device->alloc);
198 if (pipeline->blend_state.map)
199 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
200 anv_free2(&device->alloc, pAllocator, pipeline);
201 }
202
203 static const uint32_t vk_to_gen_primitive_type[] = {
204 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
205 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
206 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
207 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
208 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
209 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
214 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
215 };
216
217 static void
218 populate_sampler_prog_key(const struct brw_device_info *devinfo,
219 struct brw_sampler_prog_key_data *key)
220 {
221 /* XXX: Handle texture swizzle on HSW- */
222 for (int i = 0; i < MAX_SAMPLERS; i++) {
223 /* Assume color sampler, no swizzling. (Works for BDW+) */
224 key->swizzles[i] = SWIZZLE_XYZW;
225 }
226 }
227
228 static void
229 populate_vs_prog_key(const struct brw_device_info *devinfo,
230 struct brw_vs_prog_key *key)
231 {
232 memset(key, 0, sizeof(*key));
233
234 populate_sampler_prog_key(devinfo, &key->tex);
235
236 /* XXX: Handle vertex input work-arounds */
237
238 /* XXX: Handle sampler_prog_key */
239 }
240
241 static void
242 populate_gs_prog_key(const struct brw_device_info *devinfo,
243 struct brw_gs_prog_key *key)
244 {
245 memset(key, 0, sizeof(*key));
246
247 populate_sampler_prog_key(devinfo, &key->tex);
248 }
249
250 static void
251 populate_wm_prog_key(const struct brw_device_info *devinfo,
252 const VkGraphicsPipelineCreateInfo *info,
253 const struct anv_graphics_pipeline_create_info *extra,
254 struct brw_wm_prog_key *key)
255 {
256 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
257
258 memset(key, 0, sizeof(*key));
259
260 populate_sampler_prog_key(devinfo, &key->tex);
261
262 /* TODO: Fill out key->input_slots_valid */
263
264 /* Vulkan doesn't specify a default */
265 key->high_quality_derivatives = false;
266
267 /* XXX Vulkan doesn't appear to specify */
268 key->clamp_fragment_color = false;
269
270 /* Vulkan always specifies upper-left coordinates */
271 key->drawable_height = 0;
272 key->render_to_fbo = false;
273
274 if (extra && extra->color_attachment_count >= 0) {
275 key->nr_color_regions = extra->color_attachment_count;
276 } else {
277 key->nr_color_regions =
278 render_pass->subpasses[info->subpass].color_count;
279 }
280
281 key->replicate_alpha = key->nr_color_regions > 1 &&
282 info->pMultisampleState &&
283 info->pMultisampleState->alphaToCoverageEnable;
284
285 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
286 /* We should probably pull this out of the shader, but it's fairly
287 * harmless to compute it and then let dead-code take care of it.
288 */
289 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
290 if (key->persample_shading)
291 key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
292
293 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
294 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
295 }
296 }
297
298 static void
299 populate_cs_prog_key(const struct brw_device_info *devinfo,
300 struct brw_cs_prog_key *key)
301 {
302 memset(key, 0, sizeof(*key));
303
304 populate_sampler_prog_key(devinfo, &key->tex);
305 }
306
307 static nir_shader *
308 anv_pipeline_compile(struct anv_pipeline *pipeline,
309 struct anv_shader_module *module,
310 const char *entrypoint,
311 gl_shader_stage stage,
312 const VkSpecializationInfo *spec_info,
313 struct brw_stage_prog_data *prog_data)
314 {
315 const struct brw_compiler *compiler =
316 pipeline->device->instance->physicalDevice.compiler;
317
318 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
319 module, entrypoint, stage,
320 spec_info);
321 if (nir == NULL)
322 return NULL;
323
324 anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
325
326 /* Figure out the number of parameters */
327 prog_data->nr_params = 0;
328
329 if (nir->num_uniforms > 0) {
330 /* If the shader uses any push constants at all, we'll just give
331 * them the maximum possible number
332 */
333 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
334 }
335
336 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
337 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
338
339 if (pipeline->layout && pipeline->layout->stage[stage].image_count > 0)
340 prog_data->nr_params += pipeline->layout->stage[stage].image_count *
341 BRW_IMAGE_PARAM_SIZE;
342
343 if (prog_data->nr_params > 0) {
344 /* XXX: I think we're leaking this */
345 prog_data->param = (const union gl_constant_value **)
346 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
347
348 /* We now set the param values to be offsets into a
349 * anv_push_constant_data structure. Since the compiler doesn't
350 * actually dereference any of the gl_constant_value pointers in the
351 * params array, it doesn't really matter what we put here.
352 */
353 struct anv_push_constants *null_data = NULL;
354 if (nir->num_uniforms > 0) {
355 /* Fill out the push constants section of the param array */
356 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
357 prog_data->param[i] = (const union gl_constant_value *)
358 &null_data->client_data[i * sizeof(float)];
359 }
360 }
361
362 /* Set up dynamic offsets */
363 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
364
365 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
366 if (pipeline->layout)
367 anv_nir_apply_pipeline_layout(nir, prog_data, pipeline->layout);
368
369 /* All binding table offsets provided by apply_pipeline_layout() are
370 * relative to the start of the bindint table (plus MAX_RTS for VS).
371 */
372 unsigned bias;
373 switch (stage) {
374 case MESA_SHADER_FRAGMENT:
375 bias = MAX_RTS;
376 break;
377 case MESA_SHADER_COMPUTE:
378 bias = 1;
379 break;
380 default:
381 bias = 0;
382 break;
383 }
384 prog_data->binding_table.size_bytes = 0;
385 prog_data->binding_table.texture_start = bias;
386 prog_data->binding_table.ubo_start = bias;
387 prog_data->binding_table.ssbo_start = bias;
388 prog_data->binding_table.image_start = bias;
389
390 /* Finish the optimization and compilation process */
391 if (nir->stage != MESA_SHADER_VERTEX &&
392 nir->stage != MESA_SHADER_TESS_CTRL &&
393 nir->stage != MESA_SHADER_TESS_EVAL) {
394 nir = brw_nir_lower_io(nir, &pipeline->device->info,
395 compiler->scalar_stage[stage], false, NULL);
396 }
397
398 /* nir_lower_io will only handle the push constants; we need to set this
399 * to the full number of possible uniforms.
400 */
401 nir->num_uniforms = prog_data->nr_params * 4;
402
403 return nir;
404 }
405
406 static void
407 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
408 gl_shader_stage stage,
409 struct brw_stage_prog_data *prog_data)
410 {
411 struct brw_device_info *devinfo = &pipeline->device->info;
412 uint32_t max_threads[] = {
413 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
414 [MESA_SHADER_TESS_CTRL] = 0,
415 [MESA_SHADER_TESS_EVAL] = 0,
416 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
417 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
418 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
419 };
420
421 pipeline->prog_data[stage] = prog_data;
422 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
423 pipeline->scratch_start[stage] = pipeline->total_scratch;
424 pipeline->total_scratch =
425 align_u32(pipeline->total_scratch, 1024) +
426 prog_data->total_scratch * max_threads[stage];
427 }
428
429 static VkResult
430 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
431 struct anv_pipeline_cache *cache,
432 const VkGraphicsPipelineCreateInfo *info,
433 struct anv_shader_module *module,
434 const char *entrypoint,
435 const VkSpecializationInfo *spec_info)
436 {
437 const struct brw_compiler *compiler =
438 pipeline->device->instance->physicalDevice.compiler;
439 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
440 struct brw_vs_prog_key key;
441 uint32_t kernel;
442 unsigned char sha1[20], *hash;
443
444 populate_vs_prog_key(&pipeline->device->info, &key);
445
446 if (module->size > 0) {
447 hash = sha1;
448 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
449 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
450 } else {
451 hash = NULL;
452 }
453
454 if (module->size == 0 || kernel == NO_KERNEL) {
455 memset(prog_data, 0, sizeof(*prog_data));
456
457 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
458 MESA_SHADER_VERTEX, spec_info,
459 &prog_data->base.base);
460 if (nir == NULL)
461 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
462
463 void *mem_ctx = ralloc_context(NULL);
464
465 if (module->nir == NULL)
466 ralloc_steal(mem_ctx, nir);
467
468 prog_data->inputs_read = nir->info.inputs_read;
469 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
470 pipeline->writes_point_size = true;
471
472 brw_compute_vue_map(&pipeline->device->info,
473 &prog_data->base.vue_map,
474 nir->info.outputs_written,
475 nir->info.separate_shader);
476
477 unsigned code_size;
478 const unsigned *shader_code =
479 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
480 NULL, false, -1, &code_size, NULL);
481 if (shader_code == NULL) {
482 ralloc_free(mem_ctx);
483 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
484 }
485
486 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
487 shader_code, code_size,
488 prog_data, sizeof(*prog_data));
489 ralloc_free(mem_ctx);
490 }
491
492 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
493 pipeline->vs_simd8 = kernel;
494 pipeline->vs_vec4 = NO_KERNEL;
495 } else {
496 pipeline->vs_simd8 = NO_KERNEL;
497 pipeline->vs_vec4 = kernel;
498 }
499
500 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
501 &prog_data->base.base);
502
503 return VK_SUCCESS;
504 }
505
506 static VkResult
507 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
508 struct anv_pipeline_cache *cache,
509 const VkGraphicsPipelineCreateInfo *info,
510 struct anv_shader_module *module,
511 const char *entrypoint,
512 const VkSpecializationInfo *spec_info)
513 {
514 const struct brw_compiler *compiler =
515 pipeline->device->instance->physicalDevice.compiler;
516 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
517 struct brw_gs_prog_key key;
518 uint32_t kernel;
519 unsigned char sha1[20], *hash;
520
521 populate_gs_prog_key(&pipeline->device->info, &key);
522
523 if (module->size > 0) {
524 hash = sha1;
525 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
526 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
527 } else {
528 hash = NULL;
529 }
530
531 if (module->size == 0 || kernel == NO_KERNEL) {
532 memset(prog_data, 0, sizeof(*prog_data));
533
534 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
535 MESA_SHADER_GEOMETRY, spec_info,
536 &prog_data->base.base);
537 if (nir == NULL)
538 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
539
540 void *mem_ctx = ralloc_context(NULL);
541
542 if (module->nir == NULL)
543 ralloc_steal(mem_ctx, nir);
544
545 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
546 pipeline->writes_point_size = true;
547
548 brw_compute_vue_map(&pipeline->device->info,
549 &prog_data->base.vue_map,
550 nir->info.outputs_written,
551 nir->info.separate_shader);
552
553 unsigned code_size;
554 const unsigned *shader_code =
555 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
556 NULL, -1, &code_size, NULL);
557 if (shader_code == NULL) {
558 ralloc_free(mem_ctx);
559 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
560 }
561
562 /* TODO: SIMD8 GS */
563 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
564 shader_code, code_size,
565 prog_data, sizeof(*prog_data));
566
567 ralloc_free(mem_ctx);
568 }
569
570 pipeline->gs_kernel = kernel;
571
572 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
573 &prog_data->base.base);
574
575 return VK_SUCCESS;
576 }
577
578 static VkResult
579 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
580 struct anv_pipeline_cache *cache,
581 const VkGraphicsPipelineCreateInfo *info,
582 const struct anv_graphics_pipeline_create_info *extra,
583 struct anv_shader_module *module,
584 const char *entrypoint,
585 const VkSpecializationInfo *spec_info)
586 {
587 const struct brw_compiler *compiler =
588 pipeline->device->instance->physicalDevice.compiler;
589 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
590 struct brw_wm_prog_key key;
591 uint32_t kernel;
592 unsigned char sha1[20], *hash;
593
594 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
595
596 if (pipeline->use_repclear)
597 key.nr_color_regions = 1;
598
599 if (module->size > 0) {
600 hash = sha1;
601 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
602 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
603 } else {
604 hash = NULL;
605 }
606
607 if (module->size == 0 || kernel == NO_KERNEL) {
608 memset(prog_data, 0, sizeof(*prog_data));
609
610 prog_data->binding_table.render_target_start = 0;
611
612 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
613 MESA_SHADER_FRAGMENT, spec_info,
614 &prog_data->base);
615 if (nir == NULL)
616 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
617
618 void *mem_ctx = ralloc_context(NULL);
619
620 if (module->nir == NULL)
621 ralloc_steal(mem_ctx, nir);
622
623 unsigned code_size;
624 const unsigned *shader_code =
625 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
626 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
627 if (shader_code == NULL) {
628 ralloc_free(mem_ctx);
629 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
630 }
631
632 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
633 shader_code, code_size,
634 prog_data, sizeof(*prog_data));
635
636 ralloc_free(mem_ctx);
637 }
638
639 if (prog_data->no_8)
640 pipeline->ps_simd8 = NO_KERNEL;
641 else
642 pipeline->ps_simd8 = kernel;
643
644 if (prog_data->no_8 || prog_data->prog_offset_16) {
645 pipeline->ps_simd16 = kernel + prog_data->prog_offset_16;
646 } else {
647 pipeline->ps_simd16 = NO_KERNEL;
648 }
649
650 pipeline->ps_ksp2 = 0;
651 pipeline->ps_grf_start2 = 0;
652 if (pipeline->ps_simd8 != NO_KERNEL) {
653 pipeline->ps_ksp0 = pipeline->ps_simd8;
654 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
655 if (pipeline->ps_simd16 != NO_KERNEL) {
656 pipeline->ps_ksp2 = pipeline->ps_simd16;
657 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
658 }
659 } else if (pipeline->ps_simd16 != NO_KERNEL) {
660 pipeline->ps_ksp0 = pipeline->ps_simd16;
661 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
662 }
663
664 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
665 &prog_data->base);
666
667 return VK_SUCCESS;
668 }
669
670 VkResult
671 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
672 struct anv_pipeline_cache *cache,
673 const VkComputePipelineCreateInfo *info,
674 struct anv_shader_module *module,
675 const char *entrypoint,
676 const VkSpecializationInfo *spec_info)
677 {
678 const struct brw_compiler *compiler =
679 pipeline->device->instance->physicalDevice.compiler;
680 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
681 struct brw_cs_prog_key key;
682 uint32_t kernel;
683 unsigned char sha1[20], *hash;
684
685 populate_cs_prog_key(&pipeline->device->info, &key);
686
687 if (module->size > 0) {
688 hash = sha1;
689 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
690 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
691 } else {
692 hash = NULL;
693 }
694
695 if (module->size == 0 || kernel == NO_KERNEL) {
696 memset(prog_data, 0, sizeof(*prog_data));
697
698 prog_data->binding_table.work_groups_start = 0;
699
700 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
701 MESA_SHADER_COMPUTE, spec_info,
702 &prog_data->base);
703 if (nir == NULL)
704 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
705
706 prog_data->base.total_shared = nir->num_shared;
707
708 void *mem_ctx = ralloc_context(NULL);
709
710 if (module->nir == NULL)
711 ralloc_steal(mem_ctx, nir);
712
713 unsigned code_size;
714 const unsigned *shader_code =
715 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
716 -1, &code_size, NULL);
717 if (shader_code == NULL) {
718 ralloc_free(mem_ctx);
719 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
720 }
721
722 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
723 shader_code, code_size,
724 prog_data, sizeof(*prog_data));
725 ralloc_free(mem_ctx);
726 }
727
728 pipeline->cs_simd = kernel;
729
730 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
731 &prog_data->base);
732
733 return VK_SUCCESS;
734 }
735
736 static const int gen8_push_size = 32 * 1024;
737
738 static void
739 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
740 {
741 const struct brw_device_info *devinfo = &pipeline->device->info;
742 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
743 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
744 unsigned vs_entry_size_bytes = vs_size * 64;
745 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
746 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
747 unsigned gs_entry_size_bytes = gs_size * 64;
748
749 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
750 *
751 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
752 * Allocation Size is less than 9 512-bit URB entries.
753 *
754 * Similar text exists for GS.
755 */
756 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
757 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
758
759 /* URB allocations must be done in 8k chunks. */
760 unsigned chunk_size_bytes = 8192;
761
762 /* Determine the size of the URB in chunks. */
763 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
764
765 /* Reserve space for push constants */
766 unsigned push_constant_bytes = gen8_push_size;
767 unsigned push_constant_chunks =
768 push_constant_bytes / chunk_size_bytes;
769
770 /* Initially, assign each stage the minimum amount of URB space it needs,
771 * and make a note of how much additional space it "wants" (the amount of
772 * additional space it could actually make use of).
773 */
774
775 /* VS has a lower limit on the number of URB entries */
776 unsigned vs_chunks =
777 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
778 chunk_size_bytes) / chunk_size_bytes;
779 unsigned vs_wants =
780 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
781 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
782
783 unsigned gs_chunks = 0;
784 unsigned gs_wants = 0;
785 if (gs_present) {
786 /* There are two constraints on the minimum amount of URB space we can
787 * allocate:
788 *
789 * (1) We need room for at least 2 URB entries, since we always operate
790 * the GS in DUAL_OBJECT mode.
791 *
792 * (2) We can't allocate less than nr_gs_entries_granularity.
793 */
794 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
795 chunk_size_bytes) / chunk_size_bytes;
796 gs_wants =
797 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
798 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
799 }
800
801 /* There should always be enough URB space to satisfy the minimum
802 * requirements of each stage.
803 */
804 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
805 assert(total_needs <= urb_chunks);
806
807 /* Mete out remaining space (if any) in proportion to "wants". */
808 unsigned total_wants = vs_wants + gs_wants;
809 unsigned remaining_space = urb_chunks - total_needs;
810 if (remaining_space > total_wants)
811 remaining_space = total_wants;
812 if (remaining_space > 0) {
813 unsigned vs_additional = (unsigned)
814 round(vs_wants * (((double) remaining_space) / total_wants));
815 vs_chunks += vs_additional;
816 remaining_space -= vs_additional;
817 gs_chunks += remaining_space;
818 }
819
820 /* Sanity check that we haven't over-allocated. */
821 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
822
823 /* Finally, compute the number of entries that can fit in the space
824 * allocated to each stage.
825 */
826 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
827 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
828
829 /* Since we rounded up when computing *_wants, this may be slightly more
830 * than the maximum allowed amount, so correct for that.
831 */
832 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
833 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
834
835 /* Ensure that we program a multiple of the granularity. */
836 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
837 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
838
839 /* Finally, sanity check to make sure we have at least the minimum number
840 * of entries needed for each stage.
841 */
842 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
843 if (gs_present)
844 assert(nr_gs_entries >= 2);
845
846 /* Lay out the URB in the following order:
847 * - push constants
848 * - VS
849 * - GS
850 */
851 pipeline->urb.vs_start = push_constant_chunks;
852 pipeline->urb.vs_size = vs_size;
853 pipeline->urb.nr_vs_entries = nr_vs_entries;
854
855 pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
856 pipeline->urb.gs_size = gs_size;
857 pipeline->urb.nr_gs_entries = nr_gs_entries;
858 }
859
860 static void
861 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
862 const VkGraphicsPipelineCreateInfo *pCreateInfo)
863 {
864 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
865 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
866 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
867
868 pipeline->dynamic_state = default_dynamic_state;
869
870 if (pCreateInfo->pDynamicState) {
871 /* Remove all of the states that are marked as dynamic */
872 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
873 for (uint32_t s = 0; s < count; s++)
874 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
875 }
876
877 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
878
879 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
880 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
881 typed_memcpy(dynamic->viewport.viewports,
882 pCreateInfo->pViewportState->pViewports,
883 pCreateInfo->pViewportState->viewportCount);
884 }
885
886 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
887 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
888 typed_memcpy(dynamic->scissor.scissors,
889 pCreateInfo->pViewportState->pScissors,
890 pCreateInfo->pViewportState->scissorCount);
891 }
892
893 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
894 assert(pCreateInfo->pRasterizationState);
895 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
896 }
897
898 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
899 assert(pCreateInfo->pRasterizationState);
900 dynamic->depth_bias.bias =
901 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
902 dynamic->depth_bias.clamp =
903 pCreateInfo->pRasterizationState->depthBiasClamp;
904 dynamic->depth_bias.slope =
905 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
906 }
907
908 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
909 assert(pCreateInfo->pColorBlendState);
910 typed_memcpy(dynamic->blend_constants,
911 pCreateInfo->pColorBlendState->blendConstants, 4);
912 }
913
914 /* If there is no depthstencil attachment, then don't read
915 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
916 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
917 * no need to override the depthstencil defaults in
918 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
919 *
920 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
921 *
922 * pDepthStencilState [...] may only be NULL if renderPass and subpass
923 * specify a subpass that has no depth/stencil attachment.
924 */
925 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
926 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
927 assert(pCreateInfo->pDepthStencilState);
928 dynamic->depth_bounds.min =
929 pCreateInfo->pDepthStencilState->minDepthBounds;
930 dynamic->depth_bounds.max =
931 pCreateInfo->pDepthStencilState->maxDepthBounds;
932 }
933
934 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
935 assert(pCreateInfo->pDepthStencilState);
936 dynamic->stencil_compare_mask.front =
937 pCreateInfo->pDepthStencilState->front.compareMask;
938 dynamic->stencil_compare_mask.back =
939 pCreateInfo->pDepthStencilState->back.compareMask;
940 }
941
942 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
943 assert(pCreateInfo->pDepthStencilState);
944 dynamic->stencil_write_mask.front =
945 pCreateInfo->pDepthStencilState->front.writeMask;
946 dynamic->stencil_write_mask.back =
947 pCreateInfo->pDepthStencilState->back.writeMask;
948 }
949
950 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
951 assert(pCreateInfo->pDepthStencilState);
952 dynamic->stencil_reference.front =
953 pCreateInfo->pDepthStencilState->front.reference;
954 dynamic->stencil_reference.back =
955 pCreateInfo->pDepthStencilState->back.reference;
956 }
957 }
958
959 pipeline->dynamic_state_mask = states;
960 }
961
962 static void
963 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
964 {
965 struct anv_render_pass *renderpass = NULL;
966 struct anv_subpass *subpass = NULL;
967
968 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
969 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
970 * 4.2 Graphics Pipeline.
971 */
972 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
973
974 renderpass = anv_render_pass_from_handle(info->renderPass);
975 assert(renderpass);
976
977 if (renderpass != &anv_meta_dummy_renderpass) {
978 assert(info->subpass < renderpass->subpass_count);
979 subpass = &renderpass->subpasses[info->subpass];
980 }
981
982 assert(info->stageCount >= 1);
983 assert(info->pVertexInputState);
984 assert(info->pInputAssemblyState);
985 assert(info->pViewportState);
986 assert(info->pRasterizationState);
987
988 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
989 assert(info->pDepthStencilState);
990
991 if (subpass && subpass->color_count > 0)
992 assert(info->pColorBlendState);
993
994 for (uint32_t i = 0; i < info->stageCount; ++i) {
995 switch (info->pStages[i].stage) {
996 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
997 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
998 assert(info->pTessellationState);
999 break;
1000 default:
1001 break;
1002 }
1003 }
1004 }
1005
1006 VkResult
1007 anv_pipeline_init(struct anv_pipeline *pipeline,
1008 struct anv_device *device,
1009 struct anv_pipeline_cache *cache,
1010 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1011 const struct anv_graphics_pipeline_create_info *extra,
1012 const VkAllocationCallbacks *alloc)
1013 {
1014 VkResult result;
1015
1016 anv_validate {
1017 anv_pipeline_validate_create_info(pCreateInfo);
1018 }
1019
1020 if (alloc == NULL)
1021 alloc = &device->alloc;
1022
1023 pipeline->device = device;
1024 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1025
1026 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1027 if (result != VK_SUCCESS)
1028 return result;
1029
1030 pipeline->batch.alloc = alloc;
1031 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1032 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1033 pipeline->batch.relocs = &pipeline->batch_relocs;
1034
1035 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1036
1037 if (pCreateInfo->pTessellationState)
1038 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1039
1040 pipeline->use_repclear = extra && extra->use_repclear;
1041 pipeline->writes_point_size = false;
1042
1043 /* When we free the pipeline, we detect stages based on the NULL status
1044 * of various prog_data pointers. Make them NULL by default.
1045 */
1046 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1047 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1048
1049 pipeline->vs_simd8 = NO_KERNEL;
1050 pipeline->vs_vec4 = NO_KERNEL;
1051 pipeline->gs_kernel = NO_KERNEL;
1052 pipeline->ps_ksp0 = NO_KERNEL;
1053
1054 pipeline->active_stages = 0;
1055 pipeline->total_scratch = 0;
1056
1057 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1058 ANV_FROM_HANDLE(anv_shader_module, module,
1059 pCreateInfo->pStages[i].module);
1060
1061 switch (pCreateInfo->pStages[i].stage) {
1062 case VK_SHADER_STAGE_VERTEX_BIT:
1063 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo, module,
1064 pCreateInfo->pStages[i].pName,
1065 pCreateInfo->pStages[i].pSpecializationInfo);
1066 break;
1067 case VK_SHADER_STAGE_GEOMETRY_BIT:
1068 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo, module,
1069 pCreateInfo->pStages[i].pName,
1070 pCreateInfo->pStages[i].pSpecializationInfo);
1071 break;
1072 case VK_SHADER_STAGE_FRAGMENT_BIT:
1073 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra, module,
1074 pCreateInfo->pStages[i].pName,
1075 pCreateInfo->pStages[i].pSpecializationInfo);
1076 break;
1077 default:
1078 anv_finishme("Unsupported shader stage");
1079 }
1080 }
1081
1082 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1083 /* Vertex is only optional if disable_vs is set */
1084 assert(extra->disable_vs);
1085 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1086 }
1087
1088 gen7_compute_urb_partition(pipeline);
1089
1090 const VkPipelineVertexInputStateCreateInfo *vi_info =
1091 pCreateInfo->pVertexInputState;
1092
1093 uint64_t inputs_read;
1094 if (extra && extra->disable_vs) {
1095 /* If the VS is disabled, just assume the user knows what they're
1096 * doing and apply the layout blindly. This can only come from
1097 * meta, so this *should* be safe.
1098 */
1099 inputs_read = ~0ull;
1100 } else {
1101 inputs_read = pipeline->vs_prog_data.inputs_read;
1102 }
1103
1104 pipeline->vb_used = 0;
1105 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1106 const VkVertexInputAttributeDescription *desc =
1107 &vi_info->pVertexAttributeDescriptions[i];
1108
1109 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1110 pipeline->vb_used |= 1 << desc->binding;
1111 }
1112
1113 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1114 const VkVertexInputBindingDescription *desc =
1115 &vi_info->pVertexBindingDescriptions[i];
1116
1117 pipeline->binding_stride[desc->binding] = desc->stride;
1118
1119 /* Step rate is programmed per vertex element (attribute), not
1120 * binding. Set up a map of which bindings step per instance, for
1121 * reference by vertex element setup. */
1122 switch (desc->inputRate) {
1123 default:
1124 case VK_VERTEX_INPUT_RATE_VERTEX:
1125 pipeline->instancing_enable[desc->binding] = false;
1126 break;
1127 case VK_VERTEX_INPUT_RATE_INSTANCE:
1128 pipeline->instancing_enable[desc->binding] = true;
1129 break;
1130 }
1131 }
1132
1133 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1134 pCreateInfo->pInputAssemblyState;
1135 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1136 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1137
1138 if (extra && extra->use_rectlist)
1139 pipeline->topology = _3DPRIM_RECTLIST;
1140
1141 while (anv_block_pool_size(&device->scratch_block_pool) <
1142 pipeline->total_scratch)
1143 anv_block_pool_alloc(&device->scratch_block_pool);
1144
1145 return VK_SUCCESS;
1146 }
1147
1148 VkResult
1149 anv_graphics_pipeline_create(
1150 VkDevice _device,
1151 VkPipelineCache _cache,
1152 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1153 const struct anv_graphics_pipeline_create_info *extra,
1154 const VkAllocationCallbacks *pAllocator,
1155 VkPipeline *pPipeline)
1156 {
1157 ANV_FROM_HANDLE(anv_device, device, _device);
1158 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1159
1160 if (cache == NULL)
1161 cache = &device->default_pipeline_cache;
1162
1163 switch (device->info.gen) {
1164 case 7:
1165 if (device->info.is_haswell)
1166 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1167 else
1168 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1169 case 8:
1170 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1171 case 9:
1172 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1173 default:
1174 unreachable("unsupported gen\n");
1175 }
1176 }
1177
1178 VkResult anv_CreateGraphicsPipelines(
1179 VkDevice _device,
1180 VkPipelineCache pipelineCache,
1181 uint32_t count,
1182 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1183 const VkAllocationCallbacks* pAllocator,
1184 VkPipeline* pPipelines)
1185 {
1186 VkResult result = VK_SUCCESS;
1187
1188 unsigned i = 0;
1189 for (; i < count; i++) {
1190 result = anv_graphics_pipeline_create(_device,
1191 pipelineCache,
1192 &pCreateInfos[i],
1193 NULL, pAllocator, &pPipelines[i]);
1194 if (result != VK_SUCCESS) {
1195 for (unsigned j = 0; j < i; j++) {
1196 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1197 }
1198
1199 return result;
1200 }
1201 }
1202
1203 return VK_SUCCESS;
1204 }
1205
1206 static VkResult anv_compute_pipeline_create(
1207 VkDevice _device,
1208 VkPipelineCache _cache,
1209 const VkComputePipelineCreateInfo* pCreateInfo,
1210 const VkAllocationCallbacks* pAllocator,
1211 VkPipeline* pPipeline)
1212 {
1213 ANV_FROM_HANDLE(anv_device, device, _device);
1214 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1215
1216 if (cache == NULL)
1217 cache = &device->default_pipeline_cache;
1218
1219 switch (device->info.gen) {
1220 case 7:
1221 if (device->info.is_haswell)
1222 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1223 else
1224 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1225 case 8:
1226 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1227 case 9:
1228 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1229 default:
1230 unreachable("unsupported gen\n");
1231 }
1232 }
1233
1234 VkResult anv_CreateComputePipelines(
1235 VkDevice _device,
1236 VkPipelineCache pipelineCache,
1237 uint32_t count,
1238 const VkComputePipelineCreateInfo* pCreateInfos,
1239 const VkAllocationCallbacks* pAllocator,
1240 VkPipeline* pPipelines)
1241 {
1242 VkResult result = VK_SUCCESS;
1243
1244 unsigned i = 0;
1245 for (; i < count; i++) {
1246 result = anv_compute_pipeline_create(_device, pipelineCache,
1247 &pCreateInfos[i],
1248 pAllocator, &pPipelines[i]);
1249 if (result != VK_SUCCESS) {
1250 for (unsigned j = 0; j < i; j++) {
1251 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1252 }
1253
1254 return result;
1255 }
1256 }
1257
1258 return VK_SUCCESS;
1259 }