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anv/pipeline: Set size of shared variables in prog_data
[mesa.git] / src / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "brw_nir.h"
32 #include "anv_nir.h"
33 #include "glsl/nir/spirv/nir_spirv.h"
34
35 /* Needed for SWIZZLE macros */
36 #include "program/prog_instruction.h"
37
38 // Shader functions
39
40 VkResult anv_CreateShaderModule(
41 VkDevice _device,
42 const VkShaderModuleCreateInfo* pCreateInfo,
43 const VkAllocationCallbacks* pAllocator,
44 VkShaderModule* pShaderModule)
45 {
46 ANV_FROM_HANDLE(anv_device, device, _device);
47 struct anv_shader_module *module;
48
49 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
50 assert(pCreateInfo->flags == 0);
51
52 module = anv_alloc2(&device->alloc, pAllocator,
53 sizeof(*module) + pCreateInfo->codeSize, 8,
54 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
55 if (module == NULL)
56 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
57
58 module->nir = NULL;
59 module->size = pCreateInfo->codeSize;
60 memcpy(module->data, pCreateInfo->pCode, module->size);
61
62 *pShaderModule = anv_shader_module_to_handle(module);
63
64 return VK_SUCCESS;
65 }
66
67 void anv_DestroyShaderModule(
68 VkDevice _device,
69 VkShaderModule _module,
70 const VkAllocationCallbacks* pAllocator)
71 {
72 ANV_FROM_HANDLE(anv_device, device, _device);
73 ANV_FROM_HANDLE(anv_shader_module, module, _module);
74
75 anv_free2(&device->alloc, pAllocator, module);
76 }
77
78 #define SPIR_V_MAGIC_NUMBER 0x07230203
79
80 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
81 * we can't do that yet because we don't have the ability to copy nir.
82 */
83 static nir_shader *
84 anv_shader_compile_to_nir(struct anv_device *device,
85 struct anv_shader_module *module,
86 const char *entrypoint_name,
87 gl_shader_stage stage,
88 const VkSpecializationInfo *spec_info)
89 {
90 if (strcmp(entrypoint_name, "main") != 0) {
91 anv_finishme("Multiple shaders per module not really supported");
92 }
93
94 const struct brw_compiler *compiler =
95 device->instance->physicalDevice.compiler;
96 const nir_shader_compiler_options *nir_options =
97 compiler->glsl_compiler_options[stage].NirOptions;
98
99 nir_shader *nir;
100 nir_function *entry_point;
101 if (module->nir) {
102 /* Some things such as our meta clear/blit code will give us a NIR
103 * shader directly. In that case, we just ignore the SPIR-V entirely
104 * and just use the NIR shader */
105 nir = module->nir;
106 nir->options = nir_options;
107 nir_validate_shader(nir);
108
109 assert(exec_list_length(&nir->functions) == 1);
110 struct exec_node *node = exec_list_get_head(&nir->functions);
111 entry_point = exec_node_data(nir_function, node, node);
112 } else {
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 const uint32_t *data =
124 spec_info->pData + spec_info->pMapEntries[i].offset;
125 assert((const void *)(data + 1) <=
126 spec_info->pData + spec_info->dataSize);
127
128 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
129 spec_entries[i].data = *data;
130 }
131 }
132
133 entry_point = spirv_to_nir(spirv, module->size / 4,
134 spec_entries, num_spec_entries,
135 stage, entrypoint_name, nir_options);
136 nir = entry_point->shader;
137 assert(nir->stage == stage);
138 nir_validate_shader(nir);
139
140 free(spec_entries);
141
142 nir_lower_returns(nir);
143 nir_validate_shader(nir);
144
145 nir_inline_functions(nir);
146 nir_validate_shader(nir);
147
148 /* Pick off the single entrypoint that we want */
149 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
150 if (func != entry_point)
151 exec_node_remove(&func->node);
152 }
153 assert(exec_list_length(&nir->functions) == 1);
154 entry_point->name = ralloc_strdup(entry_point, "main");
155
156 nir_remove_dead_variables(nir, nir_var_shader_in);
157 nir_remove_dead_variables(nir, nir_var_shader_out);
158 nir_remove_dead_variables(nir, nir_var_system_value);
159 nir_validate_shader(nir);
160
161 nir_lower_outputs_to_temporaries(entry_point->shader, entry_point);
162
163 nir_lower_system_values(nir);
164 nir_validate_shader(nir);
165 }
166
167 /* Vulkan uses the separate-shader linking model */
168 nir->info.separate_shader = true;
169
170 nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
171
172 nir_shader_gather_info(nir, entry_point->impl);
173
174 uint32_t indirect_mask = (1 << nir_var_shader_in);
175 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
176 indirect_mask |= 1 << nir_var_local;
177
178 nir_lower_indirect_derefs(nir, indirect_mask);
179
180 return nir;
181 }
182
183 void
184 anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
185 struct anv_device *device)
186 {
187 cache->device = device;
188 anv_state_stream_init(&cache->program_stream,
189 &device->instruction_block_pool);
190 pthread_mutex_init(&cache->mutex, NULL);
191 }
192
193 void
194 anv_pipeline_cache_finish(struct anv_pipeline_cache *cache)
195 {
196 anv_state_stream_finish(&cache->program_stream);
197 pthread_mutex_destroy(&cache->mutex);
198 }
199
200 static uint32_t
201 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
202 const void *data, size_t size)
203 {
204 pthread_mutex_lock(&cache->mutex);
205
206 struct anv_state state =
207 anv_state_stream_alloc(&cache->program_stream, size, 64);
208
209 pthread_mutex_unlock(&cache->mutex);
210
211 assert(size < cache->program_stream.block_pool->block_size);
212
213 memcpy(state.map, data, size);
214
215 if (!cache->device->info.has_llc)
216 anv_state_clflush(state);
217
218 return state.offset;
219 }
220
221 VkResult anv_CreatePipelineCache(
222 VkDevice _device,
223 const VkPipelineCacheCreateInfo* pCreateInfo,
224 const VkAllocationCallbacks* pAllocator,
225 VkPipelineCache* pPipelineCache)
226 {
227 ANV_FROM_HANDLE(anv_device, device, _device);
228 struct anv_pipeline_cache *cache;
229
230 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO);
231 assert(pCreateInfo->flags == 0);
232
233 cache = anv_alloc2(&device->alloc, pAllocator,
234 sizeof(*cache), 8,
235 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
236 if (cache == NULL)
237 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
238
239 anv_pipeline_cache_init(cache, device);
240
241 *pPipelineCache = anv_pipeline_cache_to_handle(cache);
242
243 return VK_SUCCESS;
244 }
245
246 void anv_DestroyPipelineCache(
247 VkDevice _device,
248 VkPipelineCache _cache,
249 const VkAllocationCallbacks* pAllocator)
250 {
251 ANV_FROM_HANDLE(anv_device, device, _device);
252 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
253
254 anv_pipeline_cache_finish(cache);
255
256 anv_free2(&device->alloc, pAllocator, cache);
257 }
258
259 VkResult anv_GetPipelineCacheData(
260 VkDevice device,
261 VkPipelineCache pipelineCache,
262 size_t* pDataSize,
263 void* pData)
264 {
265 *pDataSize = 0;
266
267 return VK_SUCCESS;
268 }
269
270 VkResult anv_MergePipelineCaches(
271 VkDevice device,
272 VkPipelineCache destCache,
273 uint32_t srcCacheCount,
274 const VkPipelineCache* pSrcCaches)
275 {
276 stub_return(VK_SUCCESS);
277 }
278
279 void anv_DestroyPipeline(
280 VkDevice _device,
281 VkPipeline _pipeline,
282 const VkAllocationCallbacks* pAllocator)
283 {
284 ANV_FROM_HANDLE(anv_device, device, _device);
285 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
286
287 anv_reloc_list_finish(&pipeline->batch_relocs,
288 pAllocator ? pAllocator : &device->alloc);
289 if (pipeline->blend_state.map)
290 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
291 anv_free2(&device->alloc, pAllocator, pipeline);
292 }
293
294 static const uint32_t vk_to_gen_primitive_type[] = {
295 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
296 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
297 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
298 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
299 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
300 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
301 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
302 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
303 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
304 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
305 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
306 };
307
308 static void
309 populate_sampler_prog_key(const struct brw_device_info *devinfo,
310 struct brw_sampler_prog_key_data *key)
311 {
312 /* XXX: Handle texture swizzle on HSW- */
313 for (int i = 0; i < MAX_SAMPLERS; i++) {
314 /* Assume color sampler, no swizzling. (Works for BDW+) */
315 key->swizzles[i] = SWIZZLE_XYZW;
316 }
317 }
318
319 static void
320 populate_vs_prog_key(const struct brw_device_info *devinfo,
321 struct brw_vs_prog_key *key)
322 {
323 memset(key, 0, sizeof(*key));
324
325 populate_sampler_prog_key(devinfo, &key->tex);
326
327 /* XXX: Handle vertex input work-arounds */
328
329 /* XXX: Handle sampler_prog_key */
330 }
331
332 static void
333 populate_gs_prog_key(const struct brw_device_info *devinfo,
334 struct brw_gs_prog_key *key)
335 {
336 memset(key, 0, sizeof(*key));
337
338 populate_sampler_prog_key(devinfo, &key->tex);
339 }
340
341 static void
342 populate_wm_prog_key(const struct brw_device_info *devinfo,
343 const VkGraphicsPipelineCreateInfo *info,
344 const struct anv_graphics_pipeline_create_info *extra,
345 struct brw_wm_prog_key *key)
346 {
347 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
348
349 memset(key, 0, sizeof(*key));
350
351 populate_sampler_prog_key(devinfo, &key->tex);
352
353 /* TODO: Fill out key->input_slots_valid */
354
355 /* Vulkan doesn't specify a default */
356 key->high_quality_derivatives = false;
357
358 /* XXX Vulkan doesn't appear to specify */
359 key->clamp_fragment_color = false;
360
361 /* Vulkan always specifies upper-left coordinates */
362 key->drawable_height = 0;
363 key->render_to_fbo = false;
364
365 if (extra && extra->color_attachment_count >= 0) {
366 key->nr_color_regions = extra->color_attachment_count;
367 } else {
368 key->nr_color_regions =
369 render_pass->subpasses[info->subpass].color_count;
370 }
371
372 key->replicate_alpha = key->nr_color_regions > 1 &&
373 info->pMultisampleState &&
374 info->pMultisampleState->alphaToCoverageEnable;
375
376 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
377 /* We should probably pull this out of the shader, but it's fairly
378 * harmless to compute it and then let dead-code take care of it.
379 */
380 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
381 if (key->persample_shading)
382 key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
383
384 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
385 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
386 }
387 }
388
389 static void
390 populate_cs_prog_key(const struct brw_device_info *devinfo,
391 struct brw_cs_prog_key *key)
392 {
393 memset(key, 0, sizeof(*key));
394
395 populate_sampler_prog_key(devinfo, &key->tex);
396 }
397
398 static nir_shader *
399 anv_pipeline_compile(struct anv_pipeline *pipeline,
400 struct anv_shader_module *module,
401 const char *entrypoint,
402 gl_shader_stage stage,
403 const VkSpecializationInfo *spec_info,
404 struct brw_stage_prog_data *prog_data)
405 {
406 const struct brw_compiler *compiler =
407 pipeline->device->instance->physicalDevice.compiler;
408
409 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
410 module, entrypoint, stage,
411 spec_info);
412 if (nir == NULL)
413 return NULL;
414
415 anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
416
417 /* Figure out the number of parameters */
418 prog_data->nr_params = 0;
419
420 if (nir->num_uniforms > 0) {
421 /* If the shader uses any push constants at all, we'll just give
422 * them the maximum possible number
423 */
424 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
425 }
426
427 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
428 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
429
430 if (pipeline->layout && pipeline->layout->stage[stage].image_count > 0)
431 prog_data->nr_params += pipeline->layout->stage[stage].image_count *
432 BRW_IMAGE_PARAM_SIZE;
433
434 if (prog_data->nr_params > 0) {
435 /* XXX: I think we're leaking this */
436 prog_data->param = (const union gl_constant_value **)
437 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
438
439 /* We now set the param values to be offsets into a
440 * anv_push_constant_data structure. Since the compiler doesn't
441 * actually dereference any of the gl_constant_value pointers in the
442 * params array, it doesn't really matter what we put here.
443 */
444 struct anv_push_constants *null_data = NULL;
445 if (nir->num_uniforms > 0) {
446 /* Fill out the push constants section of the param array */
447 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
448 prog_data->param[i] = (const union gl_constant_value *)
449 &null_data->client_data[i * sizeof(float)];
450 }
451 }
452
453 /* Set up dynamic offsets */
454 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
455
456 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
457 if (pipeline->layout)
458 anv_nir_apply_pipeline_layout(nir, prog_data, pipeline->layout);
459
460 /* All binding table offsets provided by apply_pipeline_layout() are
461 * relative to the start of the bindint table (plus MAX_RTS for VS).
462 */
463 unsigned bias;
464 switch (stage) {
465 case MESA_SHADER_FRAGMENT:
466 bias = MAX_RTS;
467 break;
468 case MESA_SHADER_COMPUTE:
469 bias = 1;
470 break;
471 default:
472 bias = 0;
473 break;
474 }
475 prog_data->binding_table.size_bytes = 0;
476 prog_data->binding_table.texture_start = bias;
477 prog_data->binding_table.ubo_start = bias;
478 prog_data->binding_table.ssbo_start = bias;
479 prog_data->binding_table.image_start = bias;
480
481 /* Finish the optimization and compilation process */
482 nir = brw_nir_lower_io(nir, &pipeline->device->info,
483 compiler->scalar_stage[stage]);
484
485 /* nir_lower_io will only handle the push constants; we need to set this
486 * to the full number of possible uniforms.
487 */
488 nir->num_uniforms = prog_data->nr_params * 4;
489
490 return nir;
491 }
492
493 static void
494 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
495 gl_shader_stage stage,
496 struct brw_stage_prog_data *prog_data)
497 {
498 struct brw_device_info *devinfo = &pipeline->device->info;
499 uint32_t max_threads[] = {
500 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
501 [MESA_SHADER_TESS_CTRL] = 0,
502 [MESA_SHADER_TESS_EVAL] = 0,
503 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
504 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
505 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
506 };
507
508 pipeline->prog_data[stage] = prog_data;
509 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
510 pipeline->scratch_start[stage] = pipeline->total_scratch;
511 pipeline->total_scratch =
512 align_u32(pipeline->total_scratch, 1024) +
513 prog_data->total_scratch * max_threads[stage];
514 }
515
516 static VkResult
517 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
518 struct anv_pipeline_cache *cache,
519 const VkGraphicsPipelineCreateInfo *info,
520 struct anv_shader_module *module,
521 const char *entrypoint,
522 const VkSpecializationInfo *spec_info)
523 {
524 const struct brw_compiler *compiler =
525 pipeline->device->instance->physicalDevice.compiler;
526 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
527 struct brw_vs_prog_key key;
528
529 populate_vs_prog_key(&pipeline->device->info, &key);
530
531 /* TODO: Look up shader in cache */
532
533 memset(prog_data, 0, sizeof(*prog_data));
534
535 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
536 MESA_SHADER_VERTEX, spec_info,
537 &prog_data->base.base);
538 if (nir == NULL)
539 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
540
541 void *mem_ctx = ralloc_context(NULL);
542
543 if (module->nir == NULL)
544 ralloc_steal(mem_ctx, nir);
545
546 prog_data->inputs_read = nir->info.inputs_read;
547 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
548 pipeline->writes_point_size = true;
549
550 brw_compute_vue_map(&pipeline->device->info,
551 &prog_data->base.vue_map,
552 nir->info.outputs_written,
553 nir->info.separate_shader);
554
555 unsigned code_size;
556 const unsigned *shader_code =
557 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
558 NULL, false, -1, &code_size, NULL);
559 if (shader_code == NULL) {
560 ralloc_free(mem_ctx);
561 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
562 }
563
564 const uint32_t offset =
565 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
566 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
567 pipeline->vs_simd8 = offset;
568 pipeline->vs_vec4 = NO_KERNEL;
569 } else {
570 pipeline->vs_simd8 = NO_KERNEL;
571 pipeline->vs_vec4 = offset;
572 }
573
574 ralloc_free(mem_ctx);
575
576 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
577 &prog_data->base.base);
578
579 return VK_SUCCESS;
580 }
581
582 static VkResult
583 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
584 struct anv_pipeline_cache *cache,
585 const VkGraphicsPipelineCreateInfo *info,
586 struct anv_shader_module *module,
587 const char *entrypoint,
588 const VkSpecializationInfo *spec_info)
589 {
590 const struct brw_compiler *compiler =
591 pipeline->device->instance->physicalDevice.compiler;
592 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
593 struct brw_gs_prog_key key;
594
595 populate_gs_prog_key(&pipeline->device->info, &key);
596
597 /* TODO: Look up shader in cache */
598
599 memset(prog_data, 0, sizeof(*prog_data));
600
601 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
602 MESA_SHADER_GEOMETRY, spec_info,
603 &prog_data->base.base);
604 if (nir == NULL)
605 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
606
607 void *mem_ctx = ralloc_context(NULL);
608
609 if (module->nir == NULL)
610 ralloc_steal(mem_ctx, nir);
611
612 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
613 pipeline->writes_point_size = true;
614
615 brw_compute_vue_map(&pipeline->device->info,
616 &prog_data->base.vue_map,
617 nir->info.outputs_written,
618 nir->info.separate_shader);
619
620 unsigned code_size;
621 const unsigned *shader_code =
622 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
623 NULL, -1, &code_size, NULL);
624 if (shader_code == NULL) {
625 ralloc_free(mem_ctx);
626 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
627 }
628
629 /* TODO: SIMD8 GS */
630 pipeline->gs_kernel =
631 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
632 pipeline->gs_vertex_count = nir->info.gs.vertices_in;
633
634 ralloc_free(mem_ctx);
635
636 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
637 &prog_data->base.base);
638
639 return VK_SUCCESS;
640 }
641
642 static VkResult
643 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
644 struct anv_pipeline_cache *cache,
645 const VkGraphicsPipelineCreateInfo *info,
646 const struct anv_graphics_pipeline_create_info *extra,
647 struct anv_shader_module *module,
648 const char *entrypoint,
649 const VkSpecializationInfo *spec_info)
650 {
651 const struct brw_compiler *compiler =
652 pipeline->device->instance->physicalDevice.compiler;
653 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
654 struct brw_wm_prog_key key;
655
656 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
657
658 if (pipeline->use_repclear)
659 key.nr_color_regions = 1;
660
661 /* TODO: Look up shader in cache */
662
663 memset(prog_data, 0, sizeof(*prog_data));
664
665 prog_data->binding_table.render_target_start = 0;
666
667 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
668 MESA_SHADER_FRAGMENT, spec_info,
669 &prog_data->base);
670 if (nir == NULL)
671 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
672
673 void *mem_ctx = ralloc_context(NULL);
674
675 if (module->nir == NULL)
676 ralloc_steal(mem_ctx, nir);
677
678 unsigned code_size;
679 const unsigned *shader_code =
680 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
681 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
682 if (shader_code == NULL) {
683 ralloc_free(mem_ctx);
684 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
685 }
686
687 uint32_t offset =
688 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
689 if (prog_data->no_8)
690 pipeline->ps_simd8 = NO_KERNEL;
691 else
692 pipeline->ps_simd8 = offset;
693
694 if (prog_data->no_8 || prog_data->prog_offset_16) {
695 pipeline->ps_simd16 = offset + prog_data->prog_offset_16;
696 } else {
697 pipeline->ps_simd16 = NO_KERNEL;
698 }
699
700 pipeline->ps_ksp2 = 0;
701 pipeline->ps_grf_start2 = 0;
702 if (pipeline->ps_simd8 != NO_KERNEL) {
703 pipeline->ps_ksp0 = pipeline->ps_simd8;
704 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
705 if (pipeline->ps_simd16 != NO_KERNEL) {
706 pipeline->ps_ksp2 = pipeline->ps_simd16;
707 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
708 }
709 } else if (pipeline->ps_simd16 != NO_KERNEL) {
710 pipeline->ps_ksp0 = pipeline->ps_simd16;
711 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
712 }
713
714 ralloc_free(mem_ctx);
715
716 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
717 &prog_data->base);
718
719 return VK_SUCCESS;
720 }
721
722 VkResult
723 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
724 struct anv_pipeline_cache *cache,
725 const VkComputePipelineCreateInfo *info,
726 struct anv_shader_module *module,
727 const char *entrypoint,
728 const VkSpecializationInfo *spec_info)
729 {
730 const struct brw_compiler *compiler =
731 pipeline->device->instance->physicalDevice.compiler;
732 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
733 struct brw_cs_prog_key key;
734
735 populate_cs_prog_key(&pipeline->device->info, &key);
736
737 /* TODO: Look up shader in cache */
738
739 memset(prog_data, 0, sizeof(*prog_data));
740
741 prog_data->binding_table.work_groups_start = 0;
742
743 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
744 MESA_SHADER_COMPUTE, spec_info,
745 &prog_data->base);
746 if (nir == NULL)
747 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
748
749 prog_data->base.total_shared = nir->num_shared;
750
751 void *mem_ctx = ralloc_context(NULL);
752
753 if (module->nir == NULL)
754 ralloc_steal(mem_ctx, nir);
755
756 unsigned code_size;
757 const unsigned *shader_code =
758 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
759 -1, &code_size, NULL);
760 if (shader_code == NULL) {
761 ralloc_free(mem_ctx);
762 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
763 }
764
765 pipeline->cs_simd =
766 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
767 ralloc_free(mem_ctx);
768
769 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
770 &prog_data->base);
771
772 return VK_SUCCESS;
773 }
774
775 static const int gen8_push_size = 32 * 1024;
776
777 static void
778 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
779 {
780 const struct brw_device_info *devinfo = &pipeline->device->info;
781 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
782 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
783 unsigned vs_entry_size_bytes = vs_size * 64;
784 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
785 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
786 unsigned gs_entry_size_bytes = gs_size * 64;
787
788 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
789 *
790 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
791 * Allocation Size is less than 9 512-bit URB entries.
792 *
793 * Similar text exists for GS.
794 */
795 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
796 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
797
798 /* URB allocations must be done in 8k chunks. */
799 unsigned chunk_size_bytes = 8192;
800
801 /* Determine the size of the URB in chunks. */
802 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
803
804 /* Reserve space for push constants */
805 unsigned push_constant_bytes = gen8_push_size;
806 unsigned push_constant_chunks =
807 push_constant_bytes / chunk_size_bytes;
808
809 /* Initially, assign each stage the minimum amount of URB space it needs,
810 * and make a note of how much additional space it "wants" (the amount of
811 * additional space it could actually make use of).
812 */
813
814 /* VS has a lower limit on the number of URB entries */
815 unsigned vs_chunks =
816 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
817 chunk_size_bytes) / chunk_size_bytes;
818 unsigned vs_wants =
819 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
820 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
821
822 unsigned gs_chunks = 0;
823 unsigned gs_wants = 0;
824 if (gs_present) {
825 /* There are two constraints on the minimum amount of URB space we can
826 * allocate:
827 *
828 * (1) We need room for at least 2 URB entries, since we always operate
829 * the GS in DUAL_OBJECT mode.
830 *
831 * (2) We can't allocate less than nr_gs_entries_granularity.
832 */
833 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
834 chunk_size_bytes) / chunk_size_bytes;
835 gs_wants =
836 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
837 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
838 }
839
840 /* There should always be enough URB space to satisfy the minimum
841 * requirements of each stage.
842 */
843 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
844 assert(total_needs <= urb_chunks);
845
846 /* Mete out remaining space (if any) in proportion to "wants". */
847 unsigned total_wants = vs_wants + gs_wants;
848 unsigned remaining_space = urb_chunks - total_needs;
849 if (remaining_space > total_wants)
850 remaining_space = total_wants;
851 if (remaining_space > 0) {
852 unsigned vs_additional = (unsigned)
853 round(vs_wants * (((double) remaining_space) / total_wants));
854 vs_chunks += vs_additional;
855 remaining_space -= vs_additional;
856 gs_chunks += remaining_space;
857 }
858
859 /* Sanity check that we haven't over-allocated. */
860 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
861
862 /* Finally, compute the number of entries that can fit in the space
863 * allocated to each stage.
864 */
865 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
866 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
867
868 /* Since we rounded up when computing *_wants, this may be slightly more
869 * than the maximum allowed amount, so correct for that.
870 */
871 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
872 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
873
874 /* Ensure that we program a multiple of the granularity. */
875 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
876 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
877
878 /* Finally, sanity check to make sure we have at least the minimum number
879 * of entries needed for each stage.
880 */
881 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
882 if (gs_present)
883 assert(nr_gs_entries >= 2);
884
885 /* Lay out the URB in the following order:
886 * - push constants
887 * - VS
888 * - GS
889 */
890 pipeline->urb.vs_start = push_constant_chunks;
891 pipeline->urb.vs_size = vs_size;
892 pipeline->urb.nr_vs_entries = nr_vs_entries;
893
894 pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
895 pipeline->urb.gs_size = gs_size;
896 pipeline->urb.nr_gs_entries = nr_gs_entries;
897 }
898
899 static void
900 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
901 const VkGraphicsPipelineCreateInfo *pCreateInfo)
902 {
903 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
904 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
905 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
906
907 pipeline->dynamic_state = default_dynamic_state;
908
909 if (pCreateInfo->pDynamicState) {
910 /* Remove all of the states that are marked as dynamic */
911 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
912 for (uint32_t s = 0; s < count; s++)
913 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
914 }
915
916 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
917
918 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
919 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
920 typed_memcpy(dynamic->viewport.viewports,
921 pCreateInfo->pViewportState->pViewports,
922 pCreateInfo->pViewportState->viewportCount);
923 }
924
925 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
926 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
927 typed_memcpy(dynamic->scissor.scissors,
928 pCreateInfo->pViewportState->pScissors,
929 pCreateInfo->pViewportState->scissorCount);
930 }
931
932 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
933 assert(pCreateInfo->pRasterizationState);
934 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
935 }
936
937 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
938 assert(pCreateInfo->pRasterizationState);
939 dynamic->depth_bias.bias =
940 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
941 dynamic->depth_bias.clamp =
942 pCreateInfo->pRasterizationState->depthBiasClamp;
943 dynamic->depth_bias.slope =
944 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
945 }
946
947 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
948 assert(pCreateInfo->pColorBlendState);
949 typed_memcpy(dynamic->blend_constants,
950 pCreateInfo->pColorBlendState->blendConstants, 4);
951 }
952
953 /* If there is no depthstencil attachment, then don't read
954 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
955 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
956 * no need to override the depthstencil defaults in
957 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
958 *
959 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
960 *
961 * pDepthStencilState [...] may only be NULL if renderPass and subpass
962 * specify a subpass that has no depth/stencil attachment.
963 */
964 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
965 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
966 assert(pCreateInfo->pDepthStencilState);
967 dynamic->depth_bounds.min =
968 pCreateInfo->pDepthStencilState->minDepthBounds;
969 dynamic->depth_bounds.max =
970 pCreateInfo->pDepthStencilState->maxDepthBounds;
971 }
972
973 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
974 assert(pCreateInfo->pDepthStencilState);
975 dynamic->stencil_compare_mask.front =
976 pCreateInfo->pDepthStencilState->front.compareMask;
977 dynamic->stencil_compare_mask.back =
978 pCreateInfo->pDepthStencilState->back.compareMask;
979 }
980
981 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
982 assert(pCreateInfo->pDepthStencilState);
983 dynamic->stencil_write_mask.front =
984 pCreateInfo->pDepthStencilState->front.writeMask;
985 dynamic->stencil_write_mask.back =
986 pCreateInfo->pDepthStencilState->back.writeMask;
987 }
988
989 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
990 assert(pCreateInfo->pDepthStencilState);
991 dynamic->stencil_reference.front =
992 pCreateInfo->pDepthStencilState->front.reference;
993 dynamic->stencil_reference.back =
994 pCreateInfo->pDepthStencilState->back.reference;
995 }
996 }
997
998 pipeline->dynamic_state_mask = states;
999 }
1000
1001 static void
1002 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1003 {
1004 struct anv_render_pass *renderpass = NULL;
1005 struct anv_subpass *subpass = NULL;
1006
1007 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1008 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1009 * 4.2 Graphics Pipeline.
1010 */
1011 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1012
1013 renderpass = anv_render_pass_from_handle(info->renderPass);
1014 assert(renderpass);
1015
1016 if (renderpass != &anv_meta_dummy_renderpass) {
1017 assert(info->subpass < renderpass->subpass_count);
1018 subpass = &renderpass->subpasses[info->subpass];
1019 }
1020
1021 assert(info->stageCount >= 1);
1022 assert(info->pVertexInputState);
1023 assert(info->pInputAssemblyState);
1024 assert(info->pViewportState);
1025 assert(info->pRasterizationState);
1026
1027 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1028 assert(info->pDepthStencilState);
1029
1030 if (subpass && subpass->color_count > 0)
1031 assert(info->pColorBlendState);
1032
1033 for (uint32_t i = 0; i < info->stageCount; ++i) {
1034 switch (info->pStages[i].stage) {
1035 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1036 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1037 assert(info->pTessellationState);
1038 break;
1039 default:
1040 break;
1041 }
1042 }
1043 }
1044
1045 VkResult
1046 anv_pipeline_init(struct anv_pipeline *pipeline,
1047 struct anv_device *device,
1048 struct anv_pipeline_cache *cache,
1049 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1050 const struct anv_graphics_pipeline_create_info *extra,
1051 const VkAllocationCallbacks *alloc)
1052 {
1053 VkResult result;
1054
1055 anv_validate {
1056 anv_pipeline_validate_create_info(pCreateInfo);
1057 }
1058
1059 if (alloc == NULL)
1060 alloc = &device->alloc;
1061
1062 pipeline->device = device;
1063 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1064
1065 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1066 if (result != VK_SUCCESS)
1067 return result;
1068
1069 pipeline->batch.alloc = alloc;
1070 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1071 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1072 pipeline->batch.relocs = &pipeline->batch_relocs;
1073
1074 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1075
1076 if (pCreateInfo->pTessellationState)
1077 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1078 if (pCreateInfo->pMultisampleState &&
1079 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1080 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
1081
1082 pipeline->use_repclear = extra && extra->use_repclear;
1083 pipeline->writes_point_size = false;
1084
1085 /* When we free the pipeline, we detect stages based on the NULL status
1086 * of various prog_data pointers. Make them NULL by default.
1087 */
1088 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1089 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1090
1091 pipeline->vs_simd8 = NO_KERNEL;
1092 pipeline->vs_vec4 = NO_KERNEL;
1093 pipeline->gs_kernel = NO_KERNEL;
1094
1095 pipeline->active_stages = 0;
1096 pipeline->total_scratch = 0;
1097
1098 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1099 ANV_FROM_HANDLE(anv_shader_module, module,
1100 pCreateInfo->pStages[i].module);
1101
1102 switch (pCreateInfo->pStages[i].stage) {
1103 case VK_SHADER_STAGE_VERTEX_BIT:
1104 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo, module,
1105 pCreateInfo->pStages[i].pName,
1106 pCreateInfo->pStages[i].pSpecializationInfo);
1107 break;
1108 case VK_SHADER_STAGE_GEOMETRY_BIT:
1109 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo, module,
1110 pCreateInfo->pStages[i].pName,
1111 pCreateInfo->pStages[i].pSpecializationInfo);
1112 break;
1113 case VK_SHADER_STAGE_FRAGMENT_BIT:
1114 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra, module,
1115 pCreateInfo->pStages[i].pName,
1116 pCreateInfo->pStages[i].pSpecializationInfo);
1117 break;
1118 default:
1119 anv_finishme("Unsupported shader stage");
1120 }
1121 }
1122
1123 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1124 /* Vertex is only optional if disable_vs is set */
1125 assert(extra->disable_vs);
1126 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1127 }
1128
1129 gen7_compute_urb_partition(pipeline);
1130
1131 const VkPipelineVertexInputStateCreateInfo *vi_info =
1132 pCreateInfo->pVertexInputState;
1133
1134 uint64_t inputs_read;
1135 if (extra && extra->disable_vs) {
1136 /* If the VS is disabled, just assume the user knows what they're
1137 * doing and apply the layout blindly. This can only come from
1138 * meta, so this *should* be safe.
1139 */
1140 inputs_read = ~0ull;
1141 } else {
1142 inputs_read = pipeline->vs_prog_data.inputs_read;
1143 }
1144
1145 pipeline->vb_used = 0;
1146 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1147 const VkVertexInputAttributeDescription *desc =
1148 &vi_info->pVertexAttributeDescriptions[i];
1149
1150 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1151 pipeline->vb_used |= 1 << desc->binding;
1152 }
1153
1154 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1155 const VkVertexInputBindingDescription *desc =
1156 &vi_info->pVertexBindingDescriptions[i];
1157
1158 pipeline->binding_stride[desc->binding] = desc->stride;
1159
1160 /* Step rate is programmed per vertex element (attribute), not
1161 * binding. Set up a map of which bindings step per instance, for
1162 * reference by vertex element setup. */
1163 switch (desc->inputRate) {
1164 default:
1165 case VK_VERTEX_INPUT_RATE_VERTEX:
1166 pipeline->instancing_enable[desc->binding] = false;
1167 break;
1168 case VK_VERTEX_INPUT_RATE_INSTANCE:
1169 pipeline->instancing_enable[desc->binding] = true;
1170 break;
1171 }
1172 }
1173
1174 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1175 pCreateInfo->pInputAssemblyState;
1176 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1177 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1178
1179 if (extra && extra->use_rectlist)
1180 pipeline->topology = _3DPRIM_RECTLIST;
1181
1182 return VK_SUCCESS;
1183 }
1184
1185 VkResult
1186 anv_graphics_pipeline_create(
1187 VkDevice _device,
1188 VkPipelineCache _cache,
1189 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1190 const struct anv_graphics_pipeline_create_info *extra,
1191 const VkAllocationCallbacks *pAllocator,
1192 VkPipeline *pPipeline)
1193 {
1194 ANV_FROM_HANDLE(anv_device, device, _device);
1195 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1196
1197 if (cache == NULL)
1198 cache = &device->default_pipeline_cache;
1199
1200 switch (device->info.gen) {
1201 case 7:
1202 if (device->info.is_haswell)
1203 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1204 else
1205 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1206 case 8:
1207 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1208 case 9:
1209 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1210 default:
1211 unreachable("unsupported gen\n");
1212 }
1213 }
1214
1215 VkResult anv_CreateGraphicsPipelines(
1216 VkDevice _device,
1217 VkPipelineCache pipelineCache,
1218 uint32_t count,
1219 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1220 const VkAllocationCallbacks* pAllocator,
1221 VkPipeline* pPipelines)
1222 {
1223 VkResult result = VK_SUCCESS;
1224
1225 unsigned i = 0;
1226 for (; i < count; i++) {
1227 result = anv_graphics_pipeline_create(_device,
1228 pipelineCache,
1229 &pCreateInfos[i],
1230 NULL, pAllocator, &pPipelines[i]);
1231 if (result != VK_SUCCESS) {
1232 for (unsigned j = 0; j < i; j++) {
1233 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1234 }
1235
1236 return result;
1237 }
1238 }
1239
1240 return VK_SUCCESS;
1241 }
1242
1243 static VkResult anv_compute_pipeline_create(
1244 VkDevice _device,
1245 VkPipelineCache _cache,
1246 const VkComputePipelineCreateInfo* pCreateInfo,
1247 const VkAllocationCallbacks* pAllocator,
1248 VkPipeline* pPipeline)
1249 {
1250 ANV_FROM_HANDLE(anv_device, device, _device);
1251 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1252
1253 if (cache == NULL)
1254 cache = &device->default_pipeline_cache;
1255
1256 switch (device->info.gen) {
1257 case 7:
1258 if (device->info.is_haswell)
1259 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1260 else
1261 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1262 case 8:
1263 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1264 case 9:
1265 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1266 default:
1267 unreachable("unsupported gen\n");
1268 }
1269 }
1270
1271 VkResult anv_CreateComputePipelines(
1272 VkDevice _device,
1273 VkPipelineCache pipelineCache,
1274 uint32_t count,
1275 const VkComputePipelineCreateInfo* pCreateInfos,
1276 const VkAllocationCallbacks* pAllocator,
1277 VkPipeline* pPipelines)
1278 {
1279 VkResult result = VK_SUCCESS;
1280
1281 unsigned i = 0;
1282 for (; i < count; i++) {
1283 result = anv_compute_pipeline_create(_device, pipelineCache,
1284 &pCreateInfos[i],
1285 pAllocator, &pPipelines[i]);
1286 if (result != VK_SUCCESS) {
1287 for (unsigned j = 0; j < i; j++) {
1288 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1289 }
1290
1291 return result;
1292 }
1293 }
1294
1295 return VK_SUCCESS;
1296 }