src/vulkan/anv_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31 #include "brw_nir.h"
  32 #include "anv_nir.h"
  33 #include "glsl/nir/nir_spirv.h"
  34
  35 /* Needed for SWIZZLE macros */
  36 #include "program/prog_instruction.h"
  37
  38 // Shader functions
  39
  40 VkResult anv_CreateShaderModule(
  41     VkDevice                                    _device,
  42     const VkShaderModuleCreateInfo*             pCreateInfo,
  43     const VkAllocationCallbacks*                pAllocator,
  44     VkShaderModule*                             pShaderModule)
  45 {
  46    ANV_FROM_HANDLE(anv_device, device, _device);
  47    struct anv_shader_module *module;
  48
  49    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  50    assert(pCreateInfo->flags == 0);
  51
  52    module = anv_alloc2(&device->alloc, pAllocator,
  53                        sizeof(*module) + pCreateInfo->codeSize, 8,
  54                        VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  55    if (module == NULL)
  56       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  57
  58    module->nir = NULL;
  59    module->size = pCreateInfo->codeSize;
  60    memcpy(module->data, pCreateInfo->pCode, module->size);
  61
  62    *pShaderModule = anv_shader_module_to_handle(module);
  63
  64    return VK_SUCCESS;
  65 }
  66
  67 void anv_DestroyShaderModule(
  68     VkDevice                                    _device,
  69     VkShaderModule                              _module,
  70     const VkAllocationCallbacks*                pAllocator)
  71 {
  72    ANV_FROM_HANDLE(anv_device, device, _device);
  73    ANV_FROM_HANDLE(anv_shader_module, module, _module);
  74
  75    anv_free2(&device->alloc, pAllocator, module);
  76 }
  77
  78 #define SPIR_V_MAGIC_NUMBER 0x07230203
  79
  80 /* Eventually, this will become part of anv_CreateShader.  Unfortunately,
  81  * we can't do that yet because we don't have the ability to copy nir.
  82  */
  83 static nir_shader *
  84 anv_shader_compile_to_nir(struct anv_device *device,
  85                           struct anv_shader_module *module,
  86                           const char *entrypoint_name,
  87                           gl_shader_stage stage)
  88 {
  89    if (strcmp(entrypoint_name, "main") != 0) {
  90       anv_finishme("Multiple shaders per module not really supported");
  91    }
  92
  93    const struct brw_compiler *compiler =
  94       device->instance->physicalDevice.compiler;
  95    const nir_shader_compiler_options *nir_options =
  96       compiler->glsl_compiler_options[stage].NirOptions;
  97
  98    nir_shader *nir;
  99    if (module->nir) {
 100       /* Some things such as our meta clear/blit code will give us a NIR
 101        * shader directly.  In that case, we just ignore the SPIR-V entirely
 102        * and just use the NIR shader */
 103       nir = module->nir;
 104       nir->options = nir_options;
 105    } else {
 106       uint32_t *spirv = (uint32_t *) module->data;
 107       assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
 108       assert(module->size % 4 == 0);
 109
 110       nir = spirv_to_nir(spirv, module->size / 4, stage, nir_options);
 111    }
 112    nir_validate_shader(nir);
 113
 114    /* Vulkan uses the separate-shader linking model */
 115    nir->info.separate_shader = true;
 116
 117    /* Make sure the provided shader has exactly one entrypoint and that the
 118     * name matches the name that came in from the VkShader.
 119     */
 120    nir_function_impl *entrypoint = NULL;
 121    nir_foreach_overload(nir, overload) {
 122       if (strcmp(entrypoint_name, overload->function->name) == 0 &&
 123           overload->impl) {
 124          assert(entrypoint == NULL);
 125          entrypoint = overload->impl;
 126       }
 127    }
 128    assert(entrypoint != NULL);
 129
 130    nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
 131
 132    nir_shader_gather_info(nir, entrypoint);
 133
 134    return nir;
 135 }
 136
 137 VkResult anv_CreatePipelineCache(
 138     VkDevice                                    device,
 139     const VkPipelineCacheCreateInfo*            pCreateInfo,
 140     const VkAllocationCallbacks*                pAllocator,
 141     VkPipelineCache*                            pPipelineCache)
 142 {
 143    *pPipelineCache = (VkPipelineCache)1;
 144
 145    stub_return(VK_SUCCESS);
 146 }
 147
 148 void anv_DestroyPipelineCache(
 149     VkDevice                                    _device,
 150     VkPipelineCache                             _cache,
 151     const VkAllocationCallbacks*                pAllocator)
 152 {
 153 }
 154
 155 VkResult anv_GetPipelineCacheData(
 156     VkDevice                                    device,
 157     VkPipelineCache                             pipelineCache,
 158     size_t*                                     pDataSize,
 159     void*                                       pData)
 160 {
 161    *pDataSize = 0;
 162    stub_return(VK_SUCCESS);
 163 }
 164
 165 VkResult anv_MergePipelineCaches(
 166     VkDevice                                    device,
 167     VkPipelineCache                             destCache,
 168     uint32_t                                    srcCacheCount,
 169     const VkPipelineCache*                      pSrcCaches)
 170 {
 171    stub_return(VK_SUCCESS);
 172 }
 173
 174 void anv_DestroyPipeline(
 175     VkDevice                                    _device,
 176     VkPipeline                                  _pipeline,
 177     const VkAllocationCallbacks*                pAllocator)
 178 {
 179    ANV_FROM_HANDLE(anv_device, device, _device);
 180    ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
 181
 182    anv_reloc_list_finish(&pipeline->batch_relocs,
 183                          pAllocator ? pAllocator : &device->alloc);
 184    anv_state_stream_finish(&pipeline->program_stream);
 185    if (pipeline->blend_state.map)
 186       anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
 187    anv_free2(&device->alloc, pAllocator, pipeline);
 188 }
 189
 190 static const uint32_t vk_to_gen_primitive_type[] = {
 191    [VK_PRIMITIVE_TOPOLOGY_POINT_LIST]                    = _3DPRIM_POINTLIST,
 192    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST]                     = _3DPRIM_LINELIST,
 193    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP]                    = _3DPRIM_LINESTRIP,
 194    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST]                 = _3DPRIM_TRILIST,
 195    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP]                = _3DPRIM_TRISTRIP,
 196    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN]                  = _3DPRIM_TRIFAN,
 197    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY]      = _3DPRIM_LINELIST_ADJ,
 198    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY]     = _3DPRIM_LINESTRIP_ADJ,
 199    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY]  = _3DPRIM_TRILIST_ADJ,
 200    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
 201 /*   [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST]                = _3DPRIM_PATCHLIST_1 */
 202 };
 203
 204 static void
 205 populate_sampler_prog_key(const struct brw_device_info *devinfo,
 206                           struct brw_sampler_prog_key_data *key)
 207 {
 208    /* XXX: Handle texture swizzle on HSW- */
 209    for (int i = 0; i < MAX_SAMPLERS; i++) {
 210       /* Assume color sampler, no swizzling. (Works for BDW+) */
 211       key->swizzles[i] = SWIZZLE_XYZW;
 212    }
 213 }
 214
 215 static void
 216 populate_vs_prog_key(const struct brw_device_info *devinfo,
 217                      struct brw_vs_prog_key *key)
 218 {
 219    memset(key, 0, sizeof(*key));
 220
 221    populate_sampler_prog_key(devinfo, &key->tex);
 222
 223    /* XXX: Handle vertex input work-arounds */
 224
 225    /* XXX: Handle sampler_prog_key */
 226 }
 227
 228 static void
 229 populate_gs_prog_key(const struct brw_device_info *devinfo,
 230                      struct brw_gs_prog_key *key)
 231 {
 232    memset(key, 0, sizeof(*key));
 233
 234    populate_sampler_prog_key(devinfo, &key->tex);
 235 }
 236
 237 static void
 238 populate_wm_prog_key(const struct brw_device_info *devinfo,
 239                      const VkGraphicsPipelineCreateInfo *info,
 240                      struct brw_wm_prog_key *key)
 241 {
 242    ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
 243
 244    memset(key, 0, sizeof(*key));
 245
 246    populate_sampler_prog_key(devinfo, &key->tex);
 247
 248    /* TODO: Fill out key->input_slots_valid */
 249
 250    /* Vulkan doesn't specify a default */
 251    key->high_quality_derivatives = false;
 252
 253    /* XXX Vulkan doesn't appear to specify */
 254    key->clamp_fragment_color = false;
 255
 256    /* Vulkan always specifies upper-left coordinates */
 257    key->drawable_height = 0;
 258    key->render_to_fbo = false;
 259
 260    key->nr_color_regions = render_pass->subpasses[info->subpass].color_count;
 261
 262    key->replicate_alpha = key->nr_color_regions > 1 &&
 263                           info->pMultisampleState &&
 264                           info->pMultisampleState->alphaToCoverageEnable;
 265
 266    if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
 267       /* We should probably pull this out of the shader, but it's fairly
 268        * harmless to compute it and then let dead-code take care of it.
 269        */
 270       key->persample_shading = info->pMultisampleState->sampleShadingEnable;
 271       if (key->persample_shading)
 272          key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
 273
 274       key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
 275       key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
 276    }
 277 }
 278
 279 static void
 280 populate_cs_prog_key(const struct brw_device_info *devinfo,
 281                      struct brw_cs_prog_key *key)
 282 {
 283    memset(key, 0, sizeof(*key));
 284
 285    populate_sampler_prog_key(devinfo, &key->tex);
 286 }
 287
 288 static nir_shader *
 289 anv_pipeline_compile(struct anv_pipeline *pipeline,
 290                      struct anv_shader_module *module,
 291                      const char *entrypoint,
 292                      gl_shader_stage stage,
 293                      struct brw_stage_prog_data *prog_data)
 294 {
 295    const struct brw_compiler *compiler =
 296       pipeline->device->instance->physicalDevice.compiler;
 297
 298    nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
 299                                                module, entrypoint, stage);
 300    if (nir == NULL)
 301       return NULL;
 302
 303    anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
 304
 305    /* Figure out the number of parameters */
 306    prog_data->nr_params = 0;
 307
 308    if (nir->num_uniforms > 0) {
 309       /* If the shader uses any push constants at all, we'll just give
 310        * them the maximum possible number
 311        */
 312       prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
 313    }
 314
 315    if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
 316       prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
 317
 318    if (prog_data->nr_params > 0) {
 319       /* XXX: I think we're leaking this */
 320       prog_data->param = (const gl_constant_value **)
 321          malloc(prog_data->nr_params * sizeof(gl_constant_value *));
 322
 323       /* We now set the param values to be offsets into a
 324        * anv_push_constant_data structure.  Since the compiler doesn't
 325        * actually dereference any of the gl_constant_value pointers in the
 326        * params array, it doesn't really matter what we put here.
 327        */
 328       struct anv_push_constants *null_data = NULL;
 329       if (nir->num_uniforms > 0) {
 330          /* Fill out the push constants section of the param array */
 331          for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
 332             prog_data->param[i] = (const gl_constant_value *)
 333                &null_data->client_data[i * sizeof(float)];
 334       }
 335    }
 336
 337    /* Set up dynamic offsets */
 338    anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
 339
 340    /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
 341    if (pipeline->layout)
 342       anv_nir_apply_pipeline_layout(nir, pipeline->layout);
 343
 344    /* All binding table offsets provided by apply_pipeline_layout() are
 345     * relative to the start of the bindint table (plus MAX_RTS for VS).
 346     */
 347    unsigned bias = stage == MESA_SHADER_FRAGMENT ? MAX_RTS : 0;
 348    prog_data->binding_table.size_bytes = 0;
 349    prog_data->binding_table.texture_start = bias;
 350    prog_data->binding_table.ubo_start = bias;
 351    prog_data->binding_table.ssbo_start = bias;
 352    prog_data->binding_table.image_start = bias;
 353
 354    /* Finish the optimization and compilation process */
 355    nir = brw_lower_nir(nir, &pipeline->device->info, NULL,
 356                        compiler->scalar_stage[stage]);
 357
 358    /* nir_lower_io will only handle the push constants; we need to set this
 359     * to the full number of possible uniforms.
 360     */
 361    nir->num_uniforms = prog_data->nr_params;
 362
 363    return nir;
 364 }
 365
 366 static uint32_t
 367 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
 368                            const void *data, size_t size)
 369 {
 370    struct anv_state state =
 371       anv_state_stream_alloc(&pipeline->program_stream, size, 64);
 372
 373    assert(size < pipeline->program_stream.block_pool->block_size);
 374
 375    memcpy(state.map, data, size);
 376
 377    if (!pipeline->device->info.has_llc)
 378       anv_state_clflush(state);
 379
 380    return state.offset;
 381 }
 382
 383 static void
 384 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
 385                                 gl_shader_stage stage,
 386                                 struct brw_stage_prog_data *prog_data)
 387 {
 388    struct brw_device_info *devinfo = &pipeline->device->info;
 389    uint32_t max_threads[] = {
 390       [MESA_SHADER_VERTEX]                  = devinfo->max_vs_threads,
 391       [MESA_SHADER_TESS_CTRL]               = 0,
 392       [MESA_SHADER_TESS_EVAL]               = 0,
 393       [MESA_SHADER_GEOMETRY]                = devinfo->max_gs_threads,
 394       [MESA_SHADER_FRAGMENT]                = devinfo->max_wm_threads,
 395       [MESA_SHADER_COMPUTE]                 = devinfo->max_cs_threads,
 396    };
 397
 398    pipeline->prog_data[stage] = prog_data;
 399    pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
 400    pipeline->scratch_start[stage] = pipeline->total_scratch;
 401    pipeline->total_scratch =
 402       align_u32(pipeline->total_scratch, 1024) +
 403       prog_data->total_scratch * max_threads[stage];
 404 }
 405
 406 static VkResult
 407 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
 408                         const VkGraphicsPipelineCreateInfo *info,
 409                         struct anv_shader_module *module,
 410                         const char *entrypoint)
 411 {
 412    const struct brw_compiler *compiler =
 413       pipeline->device->instance->physicalDevice.compiler;
 414    struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
 415    struct brw_vs_prog_key key;
 416
 417    populate_vs_prog_key(&pipeline->device->info, &key);
 418
 419    /* TODO: Look up shader in cache */
 420
 421    memset(prog_data, 0, sizeof(*prog_data));
 422
 423    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 424                                           MESA_SHADER_VERTEX,
 425                                           &prog_data->base.base);
 426    if (nir == NULL)
 427       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 428
 429    void *mem_ctx = ralloc_context(NULL);
 430
 431    if (module->nir == NULL)
 432       ralloc_steal(mem_ctx, nir);
 433
 434    prog_data->inputs_read = nir->info.inputs_read;
 435    pipeline->writes_point_size = nir->info.outputs_written & VARYING_SLOT_PSIZ;
 436
 437    brw_compute_vue_map(&pipeline->device->info,
 438                        &prog_data->base.vue_map,
 439                        nir->info.outputs_written,
 440                        nir->info.separate_shader);
 441
 442    unsigned code_size;
 443    const unsigned *shader_code =
 444       brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 445                      NULL, false, -1, &code_size, NULL);
 446    if (shader_code == NULL) {
 447       ralloc_free(mem_ctx);
 448       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 449    }
 450
 451    const uint32_t offset =
 452       anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
 453    if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
 454       pipeline->vs_simd8 = offset;
 455       pipeline->vs_vec4 = NO_KERNEL;
 456    } else {
 457       pipeline->vs_simd8 = NO_KERNEL;
 458       pipeline->vs_vec4 = offset;
 459    }
 460
 461    ralloc_free(mem_ctx);
 462
 463    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
 464                                    &prog_data->base.base);
 465
 466    return VK_SUCCESS;
 467 }
 468
 469 static VkResult
 470 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
 471                         const VkGraphicsPipelineCreateInfo *info,
 472                         struct anv_shader_module *module,
 473                         const char *entrypoint)
 474 {
 475    const struct brw_compiler *compiler =
 476       pipeline->device->instance->physicalDevice.compiler;
 477    struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
 478    struct brw_gs_prog_key key;
 479
 480    populate_gs_prog_key(&pipeline->device->info, &key);
 481
 482    /* TODO: Look up shader in cache */
 483
 484    memset(prog_data, 0, sizeof(*prog_data));
 485
 486    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 487                                           MESA_SHADER_GEOMETRY,
 488                                           &prog_data->base.base);
 489    if (nir == NULL)
 490       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 491
 492    void *mem_ctx = ralloc_context(NULL);
 493
 494    if (module->nir == NULL)
 495       ralloc_steal(mem_ctx, nir);
 496
 497    brw_compute_vue_map(&pipeline->device->info,
 498                        &prog_data->base.vue_map,
 499                        nir->info.outputs_written,
 500                        nir->info.separate_shader);
 501
 502    unsigned code_size;
 503    const unsigned *shader_code =
 504       brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 505                      NULL, -1, &code_size, NULL);
 506    if (shader_code == NULL) {
 507       ralloc_free(mem_ctx);
 508       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 509    }
 510
 511    /* TODO: SIMD8 GS */
 512    pipeline->gs_vec4 =
 513       anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
 514    pipeline->gs_vertex_count = nir->info.gs.vertices_in;
 515
 516    ralloc_free(mem_ctx);
 517
 518    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
 519                                    &prog_data->base.base);
 520
 521    return VK_SUCCESS;
 522 }
 523
 524 static VkResult
 525 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
 526                         const VkGraphicsPipelineCreateInfo *info,
 527                         struct anv_shader_module *module,
 528                         const char *entrypoint)
 529 {
 530    const struct brw_compiler *compiler =
 531       pipeline->device->instance->physicalDevice.compiler;
 532    struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
 533    struct brw_wm_prog_key key;
 534
 535    populate_wm_prog_key(&pipeline->device->info, info, &key);
 536
 537    if (pipeline->use_repclear)
 538       key.nr_color_regions = 1;
 539
 540    /* TODO: Look up shader in cache */
 541
 542    memset(prog_data, 0, sizeof(*prog_data));
 543
 544    prog_data->binding_table.render_target_start = 0;
 545
 546    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 547                                           MESA_SHADER_FRAGMENT,
 548                                           &prog_data->base);
 549    if (nir == NULL)
 550       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 551
 552    void *mem_ctx = ralloc_context(NULL);
 553
 554    if (module->nir == NULL)
 555       ralloc_steal(mem_ctx, nir);
 556
 557    unsigned code_size;
 558    const unsigned *shader_code =
 559       brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 560                      NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
 561    if (shader_code == NULL) {
 562       ralloc_free(mem_ctx);
 563       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 564    }
 565
 566    uint32_t offset = anv_pipeline_upload_kernel(pipeline,
 567                                                 shader_code, code_size);
 568    if (prog_data->no_8)
 569       pipeline->ps_simd8 = NO_KERNEL;
 570    else
 571       pipeline->ps_simd8 = offset;
 572
 573    if (prog_data->no_8 || prog_data->prog_offset_16) {
 574       pipeline->ps_simd16 = offset + prog_data->prog_offset_16;
 575    } else {
 576       pipeline->ps_simd16 = NO_KERNEL;
 577    }
 578
 579    pipeline->ps_ksp2 = 0;
 580    pipeline->ps_grf_start2 = 0;
 581    if (pipeline->ps_simd8 != NO_KERNEL) {
 582       pipeline->ps_ksp0 = pipeline->ps_simd8;
 583       pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
 584       if (pipeline->ps_simd16 != NO_KERNEL) {
 585          pipeline->ps_ksp2 = pipeline->ps_simd16;
 586          pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
 587       }
 588    } else if (pipeline->ps_simd16 != NO_KERNEL) {
 589       pipeline->ps_ksp0 = pipeline->ps_simd16;
 590       pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
 591    }
 592
 593    ralloc_free(mem_ctx);
 594
 595    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
 596                                    &prog_data->base);
 597
 598    return VK_SUCCESS;
 599 }
 600
 601 VkResult
 602 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
 603                         const VkComputePipelineCreateInfo *info,
 604                         struct anv_shader_module *module,
 605                         const char *entrypoint)
 606 {
 607    const struct brw_compiler *compiler =
 608       pipeline->device->instance->physicalDevice.compiler;
 609    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 610    struct brw_cs_prog_key key;
 611
 612    populate_cs_prog_key(&pipeline->device->info, &key);
 613
 614    /* TODO: Look up shader in cache */
 615
 616    memset(prog_data, 0, sizeof(*prog_data));
 617
 618    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 619                                           MESA_SHADER_COMPUTE,
 620                                           &prog_data->base);
 621    if (nir == NULL)
 622       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 623
 624    void *mem_ctx = ralloc_context(NULL);
 625
 626    if (module->nir == NULL)
 627       ralloc_steal(mem_ctx, nir);
 628
 629    unsigned code_size;
 630    const unsigned *shader_code =
 631       brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 632                      -1, &code_size, NULL);
 633    if (shader_code == NULL) {
 634       ralloc_free(mem_ctx);
 635       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 636    }
 637
 638    pipeline->cs_simd = anv_pipeline_upload_kernel(pipeline,
 639                                                   shader_code, code_size);
 640    ralloc_free(mem_ctx);
 641
 642    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
 643                                    &prog_data->base);
 644
 645    return VK_SUCCESS;
 646 }
 647
 648 static const int gen8_push_size = 32 * 1024;
 649
 650 static void
 651 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
 652 {
 653    const struct brw_device_info *devinfo = &pipeline->device->info;
 654    bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
 655    unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
 656    unsigned vs_entry_size_bytes = vs_size * 64;
 657    bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
 658    unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
 659    unsigned gs_entry_size_bytes = gs_size * 64;
 660
 661    /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
 662     *
 663     *     VS Number of URB Entries must be divisible by 8 if the VS URB Entry
 664     *     Allocation Size is less than 9 512-bit URB entries.
 665     *
 666     * Similar text exists for GS.
 667     */
 668    unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
 669    unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
 670
 671    /* URB allocations must be done in 8k chunks. */
 672    unsigned chunk_size_bytes = 8192;
 673
 674    /* Determine the size of the URB in chunks. */
 675    unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
 676
 677    /* Reserve space for push constants */
 678    unsigned push_constant_bytes = gen8_push_size;
 679    unsigned push_constant_chunks =
 680       push_constant_bytes / chunk_size_bytes;
 681
 682    /* Initially, assign each stage the minimum amount of URB space it needs,
 683     * and make a note of how much additional space it "wants" (the amount of
 684     * additional space it could actually make use of).
 685     */
 686
 687    /* VS has a lower limit on the number of URB entries */
 688    unsigned vs_chunks =
 689       ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
 690             chunk_size_bytes) / chunk_size_bytes;
 691    unsigned vs_wants =
 692       ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
 693             chunk_size_bytes) / chunk_size_bytes - vs_chunks;
 694
 695    unsigned gs_chunks = 0;
 696    unsigned gs_wants = 0;
 697    if (gs_present) {
 698       /* There are two constraints on the minimum amount of URB space we can
 699        * allocate:
 700        *
 701        * (1) We need room for at least 2 URB entries, since we always operate
 702        * the GS in DUAL_OBJECT mode.
 703        *
 704        * (2) We can't allocate less than nr_gs_entries_granularity.
 705        */
 706       gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
 707                         chunk_size_bytes) / chunk_size_bytes;
 708       gs_wants =
 709          ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
 710                chunk_size_bytes) / chunk_size_bytes - gs_chunks;
 711    }
 712
 713    /* There should always be enough URB space to satisfy the minimum
 714     * requirements of each stage.
 715     */
 716    unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
 717    assert(total_needs <= urb_chunks);
 718
 719    /* Mete out remaining space (if any) in proportion to "wants". */
 720    unsigned total_wants = vs_wants + gs_wants;
 721    unsigned remaining_space = urb_chunks - total_needs;
 722    if (remaining_space > total_wants)
 723       remaining_space = total_wants;
 724    if (remaining_space > 0) {
 725       unsigned vs_additional = (unsigned)
 726          round(vs_wants * (((double) remaining_space) / total_wants));
 727       vs_chunks += vs_additional;
 728       remaining_space -= vs_additional;
 729       gs_chunks += remaining_space;
 730    }
 731
 732    /* Sanity check that we haven't over-allocated. */
 733    assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
 734
 735    /* Finally, compute the number of entries that can fit in the space
 736     * allocated to each stage.
 737     */
 738    unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
 739    unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
 740
 741    /* Since we rounded up when computing *_wants, this may be slightly more
 742     * than the maximum allowed amount, so correct for that.
 743     */
 744    nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
 745    nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
 746
 747    /* Ensure that we program a multiple of the granularity. */
 748    nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
 749    nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
 750
 751    /* Finally, sanity check to make sure we have at least the minimum number
 752     * of entries needed for each stage.
 753     */
 754    assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
 755    if (gs_present)
 756       assert(nr_gs_entries >= 2);
 757
 758    /* Lay out the URB in the following order:
 759     * - push constants
 760     * - VS
 761     * - GS
 762     */
 763    pipeline->urb.vs_start = push_constant_chunks;
 764    pipeline->urb.vs_size = vs_size;
 765    pipeline->urb.nr_vs_entries = nr_vs_entries;
 766
 767    pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
 768    pipeline->urb.gs_size = gs_size;
 769    pipeline->urb.nr_gs_entries = nr_gs_entries;
 770 }
 771
 772 static void
 773 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
 774                                 const VkGraphicsPipelineCreateInfo *pCreateInfo)
 775 {
 776    anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
 777    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
 778    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
 779
 780    pipeline->dynamic_state = default_dynamic_state;
 781
 782    if (pCreateInfo->pDynamicState) {
 783       /* Remove all of the states that are marked as dynamic */
 784       uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
 785       for (uint32_t s = 0; s < count; s++)
 786          states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
 787    }
 788
 789    struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
 790
 791    dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
 792    if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
 793       typed_memcpy(dynamic->viewport.viewports,
 794                    pCreateInfo->pViewportState->pViewports,
 795                    pCreateInfo->pViewportState->viewportCount);
 796    }
 797
 798    dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
 799    if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
 800       typed_memcpy(dynamic->scissor.scissors,
 801                    pCreateInfo->pViewportState->pScissors,
 802                    pCreateInfo->pViewportState->scissorCount);
 803    }
 804
 805    if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
 806       assert(pCreateInfo->pRasterizationState);
 807       dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
 808    }
 809
 810    if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
 811       assert(pCreateInfo->pRasterizationState);
 812       dynamic->depth_bias.bias =
 813          pCreateInfo->pRasterizationState->depthBiasConstantFactor;
 814       dynamic->depth_bias.clamp =
 815          pCreateInfo->pRasterizationState->depthBiasClamp;
 816       dynamic->depth_bias.slope =
 817          pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
 818    }
 819
 820    if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
 821       assert(pCreateInfo->pColorBlendState);
 822       typed_memcpy(dynamic->blend_constants,
 823                    pCreateInfo->pColorBlendState->blendConstants, 4);
 824    }
 825
 826    /* If there is no depthstencil attachment, then don't read
 827     * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
 828     * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
 829     * no need to override the depthstencil defaults in
 830     * anv_pipeline::dynamic_state when there is no depthstencil attachment.
 831     *
 832     * From the Vulkan spec (20 Oct 2015, git-aa308cb):
 833     *
 834     *    pDepthStencilState [...] may only be NULL if renderPass and subpass
 835     *    specify a subpass that has no depth/stencil attachment.
 836     */
 837    if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
 838       if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
 839          assert(pCreateInfo->pDepthStencilState);
 840          dynamic->depth_bounds.min =
 841             pCreateInfo->pDepthStencilState->minDepthBounds;
 842          dynamic->depth_bounds.max =
 843             pCreateInfo->pDepthStencilState->maxDepthBounds;
 844       }
 845
 846       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
 847          assert(pCreateInfo->pDepthStencilState);
 848          dynamic->stencil_compare_mask.front =
 849             pCreateInfo->pDepthStencilState->front.compareMask;
 850          dynamic->stencil_compare_mask.back =
 851             pCreateInfo->pDepthStencilState->back.compareMask;
 852       }
 853
 854       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
 855          assert(pCreateInfo->pDepthStencilState);
 856          dynamic->stencil_write_mask.front =
 857             pCreateInfo->pDepthStencilState->front.writeMask;
 858          dynamic->stencil_write_mask.back =
 859             pCreateInfo->pDepthStencilState->back.writeMask;
 860       }
 861
 862       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
 863          assert(pCreateInfo->pDepthStencilState);
 864          dynamic->stencil_reference.front =
 865             pCreateInfo->pDepthStencilState->front.reference;
 866          dynamic->stencil_reference.back =
 867             pCreateInfo->pDepthStencilState->back.reference;
 868       }
 869    }
 870
 871    pipeline->dynamic_state_mask = states;
 872 }
 873
 874 static void
 875 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
 876 {
 877    struct anv_render_pass *renderpass = NULL;
 878    struct anv_subpass *subpass = NULL;
 879
 880    /* Assert that all required members of VkGraphicsPipelineCreateInfo are
 881     * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
 882     * 4.2 Graphics Pipeline.
 883     */
 884    assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 885
 886    renderpass = anv_render_pass_from_handle(info->renderPass);
 887    assert(renderpass);
 888
 889    if (renderpass != &anv_meta_dummy_renderpass) {
 890       assert(info->subpass < renderpass->subpass_count);
 891       subpass = &renderpass->subpasses[info->subpass];
 892    }
 893
 894    assert(info->stageCount >= 1);
 895    assert(info->pVertexInputState);
 896    assert(info->pInputAssemblyState);
 897    assert(info->pViewportState);
 898    assert(info->pRasterizationState);
 899    assert(info->pMultisampleState);
 900
 901    if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
 902       assert(info->pDepthStencilState);
 903
 904    if (subpass && subpass->color_count > 0)
 905       assert(info->pColorBlendState);
 906
 907    for (uint32_t i = 0; i < info->stageCount; ++i) {
 908       switch (info->pStages[i].stage) {
 909       case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
 910       case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
 911          assert(info->pTessellationState);
 912          break;
 913       default:
 914          break;
 915       }
 916    }
 917 }
 918
 919 VkResult
 920 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
 921                   const VkGraphicsPipelineCreateInfo *pCreateInfo,
 922                   const struct anv_graphics_pipeline_create_info *extra,
 923                   const VkAllocationCallbacks *alloc)
 924 {
 925    anv_validate {
 926       anv_pipeline_validate_create_info(pCreateInfo);
 927    }
 928
 929    if (alloc == NULL)
 930       alloc = &device->alloc;
 931
 932    pipeline->device = device;
 933    pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
 934
 935    anv_reloc_list_init(&pipeline->batch_relocs, alloc);
 936    /* TODO: Handle allocation fail */
 937
 938    pipeline->batch.alloc = alloc;
 939    pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
 940    pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
 941    pipeline->batch.relocs = &pipeline->batch_relocs;
 942
 943    anv_state_stream_init(&pipeline->program_stream,
 944                          &device->instruction_block_pool);
 945
 946    anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
 947
 948    if (pCreateInfo->pTessellationState)
 949       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
 950    if (pCreateInfo->pMultisampleState &&
 951        pCreateInfo->pMultisampleState->rasterizationSamples > 1)
 952       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
 953
 954    pipeline->use_repclear = extra && extra->use_repclear;
 955    pipeline->writes_point_size = false;
 956
 957    /* When we free the pipeline, we detect stages based on the NULL status
 958     * of various prog_data pointers.  Make them NULL by default.
 959     */
 960    memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
 961    memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
 962
 963    pipeline->vs_simd8 = NO_KERNEL;
 964    pipeline->vs_vec4 = NO_KERNEL;
 965    pipeline->gs_vec4 = NO_KERNEL;
 966
 967    pipeline->active_stages = 0;
 968    pipeline->total_scratch = 0;
 969
 970    for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
 971       ANV_FROM_HANDLE(anv_shader_module, module,
 972                       pCreateInfo->pStages[i].module);
 973       const char *entrypoint = pCreateInfo->pStages[i].pName;
 974
 975       switch (pCreateInfo->pStages[i].stage) {
 976       case VK_SHADER_STAGE_VERTEX_BIT:
 977          anv_pipeline_compile_vs(pipeline, pCreateInfo, module, entrypoint);
 978          break;
 979       case VK_SHADER_STAGE_GEOMETRY_BIT:
 980          anv_pipeline_compile_gs(pipeline, pCreateInfo, module, entrypoint);
 981          break;
 982       case VK_SHADER_STAGE_FRAGMENT_BIT:
 983          anv_pipeline_compile_fs(pipeline, pCreateInfo, module, entrypoint);
 984          break;
 985       default:
 986          anv_finishme("Unsupported shader stage");
 987       }
 988    }
 989
 990    if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
 991       /* Vertex is only optional if disable_vs is set */
 992       assert(extra->disable_vs);
 993       memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
 994    }
 995
 996    gen7_compute_urb_partition(pipeline);
 997
 998    const VkPipelineVertexInputStateCreateInfo *vi_info =
 999       pCreateInfo->pVertexInputState;
1000    pipeline->vb_used = 0;
1001    for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1002       const VkVertexInputBindingDescription *desc =
1003          &vi_info->pVertexBindingDescriptions[i];
1004
1005       pipeline->vb_used |= 1 << desc->binding;
1006       pipeline->binding_stride[desc->binding] = desc->stride;
1007
1008       /* Step rate is programmed per vertex element (attribute), not
1009        * binding. Set up a map of which bindings step per instance, for
1010        * reference by vertex element setup. */
1011       switch (desc->inputRate) {
1012       default:
1013       case VK_VERTEX_INPUT_RATE_VERTEX:
1014          pipeline->instancing_enable[desc->binding] = false;
1015          break;
1016       case VK_VERTEX_INPUT_RATE_INSTANCE:
1017          pipeline->instancing_enable[desc->binding] = true;
1018          break;
1019       }
1020    }
1021
1022    const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1023       pCreateInfo->pInputAssemblyState;
1024    pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1025    pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1026
1027    if (extra && extra->use_rectlist)
1028       pipeline->topology = _3DPRIM_RECTLIST;
1029
1030    return VK_SUCCESS;
1031 }
1032
1033 VkResult
1034 anv_graphics_pipeline_create(
1035    VkDevice _device,
1036    const VkGraphicsPipelineCreateInfo *pCreateInfo,
1037    const struct anv_graphics_pipeline_create_info *extra,
1038    const VkAllocationCallbacks *pAllocator,
1039    VkPipeline *pPipeline)
1040 {
1041    ANV_FROM_HANDLE(anv_device, device, _device);
1042
1043    switch (device->info.gen) {
1044    case 7:
1045       if (device->info.is_haswell)
1046          return gen75_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1047       else
1048          return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1049    case 8:
1050       return gen8_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1051    case 9:
1052       return gen9_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1053    default:
1054       unreachable("unsupported gen\n");
1055    }
1056 }
1057
1058 VkResult anv_CreateGraphicsPipelines(
1059     VkDevice                                    _device,
1060     VkPipelineCache                             pipelineCache,
1061     uint32_t                                    count,
1062     const VkGraphicsPipelineCreateInfo*         pCreateInfos,
1063     const VkAllocationCallbacks*                pAllocator,
1064     VkPipeline*                                 pPipelines)
1065 {
1066    VkResult result = VK_SUCCESS;
1067
1068    unsigned i = 0;
1069    for (; i < count; i++) {
1070       result = anv_graphics_pipeline_create(_device, &pCreateInfos[i],
1071                                             NULL, pAllocator, &pPipelines[i]);
1072       if (result != VK_SUCCESS) {
1073          for (unsigned j = 0; j < i; j++) {
1074             anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1075          }
1076
1077          return result;
1078       }
1079    }
1080
1081    return VK_SUCCESS;
1082 }
1083
1084 static VkResult anv_compute_pipeline_create(
1085     VkDevice                                    _device,
1086     const VkComputePipelineCreateInfo*          pCreateInfo,
1087     const VkAllocationCallbacks*                pAllocator,
1088     VkPipeline*                                 pPipeline)
1089 {
1090    ANV_FROM_HANDLE(anv_device, device, _device);
1091
1092    switch (device->info.gen) {
1093    case 7:
1094       if (device->info.is_haswell)
1095          return gen75_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1096       else
1097          return gen7_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1098    case 8:
1099       return gen8_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1100    case 9:
1101       return gen9_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1102    default:
1103       unreachable("unsupported gen\n");
1104    }
1105 }
1106
1107 VkResult anv_CreateComputePipelines(
1108     VkDevice                                    _device,
1109     VkPipelineCache                             pipelineCache,
1110     uint32_t                                    count,
1111     const VkComputePipelineCreateInfo*          pCreateInfos,
1112     const VkAllocationCallbacks*                pAllocator,
1113     VkPipeline*                                 pPipelines)
1114 {
1115    VkResult result = VK_SUCCESS;
1116
1117    unsigned i = 0;
1118    for (; i < count; i++) {
1119       result = anv_compute_pipeline_create(_device, &pCreateInfos[i],
1120                                            pAllocator, &pPipelines[i]);
1121       if (result != VK_SUCCESS) {
1122          for (unsigned j = 0; j < i; j++) {
1123             anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1124          }
1125
1126          return result;
1127       }
1128    }
1129
1130    return VK_SUCCESS;
1131 }