2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "gen8_pack.h"
33 #include "gen9_pack.h"
36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
38 static const uint32_t push_constant_opcodes
[] = {
39 [MESA_SHADER_VERTEX
] = 21,
40 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
41 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
42 [MESA_SHADER_GEOMETRY
] = 22,
43 [MESA_SHADER_FRAGMENT
] = 23,
44 [MESA_SHADER_COMPUTE
] = 0,
47 VkShaderStageFlags flushed
= 0;
49 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
50 if (stage
== MESA_SHADER_COMPUTE
)
53 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
55 if (state
.offset
== 0)
58 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
),
59 ._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
61 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
62 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
65 flushed
|= mesa_to_vk_shader_stage(stage
);
68 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
75 emit_viewport_state(struct anv_cmd_buffer
*cmd_buffer
,
76 uint32_t count
, const VkViewport
*viewports
)
78 struct anv_state sf_clip_state
=
79 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
80 struct anv_state cc_state
=
81 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
83 for (uint32_t i
= 0; i
< count
; i
++) {
84 const VkViewport
*vp
= &viewports
[i
];
86 /* The gen7 state struct has just the matrix and guardband fields, the
87 * gen8 struct adds the min/max viewport fields. */
88 struct GENX(SF_CLIP_VIEWPORT
) sf_clip_viewport
= {
89 .ViewportMatrixElementm00
= vp
->width
/ 2,
90 .ViewportMatrixElementm11
= vp
->height
/ 2,
91 .ViewportMatrixElementm22
= 1.0,
92 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
93 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
94 .ViewportMatrixElementm32
= 0.0,
95 .XMinClipGuardband
= -1.0f
,
96 .XMaxClipGuardband
= 1.0f
,
97 .YMinClipGuardband
= -1.0f
,
98 .YMaxClipGuardband
= 1.0f
,
99 .XMinViewPort
= vp
->x
,
100 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
101 .YMinViewPort
= vp
->y
,
102 .YMaxViewPort
= vp
->y
+ vp
->height
- 1,
105 struct GENX(CC_VIEWPORT
) cc_viewport
= {
106 .MinimumDepth
= vp
->minDepth
,
107 .MaximumDepth
= vp
->maxDepth
110 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64,
112 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
115 if (!cmd_buffer
->device
->info
.has_llc
) {
116 anv_state_clflush(sf_clip_state
);
117 anv_state_clflush(cc_state
);
120 anv_batch_emit(&cmd_buffer
->batch
,
121 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
),
122 .CCViewportPointer
= cc_state
.offset
);
123 anv_batch_emit(&cmd_buffer
->batch
,
124 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
),
125 .SFClipViewportPointer
= sf_clip_state
.offset
);
129 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
131 if (cmd_buffer
->state
.dynamic
.viewport
.count
> 0) {
132 emit_viewport_state(cmd_buffer
, cmd_buffer
->state
.dynamic
.viewport
.count
,
133 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
135 /* If viewport count is 0, this is taken to mean "use the default" */
136 emit_viewport_state(cmd_buffer
, 1,
140 .width
= cmd_buffer
->state
.framebuffer
->width
,
141 .height
= cmd_buffer
->state
.framebuffer
->height
,
150 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
152 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
),
153 .RegisterOffset
= reg
,
157 #define GEN8_L3CNTLREG 0x7034
160 config_l3(struct anv_cmd_buffer
*cmd_buffer
, bool enable_slm
)
162 /* References for GL state:
164 * - commits e307cfa..228d5a3
165 * - src/mesa/drivers/dri/i965/gen7_l3_state.c
168 uint32_t val
= enable_slm
?
169 /* All = 48 ways; URB = 16 ways; DC and RO = 0, SLM = 1 */
171 /* All = 48 ways; URB = 48 ways; DC, RO and SLM = 0 */
173 bool changed
= cmd_buffer
->state
.current_l3_config
!= val
;
176 /* According to the hardware docs, the L3 partitioning can only be changed
177 * while the pipeline is completely drained and the caches are flushed,
178 * which involves a first PIPE_CONTROL flush which stalls the pipeline and
179 * initiates invalidation of the relevant caches...
181 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
182 .TextureCacheInvalidationEnable
= true,
183 .ConstantCacheInvalidationEnable
= true,
184 .InstructionCacheInvalidateEnable
= true,
185 .DCFlushEnable
= true,
186 .PostSyncOperation
= NoWrite
,
187 .CommandStreamerStallEnable
= true);
189 /* ...followed by a second stalling flush which guarantees that
190 * invalidation is complete when the L3 configuration registers are
193 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
194 .DCFlushEnable
= true,
195 .PostSyncOperation
= NoWrite
,
196 .CommandStreamerStallEnable
= true);
198 emit_lri(&cmd_buffer
->batch
, GEN8_L3CNTLREG
, val
);
199 cmd_buffer
->state
.current_l3_config
= val
;
204 __emit_genx_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
206 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
207 struct GENX(3DSTATE_SF
) sf
= {
208 GENX(3DSTATE_SF_header
),
209 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
211 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
213 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
214 cmd_buffer
->state
.pipeline
->gen8
.sf
);
217 __emit_gen9_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
219 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
220 struct GEN9_3DSTATE_SF sf
= {
221 GEN9_3DSTATE_SF_header
,
222 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
224 GEN9_3DSTATE_SF_pack(NULL
, sf_dw
, &sf
);
226 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
227 cmd_buffer
->state
.pipeline
->gen8
.sf
);
231 __emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
233 if (cmd_buffer
->device
->info
.is_cherryview
)
234 __emit_gen9_sf_state(cmd_buffer
);
236 __emit_genx_sf_state(cmd_buffer
);
240 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
242 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
245 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
247 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
249 config_l3(cmd_buffer
, false);
251 genX(flush_pipeline_select_3d
)(cmd_buffer
);
254 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
255 const uint32_t num_dwords
= 1 + num_buffers
* 4;
257 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
258 GENX(3DSTATE_VERTEX_BUFFERS
));
260 for_each_bit(vb
, vb_emit
) {
261 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
262 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
264 struct GENX(VERTEX_BUFFER_STATE
) state
= {
265 .VertexBufferIndex
= vb
,
266 .MemoryObjectControlState
= GENX(MOCS
),
267 .AddressModifyEnable
= true,
268 .BufferPitch
= pipeline
->binding_stride
[vb
],
269 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
270 .BufferSize
= buffer
->size
- offset
273 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
278 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
279 /* If somebody compiled a pipeline after starting a command buffer the
280 * scratch bo may have grown since we started this cmd buffer (and
281 * emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
282 * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
283 if (cmd_buffer
->state
.scratch_size
< pipeline
->total_scratch
)
284 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
286 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
289 /* We emit the binding tables and sampler tables first, then emit push
290 * constants and then finally emit binding table and sampler table
291 * pointers. It has to happen in this order, since emitting the binding
292 * tables may change the push constants (in case of storage images). After
293 * emitting push constants, on SKL+ we have to emit the corresponding
294 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
297 if (cmd_buffer
->state
.descriptors_dirty
)
298 dirty
= gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer
);
300 if (cmd_buffer
->state
.push_constants_dirty
)
301 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
304 gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
306 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
307 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
309 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
310 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
312 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
313 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
314 __emit_sf_state(cmd_buffer
);
317 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
318 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
319 bool enable_bias
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
!= 0.0f
||
320 cmd_buffer
->state
.dynamic
.depth_bias
.slope
!= 0.0f
;
322 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
323 struct GENX(3DSTATE_RASTER
) raster
= {
324 GENX(3DSTATE_RASTER_header
),
325 .GlobalDepthOffsetEnableSolid
= enable_bias
,
326 .GlobalDepthOffsetEnableWireframe
= enable_bias
,
327 .GlobalDepthOffsetEnablePoint
= enable_bias
,
328 .GlobalDepthOffsetConstant
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
,
329 .GlobalDepthOffsetScale
= cmd_buffer
->state
.dynamic
.depth_bias
.slope
,
330 .GlobalDepthOffsetClamp
= cmd_buffer
->state
.dynamic
.depth_bias
.clamp
332 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
333 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
334 pipeline
->gen8
.raster
);
337 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
338 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
339 * across different state packets for gen8 and gen9. We handle that by
340 * using a big old #if switch here.
343 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
344 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
345 struct anv_state cc_state
=
346 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
347 GEN8_COLOR_CALC_STATE_length
* 4,
349 struct GEN8_COLOR_CALC_STATE cc
= {
350 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
351 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
352 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
353 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
354 .StencilReferenceValue
=
355 cmd_buffer
->state
.dynamic
.stencil_reference
.front
,
356 .BackFaceStencilReferenceValue
=
357 cmd_buffer
->state
.dynamic
.stencil_reference
.back
,
359 GEN8_COLOR_CALC_STATE_pack(NULL
, cc_state
.map
, &cc
);
361 if (!cmd_buffer
->device
->info
.has_llc
)
362 anv_state_clflush(cc_state
);
364 anv_batch_emit(&cmd_buffer
->batch
,
365 GEN8_3DSTATE_CC_STATE_POINTERS
,
366 .ColorCalcStatePointer
= cc_state
.offset
,
367 .ColorCalcStatePointerValid
= true);
370 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
371 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
372 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
373 uint32_t wm_depth_stencil_dw
[GEN8_3DSTATE_WM_DEPTH_STENCIL_length
];
375 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
376 GEN8_3DSTATE_WM_DEPTH_STENCIL_header
,
378 /* Is this what we need to do? */
379 .StencilBufferWriteEnable
=
380 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
!= 0,
383 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
& 0xff,
385 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
& 0xff,
387 .BackfaceStencilTestMask
=
388 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
& 0xff,
389 .BackfaceStencilWriteMask
=
390 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
& 0xff,
392 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, wm_depth_stencil_dw
,
395 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
396 pipeline
->gen8
.wm_depth_stencil
);
399 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
400 struct anv_state cc_state
=
401 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
402 GEN9_COLOR_CALC_STATE_length
* 4,
404 struct GEN9_COLOR_CALC_STATE cc
= {
405 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
406 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
407 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
408 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
410 GEN9_COLOR_CALC_STATE_pack(NULL
, cc_state
.map
, &cc
);
412 if (!cmd_buffer
->device
->info
.has_llc
)
413 anv_state_clflush(cc_state
);
415 anv_batch_emit(&cmd_buffer
->batch
,
416 GEN9_3DSTATE_CC_STATE_POINTERS
,
417 .ColorCalcStatePointer
= cc_state
.offset
,
418 .ColorCalcStatePointerValid
= true);
421 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
422 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
423 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
424 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
425 uint32_t dwords
[GEN9_3DSTATE_WM_DEPTH_STENCIL_length
];
426 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
427 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
428 GEN9_3DSTATE_WM_DEPTH_STENCIL_header
,
430 .StencilBufferWriteEnable
= d
->stencil_write_mask
.front
!= 0,
432 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
433 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
435 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
436 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
438 .StencilReferenceValue
= d
->stencil_reference
.front
,
439 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
441 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, dwords
, &wm_depth_stencil
);
443 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
444 pipeline
->gen9
.wm_depth_stencil
);
448 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
449 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
450 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
),
451 .IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
,
452 .CutIndex
= cmd_buffer
->state
.restart_index
,
456 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
457 cmd_buffer
->state
.dirty
= 0;
460 void genX(CmdBindIndexBuffer
)(
461 VkCommandBuffer commandBuffer
,
464 VkIndexType indexType
)
466 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
467 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
469 static const uint32_t vk_to_gen_index_type
[] = {
470 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
471 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
474 static const uint32_t restart_index_for_type
[] = {
475 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
476 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
479 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
481 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
),
482 .IndexFormat
= vk_to_gen_index_type
[indexType
],
483 .MemoryObjectControlState
= GENX(MOCS
),
484 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
485 .BufferSize
= buffer
->size
- offset
);
487 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
491 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
493 struct anv_device
*device
= cmd_buffer
->device
;
494 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
495 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
498 result
= anv_cmd_buffer_emit_samplers(cmd_buffer
,
499 MESA_SHADER_COMPUTE
, &samplers
);
500 if (result
!= VK_SUCCESS
)
502 result
= anv_cmd_buffer_emit_binding_table(cmd_buffer
,
503 MESA_SHADER_COMPUTE
, &surfaces
);
504 if (result
!= VK_SUCCESS
)
507 struct anv_state push_state
= anv_cmd_buffer_cs_push_constants(cmd_buffer
);
509 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
510 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
512 unsigned local_id_dwords
= cs_prog_data
->local_invocation_id_regs
* 8;
513 unsigned push_constant_data_size
=
514 (prog_data
->nr_params
+ local_id_dwords
) * 4;
515 unsigned reg_aligned_constant_size
= ALIGN(push_constant_data_size
, 32);
516 unsigned push_constant_regs
= reg_aligned_constant_size
/ 32;
518 if (push_state
.alloc_size
) {
519 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
),
520 .CURBETotalDataLength
= push_state
.alloc_size
,
521 .CURBEDataStartAddress
= push_state
.offset
);
524 assert(prog_data
->total_shared
<= 64 * 1024);
525 uint32_t slm_size
= 0;
526 if (prog_data
->total_shared
> 0) {
527 /* slm_size is in 4k increments, but must be a power of 2. */
529 while (slm_size
< prog_data
->total_shared
)
531 slm_size
/= 4 * 1024;
534 struct anv_state state
=
535 anv_state_pool_emit(&device
->dynamic_state_pool
,
536 GENX(INTERFACE_DESCRIPTOR_DATA
), 64,
537 .KernelStartPointer
= pipeline
->cs_simd
,
538 .KernelStartPointerHigh
= 0,
539 .BindingTablePointer
= surfaces
.offset
,
540 .BindingTableEntryCount
= 0,
541 .SamplerStatePointer
= samplers
.offset
,
543 .ConstantIndirectURBEntryReadLength
= push_constant_regs
,
544 .ConstantURBEntryReadOffset
= 0,
545 .BarrierEnable
= cs_prog_data
->uses_barrier
,
546 .SharedLocalMemorySize
= slm_size
,
547 .NumberofThreadsinGPGPUThreadGroup
=
548 pipeline
->cs_thread_width_max
);
550 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
551 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
),
552 .InterfaceDescriptorTotalLength
= size
,
553 .InterfaceDescriptorDataStartAddress
= state
.offset
);
559 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
561 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
564 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
566 bool needs_slm
= pipeline
->cs_prog_data
.base
.total_shared
> 0;
567 config_l3(cmd_buffer
, needs_slm
);
569 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
571 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
573 * Software must clear the COLOR_CALC_STATE Valid field in
574 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
575 * with Pipeline Select set to GPGPU.
577 * The internal hardware docs recommend the same workaround for Gen9
580 anv_batch_emit(&cmd_buffer
->batch
,
581 GENX(3DSTATE_CC_STATE_POINTERS
));
584 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
),
588 .PipelineSelection
= GPGPU
);
589 cmd_buffer
->state
.current_pipeline
= GPGPU
;
592 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)
593 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
595 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
596 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
597 result
= flush_compute_descriptor_set(cmd_buffer
);
598 assert(result
== VK_SUCCESS
);
599 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
602 cmd_buffer
->state
.compute_dirty
= 0;
606 emit_ps_depth_count(struct anv_batch
*batch
,
607 struct anv_bo
*bo
, uint32_t offset
)
609 anv_batch_emit(batch
, GENX(PIPE_CONTROL
),
610 .DestinationAddressType
= DAT_PPGTT
,
611 .PostSyncOperation
= WritePSDepthCount
,
612 .DepthStallEnable
= true,
613 .Address
= { bo
, offset
});
617 emit_query_availability(struct anv_batch
*batch
,
618 struct anv_bo
*bo
, uint32_t offset
)
620 anv_batch_emit(batch
, GENX(PIPE_CONTROL
),
621 .DestinationAddressType
= DAT_PPGTT
,
622 .PostSyncOperation
= WriteImmediateData
,
623 .Address
= { bo
, offset
},
627 void genX(CmdBeginQuery
)(
628 VkCommandBuffer commandBuffer
,
629 VkQueryPool queryPool
,
631 VkQueryControlFlags flags
)
633 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
634 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
636 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
637 * that the pipelining of the depth write breaks. What we see is that
638 * samples from the render pass clear leaks into the first query
639 * immediately after the clear. Doing a pipecontrol with a post-sync
640 * operation and DepthStallEnable seems to work around the issue.
642 if (cmd_buffer
->state
.need_query_wa
) {
643 cmd_buffer
->state
.need_query_wa
= false;
644 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
645 .DepthCacheFlushEnable
= true,
646 .DepthStallEnable
= true);
649 switch (pool
->type
) {
650 case VK_QUERY_TYPE_OCCLUSION
:
651 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
652 query
* sizeof(struct anv_query_pool_slot
));
655 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
661 void genX(CmdEndQuery
)(
662 VkCommandBuffer commandBuffer
,
663 VkQueryPool queryPool
,
666 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
667 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
669 switch (pool
->type
) {
670 case VK_QUERY_TYPE_OCCLUSION
:
671 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
672 query
* sizeof(struct anv_query_pool_slot
) + 8);
674 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
,
675 query
* sizeof(struct anv_query_pool_slot
) + 16);
678 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
684 #define TIMESTAMP 0x2358
686 void genX(CmdWriteTimestamp
)(
687 VkCommandBuffer commandBuffer
,
688 VkPipelineStageFlagBits pipelineStage
,
689 VkQueryPool queryPool
,
692 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
693 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
694 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
696 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
698 switch (pipelineStage
) {
699 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
700 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
),
701 .RegisterAddress
= TIMESTAMP
,
702 .MemoryAddress
= { &pool
->bo
, offset
});
703 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
),
704 .RegisterAddress
= TIMESTAMP
+ 4,
705 .MemoryAddress
= { &pool
->bo
, offset
+ 4 });
709 /* Everything else is bottom-of-pipe */
710 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
711 .DestinationAddressType
= DAT_PPGTT
,
712 .PostSyncOperation
= WriteTimestamp
,
713 .Address
= { &pool
->bo
, offset
});
717 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
, query
+ 16);
720 #define alu_opcode(v) __gen_uint((v), 20, 31)
721 #define alu_operand1(v) __gen_uint((v), 10, 19)
722 #define alu_operand2(v) __gen_uint((v), 0, 9)
723 #define alu(opcode, operand1, operand2) \
724 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
726 #define OPCODE_NOOP 0x000
727 #define OPCODE_LOAD 0x080
728 #define OPCODE_LOADINV 0x480
729 #define OPCODE_LOAD0 0x081
730 #define OPCODE_LOAD1 0x481
731 #define OPCODE_ADD 0x100
732 #define OPCODE_SUB 0x101
733 #define OPCODE_AND 0x102
734 #define OPCODE_OR 0x103
735 #define OPCODE_XOR 0x104
736 #define OPCODE_STORE 0x180
737 #define OPCODE_STOREINV 0x580
739 #define OPERAND_R0 0x00
740 #define OPERAND_R1 0x01
741 #define OPERAND_R2 0x02
742 #define OPERAND_R3 0x03
743 #define OPERAND_R4 0x04
744 #define OPERAND_SRCA 0x20
745 #define OPERAND_SRCB 0x21
746 #define OPERAND_ACCU 0x31
747 #define OPERAND_ZF 0x32
748 #define OPERAND_CF 0x33
750 #define CS_GPR(n) (0x2600 + (n) * 8)
753 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
754 struct anv_bo
*bo
, uint32_t offset
)
756 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
757 .RegisterAddress
= reg
,
758 .MemoryAddress
= { bo
, offset
});
759 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
760 .RegisterAddress
= reg
+ 4,
761 .MemoryAddress
= { bo
, offset
+ 4 });
765 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
766 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
768 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
),
769 .RegisterAddress
= reg
,
770 .MemoryAddress
= { bo
, offset
});
772 if (flags
& VK_QUERY_RESULT_64_BIT
)
773 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
),
774 .RegisterAddress
= reg
+ 4,
775 .MemoryAddress
= { bo
, offset
+ 4 });
778 void genX(CmdCopyQueryPoolResults
)(
779 VkCommandBuffer commandBuffer
,
780 VkQueryPool queryPool
,
784 VkDeviceSize destOffset
,
785 VkDeviceSize destStride
,
786 VkQueryResultFlags flags
)
788 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
789 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
790 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
791 uint32_t slot_offset
, dst_offset
;
793 if (flags
& VK_QUERY_RESULT_WAIT_BIT
)
794 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
795 .CommandStreamerStallEnable
= true,
796 .StallAtPixelScoreboard
= true);
798 dst_offset
= buffer
->offset
+ destOffset
;
799 for (uint32_t i
= 0; i
< queryCount
; i
++) {
801 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
802 switch (pool
->type
) {
803 case VK_QUERY_TYPE_OCCLUSION
:
804 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
805 CS_GPR(0), &pool
->bo
, slot_offset
);
806 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
807 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
809 /* FIXME: We need to clamp the result for 32 bit. */
811 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
812 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
813 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
814 dw
[3] = alu(OPCODE_SUB
, 0, 0);
815 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
818 case VK_QUERY_TYPE_TIMESTAMP
:
819 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
820 CS_GPR(2), &pool
->bo
, slot_offset
);
824 unreachable("unhandled query type");
827 store_query_result(&cmd_buffer
->batch
,
828 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
830 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
831 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
832 &pool
->bo
, slot_offset
+ 16);
833 if (flags
& VK_QUERY_RESULT_64_BIT
)
834 store_query_result(&cmd_buffer
->batch
,
835 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
837 store_query_result(&cmd_buffer
->batch
,
838 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
841 dst_offset
+= destStride
;
845 void genX(CmdSetEvent
)(
846 VkCommandBuffer commandBuffer
,
848 VkPipelineStageFlags stageMask
)
850 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
851 ANV_FROM_HANDLE(anv_event
, event
, _event
);
853 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
854 .DestinationAddressType
= DAT_PPGTT
,
855 .PostSyncOperation
= WriteImmediateData
,
857 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
860 .ImmediateData
= VK_EVENT_SET
);
863 void genX(CmdResetEvent
)(
864 VkCommandBuffer commandBuffer
,
866 VkPipelineStageFlags stageMask
)
868 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
869 ANV_FROM_HANDLE(anv_event
, event
, _event
);
871 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
872 .DestinationAddressType
= DAT_PPGTT
,
873 .PostSyncOperation
= WriteImmediateData
,
875 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
878 .ImmediateData
= VK_EVENT_RESET
);
881 void genX(CmdWaitEvents
)(
882 VkCommandBuffer commandBuffer
,
884 const VkEvent
* pEvents
,
885 VkPipelineStageFlags srcStageMask
,
886 VkPipelineStageFlags destStageMask
,
887 uint32_t memoryBarrierCount
,
888 const VkMemoryBarrier
* pMemoryBarriers
,
889 uint32_t bufferMemoryBarrierCount
,
890 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
891 uint32_t imageMemoryBarrierCount
,
892 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
894 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
895 for (uint32_t i
= 0; i
< eventCount
; i
++) {
896 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
898 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
),
899 .WaitMode
= PollingMode
,
900 .CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
901 .SemaphoreDataDword
= VK_EVENT_SET
,
902 .SemaphoreAddress
= {
903 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
908 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
909 false, /* byRegion */
910 memoryBarrierCount
, pMemoryBarriers
,
911 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
912 imageMemoryBarrierCount
, pImageMemoryBarriers
);