nir: Add a new memory_barrier_tcs_patch intrinsic

[mesa.git] / src / intel / compiler / brw_vec4_tcs.cpp

diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp
index 9d6c4f326a447f2cc55caf5426b35aaf3133a420..e539657335ca1d91ac2312e4c3bcdc8188c178f7 100644 (file)
--- a/src/intel/compiler/brw_vec4_tcs.cpp
+++ b/src/intel/compiler/brw_vec4_tcs.cpp
@@ -315,6 +315,9 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
       break;
    }
 
+   case nir_intrinsic_memory_barrier_tcs_patch:
+      break;
+
    default:
       vec4_visitor::nir_emit_intrinsic(instr);
    }
@@ -360,12 +363,13 @@ brw_compile_tcs(const struct brw_compiler *compiler,
       nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID);
 
    if (compiler->use_tcs_8_patch &&
-       nir->info.tess.tcs_vertices_out <= 16 &&
+       nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) &&
        2 + has_primitive_id + key->input_vertices <= 31) {
-      /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode.  First,
-       * the "Instance" field limits the number of output vertices to [1, 16].
-       * Secondly, the "Dispatch GRF Start Register for URB Data" field is
-       * limited to [0, 31] - which imposes a limit on the input vertices.
+      /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the
+       * "Instance" field limits the number of output vertices to [1, 16] on
+       * gen11 and below, or [1, 32] on gen12 and above. Secondly, the
+       * "Dispatch GRF Start Register for URB Data" field is limited to [0,
+       * 31] - which imposes a limit on the input vertices.
        */
       vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH;
       prog_data->instances = nir->info.tess.tcs_vertices_out;