GL_ARB_indirect_parameters DONE (nvc0, radeonsi)
GL_ARB_parallel_shader_compile not started, but Chia-I Wu did some related work in 2014
GL_ARB_pipeline_statistics_query DONE (i965, nvc0, radeonsi, softpipe, swr)
- GL_ARB_post_depth_coverage not started
+ GL_ARB_post_depth_coverage DONE (i965)
GL_ARB_robustness_isolation not started
GL_ARB_sample_locations not started
GL_ARB_seamless_cubemap_per_texture DONE (i965, nvc0, radeonsi, r600, softpipe, swr)
</p>
<ul>
+<li>GL_ARB_post_depth_coverage on i965/gen9+</li>
<li>GL_NV_image_formats on any driver supporting GL_ARB_shader_image_load_store (i965, nvc0, radeonsi, softpipe)</li>
</ul>
bool computed_stencil;
bool early_fragment_tests;
+ bool post_depth_coverage;
bool dispatch_8;
bool dispatch_16;
bool dual_src_blend;
shader->info->outputs_read);
prog_data->early_fragment_tests = shader->info->fs.early_fragment_tests;
+ prog_data->post_depth_coverage = shader->info->fs.post_depth_coverage;
prog_data->barycentric_interp_modes =
brw_compute_barycentric_interp_modes(compiler->devinfo, shader);
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
if (prog_data->uses_sample_mask) {
- if (brw->gen >= 9)
- dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
- else
+ if (brw->gen >= 9) {
+ if (prog_data->post_depth_coverage) {
+ dw1 |= BRW_PCICMS_DEPTH << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
+ }
+ else {
+ dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
+ }
+ }
+ else {
dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
+ }
}
if (prog_data->uses_omask)
ctx->Extensions.KHR_texture_compression_astc_ldr = true;
ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
ctx->Extensions.MESA_shader_framebuffer_fetch = true;
+ ctx->Extensions.ARB_post_depth_coverage = true;
}
if (ctx->API == API_OPENGL_CORE)