}
}
-static void
-gen4_emit_buffer_surface_state(struct brw_context *brw,
- uint32_t *out_offset,
- drm_intel_bo *bo,
- unsigned buffer_offset,
- unsigned surface_format,
- unsigned buffer_size,
- unsigned pitch,
- bool rw)
+void
+brw_emit_buffer_surface_state(struct brw_context *brw,
+ uint32_t *out_offset,
+ drm_intel_bo *bo,
+ unsigned buffer_offset,
+ unsigned surface_format,
+ unsigned buffer_size,
+ unsigned pitch,
+ bool rw)
{
- unsigned elements = buffer_size / pitch;
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, out_offset);
- memset(surf, 0, 6 * 4);
+ const struct surface_state_info ss_info = surface_state_infos[brw->gen];
+
+ uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ ss_info.num_dwords * 4, ss_info.ss_align,
+ out_offset);
+
+ isl_buffer_fill_state(&brw->isl_dev, dw,
+ .address = (bo ? bo->offset64 : 0) + buffer_offset,
+ .size = buffer_size,
+ .format = surface_format,
+ .stride = pitch,
+ .mocs = ss_info.tex_mocs);
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- (brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
- surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
- surf[2] = ((elements - 1) & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
- (((elements - 1) >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
- surf[3] = (((elements - 1) >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
- (pitch - 1) << BRW_SURFACE_PITCH_SHIFT;
-
- /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
- * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
- * physical cache. It is mapped in hardware to the sampler cache."
- */
if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
+ drm_intel_bo_emit_reloc(brw->batch.bo,
+ *out_offset + 4 * ss_info.reloc_dw,
bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
_mesa_get_format_name(format));
}
- brw->vtbl.emit_buffer_surface_state(brw, surf_offset, bo,
- tObj->BufferOffset,
- brw_format,
- size,
- texel_size,
- false /* rw */);
+ brw_emit_buffer_surface_state(brw, surf_offset, bo,
+ tObj->BufferOffset,
+ brw_format,
+ size,
+ texel_size,
+ false /* rw */);
}
/**
uint32_t size,
uint32_t *out_offset)
{
- brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
- BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
- size, 1, false);
+ brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
+ BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
+ size, 1, false);
}
/**
* include a pixel mask header that we need to ensure correct behavior
* with helper invocations, which cannot write to the buffer.
*/
- brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
- BRW_SURFACEFORMAT_RAW,
- size, 1, true);
+ brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
+ BRW_SURFACEFORMAT_RAW,
+ size, 1, true);
}
/**
drm_intel_bo *bo = intel_bufferobj_buffer(
brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset);
- brw->vtbl.emit_buffer_surface_state(brw, &surf_offsets[i], bo,
- binding->Offset, BRW_SURFACEFORMAT_RAW,
- bo->size - binding->Offset, 1, true);
+ brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo,
+ binding->Offset, BRW_SURFACEFORMAT_RAW,
+ bo->size - binding->Offset, 1, true);
}
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
const unsigned texel_size = (format == BRW_SURFACEFORMAT_RAW ? 1 :
_mesa_get_format_bytes(u->_ActualFormat));
- brw->vtbl.emit_buffer_surface_state(
+ brw_emit_buffer_surface_state(
brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
format, intel_obj->Base.Size, texel_size,
access != GL_READ_ONLY);
struct intel_mipmap_tree *mt = intel_obj->mt;
if (format == BRW_SURFACEFORMAT_RAW) {
- brw->vtbl.emit_buffer_surface_state(
+ brw_emit_buffer_surface_state(
brw, surf_offset, mt->bo, mt->offset,
format, mt->bo->size - mt->offset, 1 /* pitch */,
access != GL_READ_ONLY);
brw->vtbl.update_texture_surface = brw_update_texture_surface;
brw->vtbl.update_renderbuffer_surface = gen4_update_renderbuffer_surface;
brw->vtbl.emit_null_surface_state = brw_emit_null_surface_state;
- brw->vtbl.emit_buffer_surface_state = gen4_emit_buffer_surface_state;
}
static void
bo_offset = brw->compute.num_work_groups_offset;
}
- brw->vtbl.emit_buffer_surface_state(brw, surf_offset,
- bo, bo_offset,
- BRW_SURFACEFORMAT_RAW,
- 3 * sizeof(GLuint), 1, true);
+ brw_emit_buffer_surface_state(brw, surf_offset,
+ bo, bo_offset,
+ BRW_SURFACEFORMAT_RAW,
+ 3 * sizeof(GLuint), 1, true);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
}
}
}
-static void
-gen7_emit_buffer_surface_state(struct brw_context *brw,
- uint32_t *out_offset,
- drm_intel_bo *bo,
- unsigned buffer_offset,
- unsigned surface_format,
- unsigned buffer_size,
- unsigned pitch,
- bool rw)
-{
- unsigned elements = buffer_size / pitch;
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, out_offset);
- memset(surf, 0, 8 * 4);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
- surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
- surf[2] = SET_FIELD((elements - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD(((elements - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
- if (surface_format == BRW_SURFACEFORMAT_RAW)
- surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
- else
- surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
- surf[3] |= (pitch - 1);
-
- surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
-
- if (brw->is_haswell) {
- surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
- }
-
- /* Emit relocation to surface contents */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- }
-
- gen7_check_surface_setup(surf, false /* is_render_target */);
-}
-
/**
* Creates a null surface.
*
brw->vtbl.update_texture_surface = brw_update_texture_surface;
brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
brw->vtbl.emit_null_surface_state = gen7_emit_null_surface_state;
- brw->vtbl.emit_buffer_surface_state = gen7_emit_buffer_surface_state;
}
return surf;
}
-static void
-gen8_emit_buffer_surface_state(struct brw_context *brw,
- uint32_t *out_offset,
- drm_intel_bo *bo,
- unsigned buffer_offset,
- unsigned surface_format,
- unsigned buffer_size,
- unsigned pitch,
- bool rw)
-{
- unsigned elements = buffer_size / pitch;
- const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1);
-
- surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- surface_format << BRW_SURFACE_FORMAT_SHIFT |
- BRW_SURFACE_RC_READ_WRITE;
- surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
-
- surf[2] = SET_FIELD((elements - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
- SET_FIELD(((elements - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
- if (surface_format == BRW_SURFACEFORMAT_RAW)
- surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
- else
- surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
- surf[3] |= (pitch - 1);
- surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
- SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
- SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
- SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
- /* reloc */
- *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
-
- /* Emit relocation to surface contents. */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- rw ? I915_GEM_DOMAIN_SAMPLER : 0);
- }
-}
-
/**
* Creates a null surface.
*
brw->vtbl.update_texture_surface = brw_update_texture_surface;
brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
- brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
}
projects / mesa.git / commitdiff