freedreno/a6xx: wire up dither state
authorRob Clark <robdclark@chromium.org>
Thu, 27 Jun 2019 20:37:21 +0000 (13:37 -0700)
committerRob Clark <robdclark@chromium.org>
Fri, 28 Jun 2019 20:02:59 +0000 (13:02 -0700)
Fixes:
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.no_rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.no_rebind_rbo_rgba4_stencil_index8

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
src/gallium/drivers/freedreno/a6xx/fd6_blend.c
src/gallium/drivers/freedreno/a6xx/fd6_blend.h
src/gallium/drivers/freedreno/a6xx/fd6_emit.c

index f888e162cf9a9424c46c40c707fe237cb07377e3..f010b1c507c93744477cd04db87608a178834473 100644 (file)
@@ -132,9 +132,17 @@ fd6_blend_state_create(struct pipe_context *pctx,
 //                     so->rb_mrt[i].control |= A6XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
                        mrt_blend |= (1 << i);
                }
+       }
 
-//             if (cso->dither)
-//                     so->rb_mrt[i].buf_info |= A6XX_RB_MRT_BUF_INFO_DITHER_MODE(DITHER_ALWAYS);
+       if (cso->dither) {
+               so->rb_dither_cntl = A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(DITHER_ALWAYS) |
+                               A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(DITHER_ALWAYS) |
+                               A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(DITHER_ALWAYS) |
+                               A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(DITHER_ALWAYS) |
+                               A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(DITHER_ALWAYS) |
+                               A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(DITHER_ALWAYS) |
+                               A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(DITHER_ALWAYS) |
+                               A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(DITHER_ALWAYS);
        }
 
        so->rb_blend_cntl = A6XX_RB_BLEND_CNTL_ENABLE_BLEND(mrt_blend) |
index d59b6628c5b529d9d0e06b654a01e65d8b922af0..d44ed8afb8861dba74f3f499638f9d332dacada8 100644 (file)
@@ -47,6 +47,7 @@ struct fd6_blend_stateobj {
                uint32_t blend_control_alpha;
        } rb_mrt[A6XX_MAX_RENDER_TARGETS];
        uint32_t rb_blend_cntl;
+       uint32_t rb_dither_cntl;
        uint32_t sp_blend_cntl;
 };
 
index 1240786e4dd10143306b740c0352bd9bffe4e935..5e8a65c9dd73159fc5fba37a13b333ac35396b28 100644 (file)
@@ -984,6 +984,9 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
                        OUT_RING(ring, blend_control);
                }
 
+               OUT_PKT4(ring, REG_A6XX_RB_DITHER_CNTL, 1);
+               OUT_RING(ring, blend->rb_dither_cntl);
+
                OUT_PKT4(ring, REG_A6XX_SP_BLEND_CNTL, 1);
                OUT_RING(ring, blend->sp_blend_cntl);
        }