amd/common,radv: move vertex_format_table to ac_shader_util.{h,c}

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>

diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index eb6b88bd570f5f9e0fb9d2d0f52e80b910a59af0..030c07c49ef83e3845c25c111f2f5fb94b67e550 100644 (file)
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -159,6 +159,31 @@ ac_get_tbuffer_format(enum chip_class chip_class,
        }
 }
 
+static const struct ac_data_format_info data_format_table[] = {
+       [V_008F0C_BUF_DATA_FORMAT_INVALID]     = {  0, 4, 0, V_008F0C_BUF_DATA_FORMAT_INVALID    },
+       [V_008F0C_BUF_DATA_FORMAT_8]           = {  1, 1, 1, V_008F0C_BUF_DATA_FORMAT_8          },
+       [V_008F0C_BUF_DATA_FORMAT_16]          = {  2, 1, 2, V_008F0C_BUF_DATA_FORMAT_16         },
+       [V_008F0C_BUF_DATA_FORMAT_8_8]         = {  2, 2, 1, V_008F0C_BUF_DATA_FORMAT_8          },
+       [V_008F0C_BUF_DATA_FORMAT_32]          = {  4, 1, 4, V_008F0C_BUF_DATA_FORMAT_32         },
+       [V_008F0C_BUF_DATA_FORMAT_16_16]       = {  4, 2, 2, V_008F0C_BUF_DATA_FORMAT_16         },
+       [V_008F0C_BUF_DATA_FORMAT_10_11_11]    = {  4, 3, 0, V_008F0C_BUF_DATA_FORMAT_10_11_11   },
+       [V_008F0C_BUF_DATA_FORMAT_11_11_10]    = {  4, 3, 0, V_008F0C_BUF_DATA_FORMAT_11_11_10   },
+       [V_008F0C_BUF_DATA_FORMAT_10_10_10_2]  = {  4, 4, 0, V_008F0C_BUF_DATA_FORMAT_10_10_10_2 },
+       [V_008F0C_BUF_DATA_FORMAT_2_10_10_10]  = {  4, 4, 0, V_008F0C_BUF_DATA_FORMAT_2_10_10_10 },
+       [V_008F0C_BUF_DATA_FORMAT_8_8_8_8]     = {  4, 4, 1, V_008F0C_BUF_DATA_FORMAT_8          },
+       [V_008F0C_BUF_DATA_FORMAT_32_32]       = {  8, 2, 4, V_008F0C_BUF_DATA_FORMAT_32         },
+       [V_008F0C_BUF_DATA_FORMAT_16_16_16_16] = {  8, 4, 2, V_008F0C_BUF_DATA_FORMAT_16         },
+       [V_008F0C_BUF_DATA_FORMAT_32_32_32]    = { 12, 3, 4, V_008F0C_BUF_DATA_FORMAT_32         },
+       [V_008F0C_BUF_DATA_FORMAT_32_32_32_32] = { 16, 4, 4, V_008F0C_BUF_DATA_FORMAT_32         },
+};
+
+const struct ac_data_format_info *
+ac_get_data_format_info(unsigned dfmt)
+{
+       assert(dfmt < ARRAY_SIZE(data_format_table));
+       return &data_format_table[dfmt];
+}
+
 enum ac_image_dim
 ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim,
                   bool is_array)

diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
index 20b291256eb808a38eb09de471e8227b9a4747fb..b851af270897050963466d1f9822c4331cd40e38 100644 (file)
--- a/src/amd/common/ac_shader_util.h
+++ b/src/amd/common/ac_shader_util.h
@@ -46,6 +46,13 @@ enum ac_image_dim {
        ac_image_2darraymsaa,
 };
 
+struct ac_data_format_info {
+       uint8_t element_size;
+       uint8_t num_channels;
+       uint8_t chan_byte_size;
+       uint8_t chan_format;
+};
+
 unsigned
 ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
                           bool writes_samplemask);
@@ -60,6 +67,9 @@ unsigned
 ac_get_tbuffer_format(enum chip_class chip_class,
                      unsigned dfmt, unsigned nfmt);
 
+const struct ac_data_format_info *
+ac_get_data_format_info(unsigned dfmt);
+
 enum ac_image_dim
 ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim,
                   bool is_array);

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 875bee050c79cc6ffa3bc3b153a5aa2bc3accd37..58b679a35ae22e4c989549bb20a6720012935df3 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1280,29 +1280,6 @@ adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
        return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
 }
 
-static const struct vertex_format_info {
-       uint8_t vertex_byte_size;
-       uint8_t num_channels;
-       uint8_t chan_byte_size;
-       uint8_t chan_format;
-} vertex_format_table[] = {
-       {  0, 4, 0, V_008F0C_BUF_DATA_FORMAT_INVALID    },      /* BUF_DATA_FORMAT_INVALID      */
-       {  1, 1, 1, V_008F0C_BUF_DATA_FORMAT_8          },      /* BUF_DATA_FORMAT_8            */
-       {  2, 1, 2, V_008F0C_BUF_DATA_FORMAT_16         },      /* BUF_DATA_FORMAT_16           */
-       {  2, 2, 1, V_008F0C_BUF_DATA_FORMAT_8          },      /* BUF_DATA_FORMAT_8_8          */
-       {  4, 1, 4, V_008F0C_BUF_DATA_FORMAT_32         },      /* BUF_DATA_FORMAT_32           */
-       {  4, 2, 2, V_008F0C_BUF_DATA_FORMAT_16         },      /* BUF_DATA_FORMAT_16_16        */
-       {  4, 3, 0, V_008F0C_BUF_DATA_FORMAT_10_11_11   },      /* BUF_DATA_FORMAT_10_11_11     */
-       {  4, 3, 0, V_008F0C_BUF_DATA_FORMAT_11_11_10   },      /* BUF_DATA_FORMAT_11_11_10     */
-       {  4, 4, 0, V_008F0C_BUF_DATA_FORMAT_10_10_10_2 },      /* BUF_DATA_FORMAT_10_10_10_2   */
-       {  4, 4, 0, V_008F0C_BUF_DATA_FORMAT_2_10_10_10 },      /* BUF_DATA_FORMAT_2_10_10_10   */
-       {  4, 4, 1, V_008F0C_BUF_DATA_FORMAT_8          },      /* BUF_DATA_FORMAT_8_8_8_8      */
-       {  8, 2, 4, V_008F0C_BUF_DATA_FORMAT_32         },      /* BUF_DATA_FORMAT_32_32        */
-       {  8, 4, 2, V_008F0C_BUF_DATA_FORMAT_16         },      /* BUF_DATA_FORMAT_16_16_16_16  */
-       { 12, 3, 4, V_008F0C_BUF_DATA_FORMAT_32         },      /* BUF_DATA_FORMAT_32_32_32     */
-       { 16, 4, 4, V_008F0C_BUF_DATA_FORMAT_32         },      /* BUF_DATA_FORMAT_32_32_32_32  */
-};
-
 static LLVMValueRef
 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
                                LLVMValueRef value,
@@ -1387,8 +1364,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
                                                               ctx->args->ac.base_vertex), "");
                }
 
-               assert(data_format < ARRAY_SIZE(vertex_format_table));
-               const struct vertex_format_info *vtx_info = &vertex_format_table[data_format];
+               const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
 
                /* Adjust the number of channels to load based on the vertex
                 * attribute format.
@@ -1414,8 +1390,8 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
                bool unaligned_vertex_fetches = false;
                if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
                    vtx_info->chan_format != data_format &&
-                   ((attrib_offset % vtx_info->vertex_byte_size) ||
-                    (attrib_stride % vtx_info->vertex_byte_size)))
+                   ((attrib_offset % vtx_info->element_size) ||
+                    (attrib_stride % vtx_info->element_size)))
                        unaligned_vertex_fetches = true;
 
                if (unaligned_vertex_fetches) {