r600g: HW bug workaround for TGSI_OPCODE_BREAKC
authorChristoph Bumiller <christoph.bumiller@speed.at>
Fri, 16 May 2014 23:20:17 +0000 (01:20 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 2 Jun 2014 10:49:03 +0000 (12:49 +0200)
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/r600/r600_asm.c
src/gallium/drivers/r600/r600_asm.h
src/gallium/drivers/r600/r600_shader.c

index 67df2f2acd30fcf90caba0804748128bacc9099a..e75f7d622c6f810bbf1f5df43ed1e48ca99760b1 100644 (file)
@@ -143,6 +143,7 @@ void r600_bytecode_init(struct r600_bytecode *bc,
 
        LIST_INITHEAD(&bc->cf);
        bc->chip_class = chip_class;
+       bc->family = family;
        bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
        bc->stack.entry_size = stack_entry_size(family);
 }
index 4fb0ef06956a8d61c5bad27f492cdb596f82ea15..48ea3c4bc43ae4cc30ca762afc5a74ae21d8b3c9 100644 (file)
@@ -196,6 +196,7 @@ struct r600_stack_info {
 
 struct r600_bytecode {
        enum chip_class                 chip_class;
+       enum radeon_family              family;
        bool                            has_compressed_msaa_texturing;
        int                             type;
        struct list_head                cf;
index 5823ba2e857cc1c8cbaf699d76acdcdedae50836..a4ed796b76874ebb32037ba126ffe495dc9bf4a1 100644 (file)
@@ -6280,10 +6280,26 @@ static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
                return -EINVAL;
        }
 
-       r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
-       if (r)
-               return r;
-       fc_set_mid(ctx, fscp);
+       if (ctx->bc->chip_class == EVERGREEN &&
+           ctx->bc->family != CHIP_CYPRESS &&
+           ctx->bc->family != CHIP_JUNIPER) {
+               /* HW bug: ALU_BREAK does not save the active mask correctly */
+               r = tgsi_uif(ctx);
+               if (r)
+                       return r;
+
+               r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
+               if (r)
+                       return r;
+               fc_set_mid(ctx, fscp);
+
+               return tgsi_endif(ctx);
+       } else {
+               r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
+               if (r)
+                       return r;
+               fc_set_mid(ctx, fscp);
+       }
 
        return 0;
 }