radeonsi/sdma: implement tmz support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 74c289b01349bce4329d249bb6c03f49fe98cd86..de0759ea387796583d6229a2cb6c0f87304c00e6 100644 (file)
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -112,8 +112,9 @@ static bool si_sdma_v4_copy_texture(struct si_context *sctx, struct pipe_resourc
          return false;
 
       radeon_emit(
          return false;
 
       radeon_emit(

-         cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
-                (util_logbase2(bpp) << 29));
+         cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW,
+                             sctx->ws->cs_is_secure(cs) ? (1u << 2) : 0) |
+                             (util_logbase2(bpp) << 29));

       radeon_emit(cs, src_address);
       radeon_emit(cs, src_address >> 32);
       radeon_emit(cs, srcx | (srcy << 16));
       radeon_emit(cs, src_address);
       radeon_emit(cs, src_address >> 32);
       radeon_emit(cs, srcx | (srcy << 16));


@@ -173,9 +174,10 @@ static bool si_sdma_v4_copy_texture(struct si_context *sctx, struct pipe_resourc
       si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
 
       radeon_emit(
       si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
 
       radeon_emit(

-         cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
-                tiled->buffer.b.b.last_level << 20 | tiled_level << 24 |
-                (linear == sdst ? 1u : 0) << 31);
+         cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW,
+                             sctx->ws->cs_is_secure(cs) ? (1u << 2) : 0) |
+             tiled->buffer.b.b.last_level << 20 | tiled_level << 24 |
+             (linear == sdst ? 1u : 0) << 31);

       radeon_emit(cs, (uint32_t)tiled_address);
       radeon_emit(cs, (uint32_t)(tiled_address >> 32));
       radeon_emit(cs, tiled_x | (tiled_y << 16));
       radeon_emit(cs, (uint32_t)tiled_address);
       radeon_emit(cs, (uint32_t)(tiled_address >> 32));
       radeon_emit(cs, tiled_x | (tiled_y << 16));

diff --git a/src/gallium/drivers/radeonsi/si_dma_cs.c b/src/gallium/drivers/radeonsi/si_dma_cs.c
index 673c3310a1a9582be34478a22acd29fcef20631e..195cc6468fca2019f64c94d89234eca5041929cf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_dma_cs.c
+++ b/src/gallium/drivers/radeonsi/si_dma_cs.c
@@ -74,7 +74,7 @@ void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, ui
    assert(size % 4 == 0);
 
    if (!cs || dst->flags & PIPE_RESOURCE_FLAG_SPARSE ||
    assert(size % 4 == 0);
 
    if (!cs || dst->flags & PIPE_RESOURCE_FLAG_SPARSE ||

-       sctx->screen->debug_flags & DBG(NO_SDMA_CLEARS)) {
+       sctx->screen->debug_flags & DBG(NO_SDMA_CLEARS) || sctx->ws->ws_is_secure(sctx->ws)) {

       sctx->b.clear_buffer(&sctx->b, dst, offset, size, &clear_value, 4);
       return;
    }
       sctx->b.clear_buffer(&sctx->b, dst, offset, size, &clear_value, 4);
       return;
    }


@@ -130,7 +130,8 @@ void si_sdma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
    struct si_resource *sdst = si_resource(dst);
    struct si_resource *ssrc = si_resource(src);
 
    struct si_resource *sdst = si_resource(dst);
    struct si_resource *ssrc = si_resource(src);
 

-   if (!cs || dst->flags & PIPE_RESOURCE_FLAG_SPARSE || src->flags & PIPE_RESOURCE_FLAG_SPARSE) {
+   if (!cs || dst->flags & PIPE_RESOURCE_FLAG_SPARSE || src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
+       (ssrc->flags & RADEON_FLAG_ENCRYPTED) != (sdst->flags & RADEON_FLAG_ENCRYPTED)) {

       si_copy_buffer(sctx, dst, src, dst_offset, src_offset, size);
       return;
    }
       si_copy_buffer(sctx, dst, src, dst_offset, src_offset, size);
       return;
    }


@@ -188,7 +189,8 @@ void si_sdma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
 
    for (i = 0; i < ncopy; i++) {
       csize = size >= 4 ? MIN2(size & align, CIK_SDMA_COPY_MAX_SIZE) : size;
 
    for (i = 0; i < ncopy; i++) {
       csize = size >= 4 ? MIN2(size & align, CIK_SDMA_COPY_MAX_SIZE) : size;

-      radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_LINEAR, 0));
+      radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
+                                      (sctx->ws->cs_is_secure(cs) ? 1u : 0) << 2));

       radeon_emit(cs, sctx->chip_class >= GFX9 ? csize - 1 : csize);
       radeon_emit(cs, 0); /* src/dst endian swap */
       radeon_emit(cs, src_offset);
       radeon_emit(cs, sctx->chip_class >= GFX9 ? csize - 1 : csize);
       radeon_emit(cs, 0); /* src/dst endian swap */
       radeon_emit(cs, src_offset);


@@ -223,6 +225,17 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct si_resour
         (src && ws->cs_is_buffer_referenced(ctx->gfx_cs, src->buf, RADEON_USAGE_WRITE))))
       si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 
         (src && ws->cs_is_buffer_referenced(ctx->gfx_cs, src->buf, RADEON_USAGE_WRITE))))
       si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 

+   bool use_secure_cmd = false;
+   /* if TMZ is supported and enabled */
+   if (ctx->ws->ws_is_secure(ctx->ws)) {
+      if (src && src->flags & RADEON_FLAG_ENCRYPTED) {
+         assert(!dst || (dst->flags & RADEON_FLAG_ENCRYPTED));
+         use_secure_cmd = true;
+      } else if (dst && (dst->flags & RADEON_FLAG_ENCRYPTED)) {
+         use_secure_cmd = true;
+      }
+   }
+

    /* Flush if there's not enough space, or if the memory usage per IB
     * is too large.
     *
    /* Flush if there's not enough space, or if the memory usage per IB
     * is too large.
     *


@@ -237,12 +250,14 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct si_resour
     */
    num_dw++; /* for emit_wait_idle below */
    if (!ctx->sdma_uploads_in_progress &&
     */
    num_dw++; /* for emit_wait_idle below */
    if (!ctx->sdma_uploads_in_progress &&

-       (!ws->cs_check_space(ctx->sdma_cs, num_dw, false) ||
+       (use_secure_cmd != ctx->ws->cs_is_secure(ctx->sdma_cs) ||
+        !ws->cs_check_space(ctx->sdma_cs, num_dw, false) ||

         ctx->sdma_cs->used_vram + ctx->sdma_cs->used_gart > 64 * 1024 * 1024 ||
         !radeon_cs_memory_below_limit(ctx->screen, ctx->sdma_cs, vram, gtt))) {
       si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
       assert((num_dw + ctx->sdma_cs->current.cdw) <= ctx->sdma_cs->current.max_dw);
    }
         ctx->sdma_cs->used_vram + ctx->sdma_cs->used_gart > 64 * 1024 * 1024 ||
         !radeon_cs_memory_below_limit(ctx->screen, ctx->sdma_cs, vram, gtt))) {
       si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
       assert((num_dw + ctx->sdma_cs->current.cdw) <= ctx->sdma_cs->current.max_dw);
    }

+   ctx->ws->cs_set_secure(ctx->sdma_cs, use_secure_cmd);

 
    /* Wait for idle if either buffer has been used in the IB before to
     * prevent read-after-write hazards.
 
    /* Wait for idle if either buffer has been used in the IB before to
     * prevent read-after-write hazards.

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 8856f0a75ced7f2f2cb6b56bb957032be2a8c8f9..46bdd4d5843f7057ec7601171dfe46e51096a7bf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -74,6 +74,13 @@ bool si_prepare_for_dma_blit(struct si_context *sctx, struct si_texture *dst, un
    if (vi_dcc_enabled(src, src_level) || vi_dcc_enabled(dst, dst_level))
       return false;
 
    if (vi_dcc_enabled(src, src_level) || vi_dcc_enabled(dst, dst_level))
       return false;
 

+   /* TMZ: mixing encrypted and non-encrypted buffer in a single command
+    * doesn't seem supported.
+    */
+   if ((src->buffer.flags & RADEON_FLAG_ENCRYPTED) !=
+       (dst->buffer.flags & RADEON_FLAG_ENCRYPTED))
+      return false;
+

    /* CMASK as:
     *   src: Both texture and SDMA paths need decompression. Use SDMA.
     *   dst: If overwriting the whole texture, discard CMASK and use
    /* CMASK as:
     *   src: Both texture and SDMA paths need decompression. Use SDMA.
     *   dst: If overwriting the whole texture, discard CMASK and use