freedreno/ir3/ra: fix pre-color edge case

Fixes a case where you have something like:

   aVecOutput.z = aScalarInput;

In particular, skipping over things that are not the first component is
wrong.. in the above case the input we need to precolor is the 3rd
component.  But we need to adjust the target register according to the
offset.

Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5601>

diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index c92436f8b21213ad9e7288cb92cf1a536f9eb3fa..254de0a7b2f3b6eabc28167424a0e9ebf49492bc 100644 (file)
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -1310,13 +1310,6 @@ ra_precolor(struct ir3_ra_ctx *ctx, struct ir3_instruction **precolor, unsigned
 
                        debug_assert(!(instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_HIGH)));
 
-                       /* only consider the first component: */
-                       if (id->off > 0)
-                               continue;
-
-                       if (ctx->scalar_pass && !should_assign(ctx, instr))
-                               continue;
-
                        /* 'base' is in scalar (class 0) but we need to map that
                         * the conflicting register of the appropriate class (ie.
                         * input could be vec2/vec3/etc)
@@ -1335,6 +1328,9 @@ ra_precolor(struct ir3_ra_ctx *ctx, struct ir3_instruction **precolor, unsigned
                         *           .. and so on..
                         */
                        unsigned regid = instr->regs[0]->num;
+                       assert(regid >= id->off);
+                       regid -= id->off;
+
                        unsigned reg = ctx->set->gpr_to_ra_reg[id->cls][regid];
                        unsigned name = ra_name(ctx, id);
                        ra_set_node_reg(ctx->g, name, reg);