i965/vec4/tes: consider register offsets during attribute setup

Reviewed-by: Matt Turner <mattst88@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
index bb81ad3a1559d4789b841b79e888333deebf4e04..ae6d99bed8305159342bef2240facbee3fcc83d2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
@@ -84,8 +84,8 @@ vec4_tes_visitor::setup_payload()
 
          bool is_64bit = type_sz(inst->src[i].type) == 8;
 
-         struct brw_reg grf =
-            brw_vec4_grf(reg + inst->src[i].nr / 2, 4 * (inst->src[i].nr % 2));
+         unsigned slot = inst->src[i].nr + inst->src[i].offset / 16;
+         struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2));
          grf = stride(grf, 0, is_64bit ? 2 : 4, 1);
          grf.swizzle = inst->src[i].swizzle;
          grf.type = inst->src[i].type;