freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
index 27405a6e47492faacf3a0af420229f6928a833d7..dfd196f779ae66a0ac9b7491a39c05e3af27925e 100644 (file)
--- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
+++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
@@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  28504 bytes, from 2017-04-21 20:00:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-01 19:45:59)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31541 bytes, from 2017-05-11 17:06:35)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 103235 bytes, from 2017-04-21 13:16:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 104446 bytes, from 2017-05-12 18:23:03)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-04-14 19:13:30)
 
 Copyright (C) 2013-2017 by the following authors:

diff --git a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
index dd5e1dfe69d1eb99b5959ff58cc5d69226c78006..f1157cdd9c2b8777e8f28e12bf00377a914d9fb5 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
+++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
@@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  28504 bytes, from 2017-04-21 20:00:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-01 19:45:59)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31541 bytes, from 2017-05-11 17:06:35)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 103235 bytes, from 2017-04-21 13:16:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 104446 bytes, from 2017-05-12 18:23:03)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-04-14 19:13:30)
 
 Copyright (C) 2013-2017 by the following authors:

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index 10b6691a65045b68838ddbe14c0d30fc1910c951..14a6e51717eacdfb1554a5da44007509a2cc1e1f 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  28504 bytes, from 2017-04-21 20:00:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-01 19:45:59)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31541 bytes, from 2017-05-11 17:06:35)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 103235 bytes, from 2017-04-21 13:16:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 104446 bytes, from 2017-05-12 18:23:03)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-04-14 19:13:30)
 
 Copyright (C) 2013-2017 by the following authors:

diff --git a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
index 44179ed9af8533dff731a52ac0d9f9d39c29b65b..b024ca0b0f7bfde4e0b934188dbdb7cd6a19aa6c 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
+++ b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
@@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  28504 bytes, from 2017-04-21 20:00:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-01 19:45:59)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31541 bytes, from 2017-05-11 17:06:35)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 103235 bytes, from 2017-04-21 13:16:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 104446 bytes, from 2017-05-12 18:23:03)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-04-14 19:13:30)
 
 Copyright (C) 2013-2017 by the following authors:
@@ -1341,25 +1341,85 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
 
 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL                        0x0000f810
 
-#define REG_A5XX_VSC_PIPE_DATA_LENGTH_0                                0x00000c00
+#define REG_A5XX_VSC_BIN_SIZE                                  0x00000bc2
+#define A5XX_VSC_BIN_SIZE_WIDTH__MASK                          0x000000ff
+#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT                         0
+static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
+{
+       assert(!(val & 0x1f));
+       return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
+}
+#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK                         0x0001fe00
+#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT                                9
+static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
+{
+       assert(!(val & 0x1f));
+       return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
+}
+
+#define REG_A5XX_VSC_SIZE_ADDRESS_LO                           0x00000bc3
+
+#define REG_A5XX_VSC_SIZE_ADDRESS_HI                           0x00000bc4
+
+#define REG_A5XX_UNKNOWN_0BC5                                  0x00000bc5
+
+#define REG_A5XX_UNKNOWN_0BC6                                  0x00000bc6
+
+static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
+#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK                       0x000003ff
+#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT                      0
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
+}
+#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK                       0x000ffc00
+#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT                      10
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
+}
+#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK                       0x00f00000
+#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT                      20
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
+}
+#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK                       0x0f000000
+#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT                      24
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
+}
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
 
 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0                         0x00000c60
 
 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1                         0x00000c61
 
-#define REG_A5XX_VSC_BIN_SIZE                                  0x00000cdd
-#define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE                        0x80000000
-#define A5XX_VSC_BIN_SIZE_X__MASK                              0x00007fff
-#define A5XX_VSC_BIN_SIZE_X__SHIFT                             0
-static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val)
+#define REG_A5XX_VSC_RESOLVE_CNTL                              0x00000cdd
+#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE            0x80000000
+#define A5XX_VSC_RESOLVE_CNTL_X__MASK                          0x00007fff
+#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT                         0
+static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
 {
-       return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK;
+       return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
 }
-#define A5XX_VSC_BIN_SIZE_Y__MASK                              0x7fff0000
-#define A5XX_VSC_BIN_SIZE_Y__SHIFT                             16
-static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
+#define A5XX_VSC_RESOLVE_CNTL_Y__MASK                          0x7fff0000
+#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT                         16
+static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
 {
-       return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK;
+       return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
 }
 
 #define REG_A5XX_GRAS_ADDR_MODE_CNTL                           0x00000c81
@@ -1522,6 +1582,7 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
 #define REG_A5XX_VPC_ADDR_MODE_CNTL                            0x00000e61
 
 #define REG_A5XX_VPC_MODE_CNTL                                 0x00000e62
+#define A5XX_VPC_MODE_CNTL_BINNING_PASS                                0x00000001
 
 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0                         0x00000e64
 
@@ -2107,6 +2168,7 @@ static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_dep
 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL                 0x0000e099
 
 #define REG_A5XX_GRAS_SC_CNTL                                  0x0000e0a0
+#define A5XX_GRAS_SC_CNTL_BINNING_PASS                         0x00000001
 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED                       0x00008000
 
 #define REG_A5XX_GRAS_SC_BIN_CNTL                              0x0000e0a1
@@ -2250,7 +2312,9 @@ static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
 #define A5XX_RB_CNTL_BYPASS                                    0x00020000
 
 #define REG_A5XX_RB_RENDER_CNTL                                        0x0000e141
+#define A5XX_RB_RENDER_CNTL_BINNING_PASS                       0x00000001
 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED                     0x00000040
+#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE                 0x00000080
 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH                         0x00004000
 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2                                0x00008000
 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK                    0x00ff0000

diff --git a/src/gallium/drivers/freedreno/adreno_common.xml.h b/src/gallium/drivers/freedreno/adreno_common.xml.h
index 7818a5b03cb0d82f3d6873cb52f0e1e896577163..4f8a870783b35f632d9a1c084b43f3d1f01ed514 100644 (file)
--- a/src/gallium/drivers/freedreno/adreno_common.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_common.xml.h
@@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  28504 bytes, from 2017-04-21 20:00:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-01 19:45:59)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31541 bytes, from 2017-05-11 17:06:35)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 103235 bytes, from 2017-04-21 13:16:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 104446 bytes, from 2017-05-12 18:23:03)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-04-14 19:13:30)
 
 Copyright (C) 2013-2017 by the following authors:
@@ -424,6 +424,35 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
 #define REG_AXXX_CP_IB2_BUFSZ                                  0x0000045b
 
 #define REG_AXXX_CP_STAT                                       0x0000047f
+#define AXXX_CP_STAT_CP_BUSY                                   0x80000000
+#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY                                0x40000000
+#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY                                0x20000000
+#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY                                0x10000000
+#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY                                0x08000000
+#define AXXX_CP_STAT_ME_BUSY                                   0x04000000
+#define AXXX_CP_STAT_MIU_WR_C_BUSY                             0x02000000
+#define AXXX_CP_STAT_CP_3D_BUSY                                        0x00800000
+#define AXXX_CP_STAT_CP_NRT_BUSY                               0x00400000
+#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY                         0x00200000
+#define AXXX_CP_STAT_RCIU_ME_BUSY                              0x00100000
+#define AXXX_CP_STAT_RCIU_PFP_BUSY                             0x00080000
+#define AXXX_CP_STAT_MEQ_RING_BUSY                             0x00040000
+#define AXXX_CP_STAT_PFP_BUSY                                  0x00020000
+#define AXXX_CP_STAT_ST_QUEUE_BUSY                             0x00010000
+#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY                      0x00002000
+#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY                      0x00001000
+#define AXXX_CP_STAT_RING_QUEUE_BUSY                           0x00000800
+#define AXXX_CP_STAT_CSF_BUSY                                  0x00000400
+#define AXXX_CP_STAT_CSF_ST_BUSY                               0x00000200
+#define AXXX_CP_STAT_EVENT_BUSY                                        0x00000100
+#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY                                0x00000080
+#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY                                0x00000040
+#define AXXX_CP_STAT_CSF_RING_BUSY                             0x00000020
+#define AXXX_CP_STAT_RCIU_BUSY                                 0x00000010
+#define AXXX_CP_STAT_RBIU_BUSY                                 0x00000008
+#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY                                0x00000004
+#define AXXX_CP_STAT_MIU_RD_REQ_BUSY                           0x00000002
+#define AXXX_CP_STAT_MIU_WR_BUSY                               0x00000001
 
 #define REG_AXXX_CP_SCRATCH_REG0                               0x00000578
 

diff --git a/src/gallium/drivers/freedreno/adreno_pm4.xml.h b/src/gallium/drivers/freedreno/adreno_pm4.xml.h
index 9452a9eddec753488613095da2f2607057981e63..e7ed75c0bb67fe08702c3a99c4d832fa7cd61141 100644 (file)
--- a/src/gallium/drivers/freedreno/adreno_pm4.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h
@@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  28504 bytes, from 2017-04-21 20:00:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-01 19:45:59)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31541 bytes, from 2017-05-11 17:06:35)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-04-14 19:13:31)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 103235 bytes, from 2017-04-21 13:16:50)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 104446 bytes, from 2017-05-12 18:23:03)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-04-14 19:13:30)
 
 Copyright (C) 2013-2017 by the following authors:
@@ -142,11 +142,13 @@ enum adreno_pm4_type3_packets {
        CP_WAIT_IB_PFD_COMPLETE = 93,
        CP_REG_RMW = 33,
        CP_SET_BIN_DATA = 47,
+       CP_SET_BIN_DATA5 = 47,
        CP_REG_TO_MEM = 62,
        CP_MEM_WRITE = 61,
        CP_MEM_WRITE_CNTR = 79,
        CP_COND_EXEC = 68,
        CP_COND_WRITE = 69,
+       CP_COND_WRITE5 = 69,
        CP_EVENT_WRITE = 70,
        CP_EVENT_WRITE_SHD = 88,
        CP_EVENT_WRITE_CFL = 89,
@@ -282,6 +284,16 @@ enum a4xx_index_size {
        INDEX4_SIZE_32_BIT = 2,
 };
 
+enum cp_cond_function {
+       WRITE_ALWAYS = 0,
+       WRITE_LT = 1,
+       WRITE_LE = 2,
+       WRITE_EQ = 3,
+       WRITE_NE = 4,
+       WRITE_GE = 5,
+       WRITE_GT = 6,
+};
+
 enum render_mode_cmd {
        BYPASS = 1,
        BINNING = 2,
@@ -650,6 +662,52 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
        return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
 }
 
+#define REG_CP_SET_BIN_DATA5_0                                 0x00000000
+#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK                      0x003f0000
+#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT                     16
+static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
+{
+       return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
+}
+#define CP_SET_BIN_DATA5_0_VSC_N__MASK                         0x07c00000
+#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT                                22
+static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
+{
+       return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
+}
+
+#define REG_CP_SET_BIN_DATA5_1                                 0x00000001
+#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK              0xffffffff
+#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT             0
+static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
+{
+       return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
+}
+
+#define REG_CP_SET_BIN_DATA5_2                                 0x00000002
+#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK              0xffffffff
+#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT             0
+static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
+{
+       return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
+}
+
+#define REG_CP_SET_BIN_DATA5_3                                 0x00000003
+#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK           0xffffffff
+#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT          0
+static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
+{
+       return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
+}
+
+#define REG_CP_SET_BIN_DATA5_4                                 0x00000004
+#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK           0xffffffff
+#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT          0
+static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
+{
+       return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
+}
+
 #define REG_CP_REG_TO_MEM_0                                    0x00000000
 #define CP_REG_TO_MEM_0_REG__MASK                              0x0000ffff
 #define CP_REG_TO_MEM_0_REG__SHIFT                             0
@@ -680,6 +738,122 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
 #define CP_MEM_TO_MEM_0_NEG_C                                  0x00000004
 #define CP_MEM_TO_MEM_0_DOUBLE                                 0x20000000
 
+#define REG_CP_COND_WRITE_0                                    0x00000000
+#define CP_COND_WRITE_0_FUNCTION__MASK                         0x00000007
+#define CP_COND_WRITE_0_FUNCTION__SHIFT                                0
+static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
+{
+       return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
+}
+#define CP_COND_WRITE_0_POLL_MEMORY                            0x00000010
+#define CP_COND_WRITE_0_WRITE_MEMORY                           0x00000100
+
+#define REG_CP_COND_WRITE_1                                    0x00000001
+#define CP_COND_WRITE_1_POLL_ADDR__MASK                                0xffffffff
+#define CP_COND_WRITE_1_POLL_ADDR__SHIFT                       0
+static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
+}
+
+#define REG_CP_COND_WRITE_2                                    0x00000002
+#define CP_COND_WRITE_2_REF__MASK                              0xffffffff
+#define CP_COND_WRITE_2_REF__SHIFT                             0
+static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
+}
+
+#define REG_CP_COND_WRITE_3                                    0x00000003
+#define CP_COND_WRITE_3_MASK__MASK                             0xffffffff
+#define CP_COND_WRITE_3_MASK__SHIFT                            0
+static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
+}
+
+#define REG_CP_COND_WRITE_4                                    0x00000004
+#define CP_COND_WRITE_4_WRITE_ADDR__MASK                       0xffffffff
+#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT                      0
+static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
+}
+
+#define REG_CP_COND_WRITE_5                                    0x00000005
+#define CP_COND_WRITE_5_WRITE_DATA__MASK                       0xffffffff
+#define CP_COND_WRITE_5_WRITE_DATA__SHIFT                      0
+static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
+}
+
+#define REG_CP_COND_WRITE5_0                                   0x00000000
+#define CP_COND_WRITE5_0_FUNCTION__MASK                                0x00000007
+#define CP_COND_WRITE5_0_FUNCTION__SHIFT                       0
+static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
+{
+       return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
+}
+#define CP_COND_WRITE5_0_POLL_MEMORY                           0x00000010
+#define CP_COND_WRITE5_0_WRITE_MEMORY                          0x00000100
+
+#define REG_CP_COND_WRITE5_1                                   0x00000001
+#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK                    0xffffffff
+#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT                   0
+static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
+}
+
+#define REG_CP_COND_WRITE5_2                                   0x00000002
+#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK                    0xffffffff
+#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT                   0
+static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
+}
+
+#define REG_CP_COND_WRITE5_3                                   0x00000003
+#define CP_COND_WRITE5_3_REF__MASK                             0xffffffff
+#define CP_COND_WRITE5_3_REF__SHIFT                            0
+static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
+}
+
+#define REG_CP_COND_WRITE5_4                                   0x00000004
+#define CP_COND_WRITE5_4_MASK__MASK                            0xffffffff
+#define CP_COND_WRITE5_4_MASK__SHIFT                           0
+static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
+}
+
+#define REG_CP_COND_WRITE5_5                                   0x00000005
+#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK                   0xffffffff
+#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT                  0
+static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
+}
+
+#define REG_CP_COND_WRITE5_6                                   0x00000006
+#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK                   0xffffffff
+#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT                  0
+static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
+}
+
+#define REG_CP_COND_WRITE5_7                                   0x00000007
+#define CP_COND_WRITE5_7_WRITE_DATA__MASK                      0xffffffff
+#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT                     0
+static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
+{
+       return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
+}
+
 #define REG_CP_DISPATCH_COMPUTE_0                              0x00000000
 
 #define REG_CP_DISPATCH_COMPUTE_1                              0x00000001
@@ -731,6 +905,7 @@ static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
 }
 
 #define REG_CP_SET_RENDER_MODE_3                               0x00000003
+#define CP_SET_RENDER_MODE_3_VSC_ENABLE                                0x00000008
 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE                       0x00000010
 
 #define REG_CP_SET_RENDER_MODE_4                               0x00000004