intel/blorp: Emit 3DSTATE_STENCIL_BUFFER before HIER_DEPTH

We're about to replace blorp's emit code with ISL and it emits them in
the other order.  This makes diffing the aubs easier.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 379146245d97ca661cade592dd29d138de54456b..9532e89b12f841f1107eb47a6d665c5aff822d0d 100644 (file)
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -854,18 +854,6 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
       }
    }
 
-   blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) {
-      if (params->depth.aux_usage == ISL_AUX_USAGE_HIZ) {
-         hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1;
-         hiz.SurfaceBaseAddress = params->depth.aux_addr;
-         hiz.HierarchicalDepthBufferMOCS = mocs;
-#if GEN_GEN >= 8
-         hiz.SurfaceQPitch =
-            isl_surf_get_array_pitch_sa_rows(&params->depth.aux_surf) >> 2;
-#endif
-      }
-   }
-
    blorp_emit(batch, GENX(3DSTATE_STENCIL_BUFFER), sb) {
       if (params->stencil.enabled) {
 #if GEN_GEN >= 8 || GEN_IS_HASWELL
@@ -883,6 +871,18 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
       }
    }
 
+   blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) {
+      if (params->depth.aux_usage == ISL_AUX_USAGE_HIZ) {
+         hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1;
+         hiz.SurfaceBaseAddress = params->depth.aux_addr;
+         hiz.HierarchicalDepthBufferMOCS = mocs;
+#if GEN_GEN >= 8
+         hiz.SurfaceQPitch =
+            isl_surf_get_array_pitch_sa_rows(&params->depth.aux_surf) >> 2;
+#endif
+      }
+   }
+
    /* 3DSTATE_CLEAR_PARAMS
     *
     * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS: