AC_FUNC_ATTR_READNONE);
}
+LLVMValueRef
+ac_build_canonicalize(struct ac_llvm_context *ctx, LLVMValueRef src0,
+ unsigned bitsize)
+{
+ LLVMTypeRef type;
+ char *intr;
+
+ if (bitsize == 16) {
+ intr = "llvm.canonicalize.f16";
+ type = ctx->f16;
+ } else if (bitsize == 32) {
+ intr = "llvm.canonicalize.f32";
+ type = ctx->f32;
+ } else if (bitsize == 64) {
+ intr = "llvm.canonicalize.f64";
+ type = ctx->f64;
+ }
+
+ LLVMValueRef params[] = {
+ src0,
+ };
+ return ac_build_intrinsic(ctx, intr, type, params, 1,
+ AC_FUNC_ATTR_READNONE);
+}
+
/*
* this takes an I,J coordinate pair,
* and works out the X and Y derivatives.
ac_build_frexp_mant(struct ac_llvm_context *ctx, LLVMValueRef src0,
unsigned bitsize);
+LLVMValueRef
+ac_build_canonicalize(struct ac_llvm_context *ctx, LLVMValueRef src0,
+ unsigned bitsize);
+
LLVMValueRef
ac_build_ddxy_interp(struct ac_llvm_context *ctx, LLVMValueRef interp_ij);
if (ctx->ac.chip_class < GFX9 &&
instr->dest.dest.ssa.bit_size == 32) {
/* Only pre-GFX9 chips do not flush denorms. */
- result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
- ac_to_float_type(&ctx->ac, def_type),
- result);
+ result = ac_build_canonicalize(&ctx->ac, result,
+ instr->dest.dest.ssa.bit_size);
}
break;
case nir_op_fmin:
if (ctx->ac.chip_class < GFX9 &&
instr->dest.dest.ssa.bit_size == 32) {
/* Only pre-GFX9 chips do not flush denorms. */
- result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
- ac_to_float_type(&ctx->ac, def_type),
- result);
+ result = ac_build_canonicalize(&ctx->ac, result,
+ instr->dest.dest.ssa.bit_size);
}
break;
case nir_op_ffma: