radeonsi: set VGT_GS_ONCHIP_CNTL on CIK and later

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 11.2 12.0 13.0  <mesa-stable@lists.freedesktop.org>

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 42689da79fb05964eb4adbccf455a6bff4015dda..0633b64de3343732c00d19632090601bdd030b37 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3925,6 +3925,14 @@ static void si_init_config(struct si_context *sctx)
        si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
 
        if (sctx->b.chip_class >= CIK) {
+               /* If this is 0, Bonaire can hang even if GS isn't being used.
+                * Other chips are unaffected. These are suboptimal values,
+                * but we don't use on-chip GS.
+                */
+               si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
+                              S_028A44_ES_VERTS_PER_SUBGRP(64) |
+                              S_028A44_GS_PRIMS_PER_SUBGRP(4));
+
                si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
                si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
                si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));