GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE |
GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
GEN6_PIPE_CONTROL_CS_STALL;
+ const unsigned batch_used = ilo_builder_batch_used(render->builder);
ILO_DEV_ASSERT(render->dev, 6, 7.5);
render->state.current_pipe_control_dw1 |= dw1;
render->state.deferred_pipe_control_dw1 &= ~dw1;
+
+ assert(ilo_builder_batch_used(render->builder) <= batch_used +
+ ilo_render_get_flush_len(render));
}
/**
(ilo_dev_gen(render->dev) >= ILO_GEN(7)) ?
GEN7_REG_SO_NUM_PRIMS_WRITTEN(q->index) :
GEN6_REG_SO_NUM_PRIMS_WRITTEN;
+ const unsigned batch_used = ilo_builder_batch_used(render->builder);
const uint32_t *regs;
int reg_count = 0, i;
uint32_t pipe_control_dw1 = 0;
}
if (pipe_control_dw1) {
+ assert(!reg_count);
+
if (ilo_dev_gen(render->dev) == ILO_GEN(6))
gen6_wa_pre_pipe_control(render, pipe_control_dw1);
render->state.current_pipe_control_dw1 |= pipe_control_dw1;
render->state.deferred_pipe_control_dw1 &= ~pipe_control_dw1;
+ } else if (reg_count) {
+ ilo_render_emit_flush(render);
}
- if (!reg_count)
- return;
-
- ilo_render_emit_flush(render);
-
for (i = 0; i < reg_count; i++) {
if (regs[i]) {
/* store lower 32 bits */
offset += 8;
}
+
+ assert(ilo_builder_batch_used(render->builder) <= batch_used +
+ ilo_render_get_query_len(render, q->type));
}