i965: Set "Stencil Buffer Enable" bit on Haswell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index a0931121475f1300f3d3f81f96449b9c954e00d0..e7326c6ca3fb0d797129c81232d614e5c68f9140 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1445,6 +1445,7 @@ enum brw_wm_barycentric_interp_mode {
 #define GEN7_3DSTATE_CLEAR_PARAMS              0x7804
 #define GEN7_3DSTATE_DEPTH_BUFFER              0x7805
 #define GEN7_3DSTATE_STENCIL_BUFFER            0x7806
+# define HSW_STENCIL_ENABLED                            (1 << 31)
 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER         0x7807
 
 #define _3DSTATE_CLEAR_PARAMS                  0x7910 /* ILK, SNB */

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index d0ce54241b6aa4d55e2246abbeb5479b3257a52e..5da64349e5ac7389ce6ce0982faba4a6c437c8c7 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -139,9 +139,12 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
+      const int enabled = intel->is_haswell ? HSW_STENCIL_ENABLED : 0;
+
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
-      OUT_BATCH(stencil_mt->region->pitch * stencil_mt->region->cpp - 1);
+      OUT_BATCH(enabled |
+               (stencil_mt->region->pitch * stencil_mt->region->cpp - 1));
       OUT_RELOC(stencil_mt->region->bo,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                0);