#include "xf86drm.h"
#include "dri2.h"
#include "dri_common.h"
-#include "../../mesa/drivers/dri/common/dri_util.h"
+
+/* From xmlpool/options.h, user exposed so should be stable */
+#define DRI_CONF_VBLANK_NEVER 0
+#define DRI_CONF_VBLANK_DEF_INTERVAL_0 1
+#define DRI_CONF_VBLANK_DEF_INTERVAL_1 2
+#define DRI_CONF_VBLANK_ALWAYS_SYNC 3
#undef DRI2_MINOR
#define DRI2_MINOR 1
__GLXDRIconfigPrivate *config = (__GLXDRIconfigPrivate *) modes;
__GLXdisplayPrivate *dpyPriv;
__GLXDRIdisplayPrivate *pdp;
+ GLint vblank_mode = DRI_CONF_VBLANK_DEF_INTERVAL_1;
pdraw = Xmalloc(sizeof(*pdraw));
if (!pdraw)
pdraw->base.drawable = drawable;
pdraw->base.psc = psc;
pdraw->bufferCount = 0;
- pdraw->swap_interval = 1;
+ pdraw->swap_interval = 1; /* default may be overridden below */
+
+ if (psc->config)
+ psc->config->configQueryi(psc->__driScreen, "vblank_mode", &vblank_mode);
+
+ switch (vblank_mode) {
+ case DRI_CONF_VBLANK_NEVER:
+ case DRI_CONF_VBLANK_DEF_INTERVAL_0:
+ pdraw->swap_interval = 0;
+ break;
+ case DRI_CONF_VBLANK_DEF_INTERVAL_1:
+ case DRI_CONF_VBLANK_ALWAYS_SYNC:
+ default:
+ pdraw->swap_interval = 1;
+ break;
+ }
DRI2CreateDrawable(psc->dpy, xDrawable);
return NULL;
}
+ #ifdef X_DRI2SwapInterval
/*
* Make sure server has the same swap interval we do for the new
* drawable.
*/
if (pdp->swapAvailable)
DRI2SwapInterval(psc->dpy, xDrawable, pdraw->swap_interval);
+ #endif
return &pdraw->base;
}
static void
dri2SetSwapInterval(__GLXDRIdrawable *pdraw, int interval)
{
+ __GLXscreenConfigs *psc = pdraw->psc;
__GLXDRIdrawablePrivate *priv = (__GLXDRIdrawablePrivate *) pdraw;
+ GLint vblank_mode = DRI_CONF_VBLANK_DEF_INTERVAL_1;
+
+ if (psc->config)
+ psc->config->configQueryi(psc->__driScreen, "vblank_mode", &vblank_mode);
+
+ switch (vblank_mode) {
+ case DRI_CONF_VBLANK_NEVER:
+ return;
+ case DRI_CONF_VBLANK_ALWAYS_SYNC:
+ if (interval <= 0)
+ return;
+ break;
+ default:
+ break;
+ }
DRI2SwapInterval(priv->base.psc->dpy, pdraw->xDrawable, interval);
priv->swap_interval = interval;
case PCI_CHIP_RV380_3150:
case PCI_CHIP_RV380_3152:
case PCI_CHIP_RV380_3154:
+ case PCI_CHIP_RV380_3155:
case PCI_CHIP_RV380_3E50:
case PCI_CHIP_RV380_3E54:
screen->chip_family = CHIP_FAMILY_RV380;
/* pipe overrides */
switch (dri_priv->deviceID) {
case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
+ case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
screen->num_gb_pipes = 1;
screen->extensions[i++] = &r600texOffsetExtension.base;
#endif
+ screen->extensions[i++] = &dri2ConfigQueryExtension.base;
+
screen->extensions[i++] = NULL;
sPriv->extensions = screen->extensions;
/* pipe overrides */
switch (device_id) {
case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
+ case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
screen->num_gb_pipes = 1;